/*! @file */
/*! @brief enums */
#define AMED_AARCH64_IFORM_MAX_TEXT_LENGTH (11 + 1)

typedef enum _amed_aarch64_iform
{
  AMED_AARCH64_IFORM_NONE,
  AMED_AARCH64_IFORM_INVALID,
  AMED_AARCH64_IFORM_ADCr,
  AMED_AARCH64_IFORM_ADCSr,
  AMED_AARCH64_IFORM_ADDr,
  AMED_AARCH64_IFORM_ADDri,
  AMED_AARCH64_IFORM_ADDGri,
  AMED_AARCH64_IFORM_ADDSr,
  AMED_AARCH64_IFORM_ADDSri,
  AMED_AARCH64_IFORM_ADRr,
  AMED_AARCH64_IFORM_ADRPr,
  AMED_AARCH64_IFORM_ANDri,
  AMED_AARCH64_IFORM_ANDr,
  AMED_AARCH64_IFORM_ANDSri,
  AMED_AARCH64_IFORM_ANDSr,
  AMED_AARCH64_IFORM_ASRVr,
  AMED_AARCH64_IFORM_AUTDAr,
  AMED_AARCH64_IFORM_AUTDZAr,
  AMED_AARCH64_IFORM_AUTDBr,
  AMED_AARCH64_IFORM_AUTDZBr,
  AMED_AARCH64_IFORM_AUTIAr,
  AMED_AARCH64_IFORM_AUTIZAr,
  AMED_AARCH64_IFORM_AUTIA1716,
  AMED_AARCH64_IFORM_AUTIASP,
  AMED_AARCH64_IFORM_AUTIAZ,
  AMED_AARCH64_IFORM_AUTIBr,
  AMED_AARCH64_IFORM_AUTIZBr,
  AMED_AARCH64_IFORM_AUTIB1716,
  AMED_AARCH64_IFORM_AUTIBSP,
  AMED_AARCH64_IFORM_AUTIBZ,
  AMED_AARCH64_IFORM_AXFLAG,
  AMED_AARCH64_IFORM_B,
  AMED_AARCH64_IFORM_BFMri,
  AMED_AARCH64_IFORM_BICr,
  AMED_AARCH64_IFORM_BICSr,
  AMED_AARCH64_IFORM_BL,
  AMED_AARCH64_IFORM_BLRr,
  AMED_AARCH64_IFORM_BLRAAZr,
  AMED_AARCH64_IFORM_BLRAAr,
  AMED_AARCH64_IFORM_BLRABZr,
  AMED_AARCH64_IFORM_BLRABr,
  AMED_AARCH64_IFORM_BRr,
  AMED_AARCH64_IFORM_BRAAZr,
  AMED_AARCH64_IFORM_BRAAr,
  AMED_AARCH64_IFORM_BRABZr,
  AMED_AARCH64_IFORM_BRABr,
  AMED_AARCH64_IFORM_BRKi,
  AMED_AARCH64_IFORM_BTI,
  AMED_AARCH64_IFORM_CASrm,
  AMED_AARCH64_IFORM_CASArm,
  AMED_AARCH64_IFORM_CASALrm,
  AMED_AARCH64_IFORM_CASLrm,
  AMED_AARCH64_IFORM_CASABrm,
  AMED_AARCH64_IFORM_CASALBrm,
  AMED_AARCH64_IFORM_CASBrm,
  AMED_AARCH64_IFORM_CASLBrm,
  AMED_AARCH64_IFORM_CASAHrm,
  AMED_AARCH64_IFORM_CASALHrm,
  AMED_AARCH64_IFORM_CASHrm,
  AMED_AARCH64_IFORM_CASLHrm,
  AMED_AARCH64_IFORM_CASPrm,
  AMED_AARCH64_IFORM_CASPArm,
  AMED_AARCH64_IFORM_CASPALrm,
  AMED_AARCH64_IFORM_CASPLrm,
  AMED_AARCH64_IFORM_CBNZr,
  AMED_AARCH64_IFORM_CBZr,
  AMED_AARCH64_IFORM_CCMNri,
  AMED_AARCH64_IFORM_CCMPri,
  AMED_AARCH64_IFORM_CFINV,
  AMED_AARCH64_IFORM_CLREXi,
  AMED_AARCH64_IFORM_CLSr,
  AMED_AARCH64_IFORM_CLZr,
  AMED_AARCH64_IFORM_CRC32Br,
  AMED_AARCH64_IFORM_CRC32Hr,
  AMED_AARCH64_IFORM_CRC32Wr,
  AMED_AARCH64_IFORM_CRC32Xr,
  AMED_AARCH64_IFORM_CRC32CBr,
  AMED_AARCH64_IFORM_CRC32CHr,
  AMED_AARCH64_IFORM_CRC32CWr,
  AMED_AARCH64_IFORM_CRC32CXr,
  AMED_AARCH64_IFORM_CSDB,
  AMED_AARCH64_IFORM_CSELr,
  AMED_AARCH64_IFORM_CSINCr,
  AMED_AARCH64_IFORM_CSINVr,
  AMED_AARCH64_IFORM_CSNEGr,
  AMED_AARCH64_IFORM_DCPS1i,
  AMED_AARCH64_IFORM_DCPS2i,
  AMED_AARCH64_IFORM_DCPS3i,
  AMED_AARCH64_IFORM_DGH,
  AMED_AARCH64_IFORM_DMB,
  AMED_AARCH64_IFORM_DRPS,
  AMED_AARCH64_IFORM_DSB,
  AMED_AARCH64_IFORM_EONr,
  AMED_AARCH64_IFORM_EORri,
  AMED_AARCH64_IFORM_EORr,
  AMED_AARCH64_IFORM_ERET,
  AMED_AARCH64_IFORM_ERETAA,
  AMED_AARCH64_IFORM_ERETAB,
  AMED_AARCH64_IFORM_ESB,
  AMED_AARCH64_IFORM_EXTRri,
  AMED_AARCH64_IFORM_GMIr,
  AMED_AARCH64_IFORM_HINTi,
  AMED_AARCH64_IFORM_HLTi,
  AMED_AARCH64_IFORM_HVCi,
  AMED_AARCH64_IFORM_IRGr,
  AMED_AARCH64_IFORM_ISB,
  AMED_AARCH64_IFORM_LDADDrm,
  AMED_AARCH64_IFORM_LDADDArm,
  AMED_AARCH64_IFORM_LDADDALrm,
  AMED_AARCH64_IFORM_LDADDLrm,
  AMED_AARCH64_IFORM_LDADDABrm,
  AMED_AARCH64_IFORM_LDADDALBrm,
  AMED_AARCH64_IFORM_LDADDBrm,
  AMED_AARCH64_IFORM_LDADDLBrm,
  AMED_AARCH64_IFORM_LDADDAHrm,
  AMED_AARCH64_IFORM_LDADDALHrm,
  AMED_AARCH64_IFORM_LDADDHrm,
  AMED_AARCH64_IFORM_LDADDLHrm,
  AMED_AARCH64_IFORM_LDAPRrm,
  AMED_AARCH64_IFORM_LDAPRBrm,
  AMED_AARCH64_IFORM_LDAPRHrm,
  AMED_AARCH64_IFORM_LDAPURrm,
  AMED_AARCH64_IFORM_LDAPURBrm,
  AMED_AARCH64_IFORM_LDAPURHrm,
  AMED_AARCH64_IFORM_LDAPURSBrm,
  AMED_AARCH64_IFORM_LDAPURSHrm,
  AMED_AARCH64_IFORM_LDAPURSWrm,
  AMED_AARCH64_IFORM_LDARrm,
  AMED_AARCH64_IFORM_LDARBrm,
  AMED_AARCH64_IFORM_LDARHrm,
  AMED_AARCH64_IFORM_LDAXPrm,
  AMED_AARCH64_IFORM_LDAXRrm,
  AMED_AARCH64_IFORM_LDAXRBrm,
  AMED_AARCH64_IFORM_LDAXRHrm,
  AMED_AARCH64_IFORM_LDCLRrm,
  AMED_AARCH64_IFORM_LDCLRArm,
  AMED_AARCH64_IFORM_LDCLRALrm,
  AMED_AARCH64_IFORM_LDCLRLrm,
  AMED_AARCH64_IFORM_LDCLRABrm,
  AMED_AARCH64_IFORM_LDCLRALBrm,
  AMED_AARCH64_IFORM_LDCLRBrm,
  AMED_AARCH64_IFORM_LDCLRLBrm,
  AMED_AARCH64_IFORM_LDCLRAHrm,
  AMED_AARCH64_IFORM_LDCLRALHrm,
  AMED_AARCH64_IFORM_LDCLRHrm,
  AMED_AARCH64_IFORM_LDCLRLHrm,
  AMED_AARCH64_IFORM_LDEORrm,
  AMED_AARCH64_IFORM_LDEORArm,
  AMED_AARCH64_IFORM_LDEORALrm,
  AMED_AARCH64_IFORM_LDEORLrm,
  AMED_AARCH64_IFORM_LDEORABrm,
  AMED_AARCH64_IFORM_LDEORALBrm,
  AMED_AARCH64_IFORM_LDEORBrm,
  AMED_AARCH64_IFORM_LDEORLBrm,
  AMED_AARCH64_IFORM_LDEORAHrm,
  AMED_AARCH64_IFORM_LDEORALHrm,
  AMED_AARCH64_IFORM_LDEORHrm,
  AMED_AARCH64_IFORM_LDEORLHrm,
  AMED_AARCH64_IFORM_LDGrm,
  AMED_AARCH64_IFORM_LDGMrm,
  AMED_AARCH64_IFORM_LDLARrm,
  AMED_AARCH64_IFORM_LDLARBrm,
  AMED_AARCH64_IFORM_LDLARHrm,
  AMED_AARCH64_IFORM_LDNPrm,
  AMED_AARCH64_IFORM_LDPrm,
  AMED_AARCH64_IFORM_LDPSWrm,
  AMED_AARCH64_IFORM_LDRrm,
  AMED_AARCH64_IFORM_LDRr,
  AMED_AARCH64_IFORM_LDRAArm,
  AMED_AARCH64_IFORM_LDRABrm,
  AMED_AARCH64_IFORM_LDRBrm,
  AMED_AARCH64_IFORM_LDRHrm,
  AMED_AARCH64_IFORM_LDRSBrm,
  AMED_AARCH64_IFORM_LDRSHrm,
  AMED_AARCH64_IFORM_LDRSWrm,
  AMED_AARCH64_IFORM_LDRSWr,
  AMED_AARCH64_IFORM_LDSETrm,
  AMED_AARCH64_IFORM_LDSETArm,
  AMED_AARCH64_IFORM_LDSETALrm,
  AMED_AARCH64_IFORM_LDSETLrm,
  AMED_AARCH64_IFORM_LDSETABrm,
  AMED_AARCH64_IFORM_LDSETALBrm,
  AMED_AARCH64_IFORM_LDSETBrm,
  AMED_AARCH64_IFORM_LDSETLBrm,
  AMED_AARCH64_IFORM_LDSETAHrm,
  AMED_AARCH64_IFORM_LDSETALHrm,
  AMED_AARCH64_IFORM_LDSETHrm,
  AMED_AARCH64_IFORM_LDSETLHrm,
  AMED_AARCH64_IFORM_LDSMAXrm,
  AMED_AARCH64_IFORM_LDSMAXArm,
  AMED_AARCH64_IFORM_LDSMAXALrm,
  AMED_AARCH64_IFORM_LDSMAXLrm,
  AMED_AARCH64_IFORM_LDSMAXABrm,
  AMED_AARCH64_IFORM_LDSMAXALBrm,
  AMED_AARCH64_IFORM_LDSMAXBrm,
  AMED_AARCH64_IFORM_LDSMAXLBrm,
  AMED_AARCH64_IFORM_LDSMAXAHrm,
  AMED_AARCH64_IFORM_LDSMAXALHrm,
  AMED_AARCH64_IFORM_LDSMAXHrm,
  AMED_AARCH64_IFORM_LDSMAXLHrm,
  AMED_AARCH64_IFORM_LDSMINrm,
  AMED_AARCH64_IFORM_LDSMINArm,
  AMED_AARCH64_IFORM_LDSMINALrm,
  AMED_AARCH64_IFORM_LDSMINLrm,
  AMED_AARCH64_IFORM_LDSMINABrm,
  AMED_AARCH64_IFORM_LDSMINALBrm,
  AMED_AARCH64_IFORM_LDSMINBrm,
  AMED_AARCH64_IFORM_LDSMINLBrm,
  AMED_AARCH64_IFORM_LDSMINAHrm,
  AMED_AARCH64_IFORM_LDSMINALHrm,
  AMED_AARCH64_IFORM_LDSMINHrm,
  AMED_AARCH64_IFORM_LDSMINLHrm,
  AMED_AARCH64_IFORM_LDTRrm,
  AMED_AARCH64_IFORM_LDTRBrm,
  AMED_AARCH64_IFORM_LDTRHrm,
  AMED_AARCH64_IFORM_LDTRSBrm,
  AMED_AARCH64_IFORM_LDTRSHrm,
  AMED_AARCH64_IFORM_LDTRSWrm,
  AMED_AARCH64_IFORM_LDUMAXrm,
  AMED_AARCH64_IFORM_LDUMAXArm,
  AMED_AARCH64_IFORM_LDUMAXALrm,
  AMED_AARCH64_IFORM_LDUMAXLrm,
  AMED_AARCH64_IFORM_LDUMAXABrm,
  AMED_AARCH64_IFORM_LDUMAXALBrm,
  AMED_AARCH64_IFORM_LDUMAXBrm,
  AMED_AARCH64_IFORM_LDUMAXLBrm,
  AMED_AARCH64_IFORM_LDUMAXAHrm,
  AMED_AARCH64_IFORM_LDUMAXALHrm,
  AMED_AARCH64_IFORM_LDUMAXHrm,
  AMED_AARCH64_IFORM_LDUMAXLHrm,
  AMED_AARCH64_IFORM_LDUMINrm,
  AMED_AARCH64_IFORM_LDUMINArm,
  AMED_AARCH64_IFORM_LDUMINALrm,
  AMED_AARCH64_IFORM_LDUMINLrm,
  AMED_AARCH64_IFORM_LDUMINABrm,
  AMED_AARCH64_IFORM_LDUMINALBrm,
  AMED_AARCH64_IFORM_LDUMINBrm,
  AMED_AARCH64_IFORM_LDUMINLBrm,
  AMED_AARCH64_IFORM_LDUMINAHrm,
  AMED_AARCH64_IFORM_LDUMINALHrm,
  AMED_AARCH64_IFORM_LDUMINHrm,
  AMED_AARCH64_IFORM_LDUMINLHrm,
  AMED_AARCH64_IFORM_LDURrm,
  AMED_AARCH64_IFORM_LDURBrm,
  AMED_AARCH64_IFORM_LDURHrm,
  AMED_AARCH64_IFORM_LDURSBrm,
  AMED_AARCH64_IFORM_LDURSHrm,
  AMED_AARCH64_IFORM_LDURSWrm,
  AMED_AARCH64_IFORM_LDXPrm,
  AMED_AARCH64_IFORM_LDXRrm,
  AMED_AARCH64_IFORM_LDXRBrm,
  AMED_AARCH64_IFORM_LDXRHrm,
  AMED_AARCH64_IFORM_LSLVr,
  AMED_AARCH64_IFORM_LSRVr,
  AMED_AARCH64_IFORM_MADDr,
  AMED_AARCH64_IFORM_MOVKri,
  AMED_AARCH64_IFORM_MOVNri,
  AMED_AARCH64_IFORM_MOVZri,
  AMED_AARCH64_IFORM_MRSr,
  AMED_AARCH64_IFORM_MSRi,
  AMED_AARCH64_IFORM_MSRr,
  AMED_AARCH64_IFORM_MSUBr,
  AMED_AARCH64_IFORM_NOP,
  AMED_AARCH64_IFORM_ORNr,
  AMED_AARCH64_IFORM_ORRri,
  AMED_AARCH64_IFORM_ORRr,
  AMED_AARCH64_IFORM_PACDAr,
  AMED_AARCH64_IFORM_PACDZAr,
  AMED_AARCH64_IFORM_PACDBr,
  AMED_AARCH64_IFORM_PACDZBr,
  AMED_AARCH64_IFORM_PACGAr,
  AMED_AARCH64_IFORM_PACIAr,
  AMED_AARCH64_IFORM_PACIZAr,
  AMED_AARCH64_IFORM_PACIA1716,
  AMED_AARCH64_IFORM_PACIASP,
  AMED_AARCH64_IFORM_PACIAZ,
  AMED_AARCH64_IFORM_PACIBr,
  AMED_AARCH64_IFORM_PACIZBr,
  AMED_AARCH64_IFORM_PACIB1716,
  AMED_AARCH64_IFORM_PACIBSP,
  AMED_AARCH64_IFORM_PACIBZ,
  AMED_AARCH64_IFORM_PRFMm,
  AMED_AARCH64_IFORM_PRFM,
  AMED_AARCH64_IFORM_PRFUMm,
  AMED_AARCH64_IFORM_PSB,
  AMED_AARCH64_IFORM_PSSBB,
  AMED_AARCH64_IFORM_RBITr,
  AMED_AARCH64_IFORM_RETr,
  AMED_AARCH64_IFORM_RETAA,
  AMED_AARCH64_IFORM_RETAB,
  AMED_AARCH64_IFORM_REVr,
  AMED_AARCH64_IFORM_REV16r,
  AMED_AARCH64_IFORM_REV32r,
  AMED_AARCH64_IFORM_RMIFri,
  AMED_AARCH64_IFORM_RORVr,
  AMED_AARCH64_IFORM_SB,
  AMED_AARCH64_IFORM_SBCr,
  AMED_AARCH64_IFORM_SBCSr,
  AMED_AARCH64_IFORM_SBFMri,
  AMED_AARCH64_IFORM_SDIVr,
  AMED_AARCH64_IFORM_SETF8r,
  AMED_AARCH64_IFORM_SETF16r,
  AMED_AARCH64_IFORM_SEV,
  AMED_AARCH64_IFORM_SEVL,
  AMED_AARCH64_IFORM_SMADDLr,
  AMED_AARCH64_IFORM_SMCi,
  AMED_AARCH64_IFORM_SMSUBLr,
  AMED_AARCH64_IFORM_SMULHr,
  AMED_AARCH64_IFORM_SSBB,
  AMED_AARCH64_IFORM_ST2Grm,
  AMED_AARCH64_IFORM_STGrm,
  AMED_AARCH64_IFORM_STGMrm,
  AMED_AARCH64_IFORM_STGPrm,
  AMED_AARCH64_IFORM_STLLRrm,
  AMED_AARCH64_IFORM_STLLRBrm,
  AMED_AARCH64_IFORM_STLLRHrm,
  AMED_AARCH64_IFORM_STLRrm,
  AMED_AARCH64_IFORM_STLRBrm,
  AMED_AARCH64_IFORM_STLRHrm,
  AMED_AARCH64_IFORM_STLURrm,
  AMED_AARCH64_IFORM_STLURBrm,
  AMED_AARCH64_IFORM_STLURHrm,
  AMED_AARCH64_IFORM_STLXPrm,
  AMED_AARCH64_IFORM_STLXRrm,
  AMED_AARCH64_IFORM_STLXRBrm,
  AMED_AARCH64_IFORM_STLXRHrm,
  AMED_AARCH64_IFORM_STNPrm,
  AMED_AARCH64_IFORM_STPrm,
  AMED_AARCH64_IFORM_STRrm,
  AMED_AARCH64_IFORM_STRBrm,
  AMED_AARCH64_IFORM_STRHrm,
  AMED_AARCH64_IFORM_STTRrm,
  AMED_AARCH64_IFORM_STTRBrm,
  AMED_AARCH64_IFORM_STTRHrm,
  AMED_AARCH64_IFORM_STURrm,
  AMED_AARCH64_IFORM_STURBrm,
  AMED_AARCH64_IFORM_STURHrm,
  AMED_AARCH64_IFORM_STXPrm,
  AMED_AARCH64_IFORM_STXRrm,
  AMED_AARCH64_IFORM_STXRBrm,
  AMED_AARCH64_IFORM_STXRHrm,
  AMED_AARCH64_IFORM_STZ2Grm,
  AMED_AARCH64_IFORM_STZGrm,
  AMED_AARCH64_IFORM_STZGMrm,
  AMED_AARCH64_IFORM_SUBr,
  AMED_AARCH64_IFORM_SUBri,
  AMED_AARCH64_IFORM_SUBGri,
  AMED_AARCH64_IFORM_SUBPr,
  AMED_AARCH64_IFORM_SUBPSr,
  AMED_AARCH64_IFORM_SUBSr,
  AMED_AARCH64_IFORM_SUBSri,
  AMED_AARCH64_IFORM_SVCi,
  AMED_AARCH64_IFORM_SWPrm,
  AMED_AARCH64_IFORM_SWPArm,
  AMED_AARCH64_IFORM_SWPALrm,
  AMED_AARCH64_IFORM_SWPLrm,
  AMED_AARCH64_IFORM_SWPABrm,
  AMED_AARCH64_IFORM_SWPALBrm,
  AMED_AARCH64_IFORM_SWPBrm,
  AMED_AARCH64_IFORM_SWPLBrm,
  AMED_AARCH64_IFORM_SWPAHrm,
  AMED_AARCH64_IFORM_SWPALHrm,
  AMED_AARCH64_IFORM_SWPHrm,
  AMED_AARCH64_IFORM_SWPLHrm,
  AMED_AARCH64_IFORM_SYSir,
  AMED_AARCH64_IFORM_SYSLri,
  AMED_AARCH64_IFORM_TBNZri,
  AMED_AARCH64_IFORM_TBZri,
  AMED_AARCH64_IFORM_TCANCELi,
  AMED_AARCH64_IFORM_TCOMMIT,
  AMED_AARCH64_IFORM_TSB,
  AMED_AARCH64_IFORM_TSTARTr,
  AMED_AARCH64_IFORM_TTESTr,
  AMED_AARCH64_IFORM_UBFMri,
  AMED_AARCH64_IFORM_UDFi,
  AMED_AARCH64_IFORM_UDIVr,
  AMED_AARCH64_IFORM_UMADDLr,
  AMED_AARCH64_IFORM_UMSUBLr,
  AMED_AARCH64_IFORM_UMULHr,
  AMED_AARCH64_IFORM_WFE,
  AMED_AARCH64_IFORM_WFI,
  AMED_AARCH64_IFORM_XAFLAG,
  AMED_AARCH64_IFORM_XPACDr,
  AMED_AARCH64_IFORM_XPACIr,
  AMED_AARCH64_IFORM_XPACLRI,
  AMED_AARCH64_IFORM_YIELD,
  AMED_AARCH64_IFORM_ASRr,
  AMED_AARCH64_IFORM_ASRri,
  AMED_AARCH64_IFORM_ATr,
  AMED_AARCH64_IFORM_BFCri,
  AMED_AARCH64_IFORM_BFIri,
  AMED_AARCH64_IFORM_BFXILri,
  AMED_AARCH64_IFORM_CFPr,
  AMED_AARCH64_IFORM_CINCr,
  AMED_AARCH64_IFORM_CINVr,
  AMED_AARCH64_IFORM_CMNr,
  AMED_AARCH64_IFORM_CMNri,
  AMED_AARCH64_IFORM_CMPr,
  AMED_AARCH64_IFORM_CMPri,
  AMED_AARCH64_IFORM_CMPPr,
  AMED_AARCH64_IFORM_CNEGr,
  AMED_AARCH64_IFORM_CPPr,
  AMED_AARCH64_IFORM_CSETr,
  AMED_AARCH64_IFORM_CSETMr,
  AMED_AARCH64_IFORM_DCr,
  AMED_AARCH64_IFORM_DFB,
  AMED_AARCH64_IFORM_DVPr,
  AMED_AARCH64_IFORM_ICr,
  AMED_AARCH64_IFORM_LSLr,
  AMED_AARCH64_IFORM_LSLri,
  AMED_AARCH64_IFORM_LSRr,
  AMED_AARCH64_IFORM_LSRri,
  AMED_AARCH64_IFORM_MNEGr,
  AMED_AARCH64_IFORM_MOVr,
  AMED_AARCH64_IFORM_MOVri,
  AMED_AARCH64_IFORM_MULr,
  AMED_AARCH64_IFORM_MVNr,
  AMED_AARCH64_IFORM_NEGr,
  AMED_AARCH64_IFORM_NEGSr,
  AMED_AARCH64_IFORM_NGCr,
  AMED_AARCH64_IFORM_NGCSr,
  AMED_AARCH64_IFORM_REV64r,
  AMED_AARCH64_IFORM_RORri,
  AMED_AARCH64_IFORM_RORr,
  AMED_AARCH64_IFORM_SBFIZri,
  AMED_AARCH64_IFORM_SBFXri,
  AMED_AARCH64_IFORM_SMNEGLr,
  AMED_AARCH64_IFORM_SMULLr,
  AMED_AARCH64_IFORM_STADDrm,
  AMED_AARCH64_IFORM_STADDLrm,
  AMED_AARCH64_IFORM_STADDBrm,
  AMED_AARCH64_IFORM_STADDLBrm,
  AMED_AARCH64_IFORM_STADDHrm,
  AMED_AARCH64_IFORM_STADDLHrm,
  AMED_AARCH64_IFORM_STCLRrm,
  AMED_AARCH64_IFORM_STCLRLrm,
  AMED_AARCH64_IFORM_STCLRBrm,
  AMED_AARCH64_IFORM_STCLRLBrm,
  AMED_AARCH64_IFORM_STCLRHrm,
  AMED_AARCH64_IFORM_STCLRLHrm,
  AMED_AARCH64_IFORM_STEORrm,
  AMED_AARCH64_IFORM_STEORLrm,
  AMED_AARCH64_IFORM_STEORBrm,
  AMED_AARCH64_IFORM_STEORLBrm,
  AMED_AARCH64_IFORM_STEORHrm,
  AMED_AARCH64_IFORM_STEORLHrm,
  AMED_AARCH64_IFORM_STSETrm,
  AMED_AARCH64_IFORM_STSETLrm,
  AMED_AARCH64_IFORM_STSETBrm,
  AMED_AARCH64_IFORM_STSETLBrm,
  AMED_AARCH64_IFORM_STSETHrm,
  AMED_AARCH64_IFORM_STSETLHrm,
  AMED_AARCH64_IFORM_STSMAXrm,
  AMED_AARCH64_IFORM_STSMAXLrm,
  AMED_AARCH64_IFORM_STSMAXBrm,
  AMED_AARCH64_IFORM_STSMAXLBrm,
  AMED_AARCH64_IFORM_STSMAXHrm,
  AMED_AARCH64_IFORM_STSMAXLHrm,
  AMED_AARCH64_IFORM_STSMINrm,
  AMED_AARCH64_IFORM_STSMINLrm,
  AMED_AARCH64_IFORM_STSMINBrm,
  AMED_AARCH64_IFORM_STSMINLBrm,
  AMED_AARCH64_IFORM_STSMINHrm,
  AMED_AARCH64_IFORM_STSMINLHrm,
  AMED_AARCH64_IFORM_STUMAXrm,
  AMED_AARCH64_IFORM_STUMAXLrm,
  AMED_AARCH64_IFORM_STUMAXBrm,
  AMED_AARCH64_IFORM_STUMAXLBrm,
  AMED_AARCH64_IFORM_STUMAXHrm,
  AMED_AARCH64_IFORM_STUMAXLHrm,
  AMED_AARCH64_IFORM_STUMINrm,
  AMED_AARCH64_IFORM_STUMINLrm,
  AMED_AARCH64_IFORM_STUMINBrm,
  AMED_AARCH64_IFORM_STUMINLBrm,
  AMED_AARCH64_IFORM_STUMINHrm,
  AMED_AARCH64_IFORM_STUMINLHrm,
  AMED_AARCH64_IFORM_SXTBr,
  AMED_AARCH64_IFORM_SXTHr,
  AMED_AARCH64_IFORM_SXTWr,
  AMED_AARCH64_IFORM_TLBIr,
  AMED_AARCH64_IFORM_TSTri,
  AMED_AARCH64_IFORM_TSTr,
  AMED_AARCH64_IFORM_UBFIZri,
  AMED_AARCH64_IFORM_UBFXri,
  AMED_AARCH64_IFORM_UMNEGLr,
  AMED_AARCH64_IFORM_UMULLr,
  AMED_AARCH64_IFORM_UXTBr,
  AMED_AARCH64_IFORM_UXTHr,
  AMED_AARCH64_IFORM_ABSd,
  AMED_AARCH64_IFORM_ABSv,
  AMED_AARCH64_IFORM_ADDd,
  AMED_AARCH64_IFORM_ADDv,
  AMED_AARCH64_IFORM_ADDHNv,
  AMED_AARCH64_IFORM_ADDHN2v,
  AMED_AARCH64_IFORM_ADDPdv,
  AMED_AARCH64_IFORM_ADDPv,
  AMED_AARCH64_IFORM_ADDVbv,
  AMED_AARCH64_IFORM_ADDVhv,
  AMED_AARCH64_IFORM_ADDVsv,
  AMED_AARCH64_IFORM_AESDv,
  AMED_AARCH64_IFORM_AESEv,
  AMED_AARCH64_IFORM_AESIMCv,
  AMED_AARCH64_IFORM_AESMCv,
  AMED_AARCH64_IFORM_ANDv,
  AMED_AARCH64_IFORM_BCAXv,
  AMED_AARCH64_IFORM_BFCVThs,
  AMED_AARCH64_IFORM_BFCVTNv,
  AMED_AARCH64_IFORM_BFCVTN2v,
  AMED_AARCH64_IFORM_BFDOTv,
  AMED_AARCH64_IFORM_BFMLALBv,
  AMED_AARCH64_IFORM_BFMLALTv,
  AMED_AARCH64_IFORM_BFMMLAv,
  AMED_AARCH64_IFORM_BICvi,
  AMED_AARCH64_IFORM_BICv,
  AMED_AARCH64_IFORM_BIFv,
  AMED_AARCH64_IFORM_BITv,
  AMED_AARCH64_IFORM_BSLv,
  AMED_AARCH64_IFORM_CLSv,
  AMED_AARCH64_IFORM_CLZv,
  AMED_AARCH64_IFORM_CMEQd,
  AMED_AARCH64_IFORM_CMEQv,
  AMED_AARCH64_IFORM_CMEQdi,
  AMED_AARCH64_IFORM_CMEQvi,
  AMED_AARCH64_IFORM_CMGEd,
  AMED_AARCH64_IFORM_CMGEv,
  AMED_AARCH64_IFORM_CMGEdi,
  AMED_AARCH64_IFORM_CMGEvi,
  AMED_AARCH64_IFORM_CMGTd,
  AMED_AARCH64_IFORM_CMGTv,
  AMED_AARCH64_IFORM_CMGTdi,
  AMED_AARCH64_IFORM_CMGTvi,
  AMED_AARCH64_IFORM_CMHId,
  AMED_AARCH64_IFORM_CMHIv,
  AMED_AARCH64_IFORM_CMHSd,
  AMED_AARCH64_IFORM_CMHSv,
  AMED_AARCH64_IFORM_CMLEdi,
  AMED_AARCH64_IFORM_CMLEvi,
  AMED_AARCH64_IFORM_CMLTdi,
  AMED_AARCH64_IFORM_CMLTvi,
  AMED_AARCH64_IFORM_CMTSTd,
  AMED_AARCH64_IFORM_CMTSTv,
  AMED_AARCH64_IFORM_CNTv,
  AMED_AARCH64_IFORM_DUPbv,
  AMED_AARCH64_IFORM_DUPhv,
  AMED_AARCH64_IFORM_DUPsv,
  AMED_AARCH64_IFORM_DUPdv,
  AMED_AARCH64_IFORM_DUPv,
  AMED_AARCH64_IFORM_DUPvr,
  AMED_AARCH64_IFORM_EOR3v,
  AMED_AARCH64_IFORM_EORv,
  AMED_AARCH64_IFORM_EXTvi,
  AMED_AARCH64_IFORM_FABDh,
  AMED_AARCH64_IFORM_FABDs,
  AMED_AARCH64_IFORM_FABDd,
  AMED_AARCH64_IFORM_FABDv,
  AMED_AARCH64_IFORM_FABSv,
  AMED_AARCH64_IFORM_FABSh,
  AMED_AARCH64_IFORM_FABSs,
  AMED_AARCH64_IFORM_FABSd,
  AMED_AARCH64_IFORM_FACGEh,
  AMED_AARCH64_IFORM_FACGEs,
  AMED_AARCH64_IFORM_FACGEd,
  AMED_AARCH64_IFORM_FACGEv,
  AMED_AARCH64_IFORM_FACGTh,
  AMED_AARCH64_IFORM_FACGTs,
  AMED_AARCH64_IFORM_FACGTd,
  AMED_AARCH64_IFORM_FACGTv,
  AMED_AARCH64_IFORM_FADDv,
  AMED_AARCH64_IFORM_FADDh,
  AMED_AARCH64_IFORM_FADDs,
  AMED_AARCH64_IFORM_FADDd,
  AMED_AARCH64_IFORM_FADDPhv,
  AMED_AARCH64_IFORM_FADDPsv,
  AMED_AARCH64_IFORM_FADDPdv,
  AMED_AARCH64_IFORM_FADDPv,
  AMED_AARCH64_IFORM_FCADDvi,
  AMED_AARCH64_IFORM_FCCMPhi,
  AMED_AARCH64_IFORM_FCCMPsi,
  AMED_AARCH64_IFORM_FCCMPdi,
  AMED_AARCH64_IFORM_FCCMPEhi,
  AMED_AARCH64_IFORM_FCCMPEsi,
  AMED_AARCH64_IFORM_FCCMPEdi,
  AMED_AARCH64_IFORM_FCMEQh,
  AMED_AARCH64_IFORM_FCMEQs,
  AMED_AARCH64_IFORM_FCMEQd,
  AMED_AARCH64_IFORM_FCMEQv,
  AMED_AARCH64_IFORM_FCMEQhi,
  AMED_AARCH64_IFORM_FCMEQsi,
  AMED_AARCH64_IFORM_FCMEQdi,
  AMED_AARCH64_IFORM_FCMEQvi,
  AMED_AARCH64_IFORM_FCMGEh,
  AMED_AARCH64_IFORM_FCMGEs,
  AMED_AARCH64_IFORM_FCMGEd,
  AMED_AARCH64_IFORM_FCMGEv,
  AMED_AARCH64_IFORM_FCMGEhi,
  AMED_AARCH64_IFORM_FCMGEsi,
  AMED_AARCH64_IFORM_FCMGEdi,
  AMED_AARCH64_IFORM_FCMGEvi,
  AMED_AARCH64_IFORM_FCMGTh,
  AMED_AARCH64_IFORM_FCMGTs,
  AMED_AARCH64_IFORM_FCMGTd,
  AMED_AARCH64_IFORM_FCMGTv,
  AMED_AARCH64_IFORM_FCMGThi,
  AMED_AARCH64_IFORM_FCMGTsi,
  AMED_AARCH64_IFORM_FCMGTdi,
  AMED_AARCH64_IFORM_FCMGTvi,
  AMED_AARCH64_IFORM_FCMLAvi,
  AMED_AARCH64_IFORM_FCMLEhi,
  AMED_AARCH64_IFORM_FCMLEsi,
  AMED_AARCH64_IFORM_FCMLEdi,
  AMED_AARCH64_IFORM_FCMLEvi,
  AMED_AARCH64_IFORM_FCMLThi,
  AMED_AARCH64_IFORM_FCMLTsi,
  AMED_AARCH64_IFORM_FCMLTdi,
  AMED_AARCH64_IFORM_FCMLTvi,
  AMED_AARCH64_IFORM_FCMPh,
  AMED_AARCH64_IFORM_FCMPhi,
  AMED_AARCH64_IFORM_FCMPs,
  AMED_AARCH64_IFORM_FCMPsi,
  AMED_AARCH64_IFORM_FCMPd,
  AMED_AARCH64_IFORM_FCMPdi,
  AMED_AARCH64_IFORM_FCMPEh,
  AMED_AARCH64_IFORM_FCMPEhi,
  AMED_AARCH64_IFORM_FCMPEs,
  AMED_AARCH64_IFORM_FCMPEsi,
  AMED_AARCH64_IFORM_FCMPEd,
  AMED_AARCH64_IFORM_FCMPEdi,
  AMED_AARCH64_IFORM_FCSELh,
  AMED_AARCH64_IFORM_FCSELs,
  AMED_AARCH64_IFORM_FCSELd,
  AMED_AARCH64_IFORM_FCVTsh,
  AMED_AARCH64_IFORM_FCVTdh,
  AMED_AARCH64_IFORM_FCVThs,
  AMED_AARCH64_IFORM_FCVTds,
  AMED_AARCH64_IFORM_FCVThd,
  AMED_AARCH64_IFORM_FCVTsd,
  AMED_AARCH64_IFORM_FCVTASh,
  AMED_AARCH64_IFORM_FCVTASs,
  AMED_AARCH64_IFORM_FCVTASd,
  AMED_AARCH64_IFORM_FCVTASv,
  AMED_AARCH64_IFORM_FCVTASrh,
  AMED_AARCH64_IFORM_FCVTASrs,
  AMED_AARCH64_IFORM_FCVTASrd,
  AMED_AARCH64_IFORM_FCVTAUh,
  AMED_AARCH64_IFORM_FCVTAUs,
  AMED_AARCH64_IFORM_FCVTAUd,
  AMED_AARCH64_IFORM_FCVTAUv,
  AMED_AARCH64_IFORM_FCVTAUrh,
  AMED_AARCH64_IFORM_FCVTAUrs,
  AMED_AARCH64_IFORM_FCVTAUrd,
  AMED_AARCH64_IFORM_FCVTLv,
  AMED_AARCH64_IFORM_FCVTL2v,
  AMED_AARCH64_IFORM_FCVTMSh,
  AMED_AARCH64_IFORM_FCVTMSs,
  AMED_AARCH64_IFORM_FCVTMSd,
  AMED_AARCH64_IFORM_FCVTMSv,
  AMED_AARCH64_IFORM_FCVTMSrh,
  AMED_AARCH64_IFORM_FCVTMSrs,
  AMED_AARCH64_IFORM_FCVTMSrd,
  AMED_AARCH64_IFORM_FCVTMUh,
  AMED_AARCH64_IFORM_FCVTMUs,
  AMED_AARCH64_IFORM_FCVTMUd,
  AMED_AARCH64_IFORM_FCVTMUv,
  AMED_AARCH64_IFORM_FCVTMUrh,
  AMED_AARCH64_IFORM_FCVTMUrs,
  AMED_AARCH64_IFORM_FCVTMUrd,
  AMED_AARCH64_IFORM_FCVTNv,
  AMED_AARCH64_IFORM_FCVTN2v,
  AMED_AARCH64_IFORM_FCVTNSh,
  AMED_AARCH64_IFORM_FCVTNSs,
  AMED_AARCH64_IFORM_FCVTNSd,
  AMED_AARCH64_IFORM_FCVTNSv,
  AMED_AARCH64_IFORM_FCVTNSrh,
  AMED_AARCH64_IFORM_FCVTNSrs,
  AMED_AARCH64_IFORM_FCVTNSrd,
  AMED_AARCH64_IFORM_FCVTNUh,
  AMED_AARCH64_IFORM_FCVTNUs,
  AMED_AARCH64_IFORM_FCVTNUd,
  AMED_AARCH64_IFORM_FCVTNUv,
  AMED_AARCH64_IFORM_FCVTNUrh,
  AMED_AARCH64_IFORM_FCVTNUrs,
  AMED_AARCH64_IFORM_FCVTNUrd,
  AMED_AARCH64_IFORM_FCVTPSh,
  AMED_AARCH64_IFORM_FCVTPSs,
  AMED_AARCH64_IFORM_FCVTPSd,
  AMED_AARCH64_IFORM_FCVTPSv,
  AMED_AARCH64_IFORM_FCVTPSrh,
  AMED_AARCH64_IFORM_FCVTPSrs,
  AMED_AARCH64_IFORM_FCVTPSrd,
  AMED_AARCH64_IFORM_FCVTPUh,
  AMED_AARCH64_IFORM_FCVTPUs,
  AMED_AARCH64_IFORM_FCVTPUd,
  AMED_AARCH64_IFORM_FCVTPUv,
  AMED_AARCH64_IFORM_FCVTPUrh,
  AMED_AARCH64_IFORM_FCVTPUrs,
  AMED_AARCH64_IFORM_FCVTPUrd,
  AMED_AARCH64_IFORM_FCVTXNsd,
  AMED_AARCH64_IFORM_FCVTXNv,
  AMED_AARCH64_IFORM_FCVTXN2v,
  AMED_AARCH64_IFORM_FCVTZShi,
  AMED_AARCH64_IFORM_FCVTZSsi,
  AMED_AARCH64_IFORM_FCVTZSdi,
  AMED_AARCH64_IFORM_FCVTZSvi,
  AMED_AARCH64_IFORM_FCVTZSh,
  AMED_AARCH64_IFORM_FCVTZSs,
  AMED_AARCH64_IFORM_FCVTZSd,
  AMED_AARCH64_IFORM_FCVTZSv,
  AMED_AARCH64_IFORM_FCVTZSrhi,
  AMED_AARCH64_IFORM_FCVTZSrsi,
  AMED_AARCH64_IFORM_FCVTZSrdi,
  AMED_AARCH64_IFORM_FCVTZSrh,
  AMED_AARCH64_IFORM_FCVTZSrs,
  AMED_AARCH64_IFORM_FCVTZSrd,
  AMED_AARCH64_IFORM_FCVTZUhi,
  AMED_AARCH64_IFORM_FCVTZUsi,
  AMED_AARCH64_IFORM_FCVTZUdi,
  AMED_AARCH64_IFORM_FCVTZUvi,
  AMED_AARCH64_IFORM_FCVTZUh,
  AMED_AARCH64_IFORM_FCVTZUs,
  AMED_AARCH64_IFORM_FCVTZUd,
  AMED_AARCH64_IFORM_FCVTZUv,
  AMED_AARCH64_IFORM_FCVTZUrhi,
  AMED_AARCH64_IFORM_FCVTZUrsi,
  AMED_AARCH64_IFORM_FCVTZUrdi,
  AMED_AARCH64_IFORM_FCVTZUrh,
  AMED_AARCH64_IFORM_FCVTZUrs,
  AMED_AARCH64_IFORM_FCVTZUrd,
  AMED_AARCH64_IFORM_FDIVv,
  AMED_AARCH64_IFORM_FDIVh,
  AMED_AARCH64_IFORM_FDIVs,
  AMED_AARCH64_IFORM_FDIVd,
  AMED_AARCH64_IFORM_FJCVTZSrd,
  AMED_AARCH64_IFORM_FMADDh,
  AMED_AARCH64_IFORM_FMADDs,
  AMED_AARCH64_IFORM_FMADDd,
  AMED_AARCH64_IFORM_FMAXv,
  AMED_AARCH64_IFORM_FMAXh,
  AMED_AARCH64_IFORM_FMAXs,
  AMED_AARCH64_IFORM_FMAXd,
  AMED_AARCH64_IFORM_FMAXNMv,
  AMED_AARCH64_IFORM_FMAXNMh,
  AMED_AARCH64_IFORM_FMAXNMs,
  AMED_AARCH64_IFORM_FMAXNMd,
  AMED_AARCH64_IFORM_FMAXNMPhv,
  AMED_AARCH64_IFORM_FMAXNMPsv,
  AMED_AARCH64_IFORM_FMAXNMPdv,
  AMED_AARCH64_IFORM_FMAXNMPv,
  AMED_AARCH64_IFORM_FMAXNMVhv,
  AMED_AARCH64_IFORM_FMAXNMVsv,
  AMED_AARCH64_IFORM_FMAXPhv,
  AMED_AARCH64_IFORM_FMAXPsv,
  AMED_AARCH64_IFORM_FMAXPdv,
  AMED_AARCH64_IFORM_FMAXPv,
  AMED_AARCH64_IFORM_FMAXVhv,
  AMED_AARCH64_IFORM_FMAXVsv,
  AMED_AARCH64_IFORM_FMINv,
  AMED_AARCH64_IFORM_FMINh,
  AMED_AARCH64_IFORM_FMINs,
  AMED_AARCH64_IFORM_FMINd,
  AMED_AARCH64_IFORM_FMINNMv,
  AMED_AARCH64_IFORM_FMINNMh,
  AMED_AARCH64_IFORM_FMINNMs,
  AMED_AARCH64_IFORM_FMINNMd,
  AMED_AARCH64_IFORM_FMINNMPhv,
  AMED_AARCH64_IFORM_FMINNMPsv,
  AMED_AARCH64_IFORM_FMINNMPdv,
  AMED_AARCH64_IFORM_FMINNMPv,
  AMED_AARCH64_IFORM_FMINNMVhv,
  AMED_AARCH64_IFORM_FMINNMVsv,
  AMED_AARCH64_IFORM_FMINPhv,
  AMED_AARCH64_IFORM_FMINPsv,
  AMED_AARCH64_IFORM_FMINPdv,
  AMED_AARCH64_IFORM_FMINPv,
  AMED_AARCH64_IFORM_FMINVhv,
  AMED_AARCH64_IFORM_FMINVsv,
  AMED_AARCH64_IFORM_FMLAhv,
  AMED_AARCH64_IFORM_FMLAsv,
  AMED_AARCH64_IFORM_FMLAdv,
  AMED_AARCH64_IFORM_FMLAv,
  AMED_AARCH64_IFORM_FMLALv,
  AMED_AARCH64_IFORM_FMLAL2v,
  AMED_AARCH64_IFORM_FMLShv,
  AMED_AARCH64_IFORM_FMLSsv,
  AMED_AARCH64_IFORM_FMLSdv,
  AMED_AARCH64_IFORM_FMLSv,
  AMED_AARCH64_IFORM_FMLSLv,
  AMED_AARCH64_IFORM_FMLSL2v,
  AMED_AARCH64_IFORM_FMOVvi,
  AMED_AARCH64_IFORM_FMOVh,
  AMED_AARCH64_IFORM_FMOVs,
  AMED_AARCH64_IFORM_FMOVd,
  AMED_AARCH64_IFORM_FMOVrh,
  AMED_AARCH64_IFORM_FMOVhr,
  AMED_AARCH64_IFORM_FMOVsr,
  AMED_AARCH64_IFORM_FMOVrs,
  AMED_AARCH64_IFORM_FMOVdr,
  AMED_AARCH64_IFORM_FMOVvr,
  AMED_AARCH64_IFORM_FMOVrd,
  AMED_AARCH64_IFORM_FMOVrv,
  AMED_AARCH64_IFORM_FMOVhi,
  AMED_AARCH64_IFORM_FMOVsi,
  AMED_AARCH64_IFORM_FMOVdi,
  AMED_AARCH64_IFORM_FMSUBh,
  AMED_AARCH64_IFORM_FMSUBs,
  AMED_AARCH64_IFORM_FMSUBd,
  AMED_AARCH64_IFORM_FMULhv,
  AMED_AARCH64_IFORM_FMULsv,
  AMED_AARCH64_IFORM_FMULdv,
  AMED_AARCH64_IFORM_FMULv,
  AMED_AARCH64_IFORM_FMULh,
  AMED_AARCH64_IFORM_FMULs,
  AMED_AARCH64_IFORM_FMULd,
  AMED_AARCH64_IFORM_FMULXhv,
  AMED_AARCH64_IFORM_FMULXsv,
  AMED_AARCH64_IFORM_FMULXdv,
  AMED_AARCH64_IFORM_FMULXv,
  AMED_AARCH64_IFORM_FMULXh,
  AMED_AARCH64_IFORM_FMULXs,
  AMED_AARCH64_IFORM_FMULXd,
  AMED_AARCH64_IFORM_FNEGv,
  AMED_AARCH64_IFORM_FNEGh,
  AMED_AARCH64_IFORM_FNEGs,
  AMED_AARCH64_IFORM_FNEGd,
  AMED_AARCH64_IFORM_FNMADDh,
  AMED_AARCH64_IFORM_FNMADDs,
  AMED_AARCH64_IFORM_FNMADDd,
  AMED_AARCH64_IFORM_FNMSUBh,
  AMED_AARCH64_IFORM_FNMSUBs,
  AMED_AARCH64_IFORM_FNMSUBd,
  AMED_AARCH64_IFORM_FNMULh,
  AMED_AARCH64_IFORM_FNMULs,
  AMED_AARCH64_IFORM_FNMULd,
  AMED_AARCH64_IFORM_FRECPEh,
  AMED_AARCH64_IFORM_FRECPEs,
  AMED_AARCH64_IFORM_FRECPEd,
  AMED_AARCH64_IFORM_FRECPEv,
  AMED_AARCH64_IFORM_FRECPSh,
  AMED_AARCH64_IFORM_FRECPSs,
  AMED_AARCH64_IFORM_FRECPSd,
  AMED_AARCH64_IFORM_FRECPSv,
  AMED_AARCH64_IFORM_FRECPXh,
  AMED_AARCH64_IFORM_FRECPXs,
  AMED_AARCH64_IFORM_FRECPXd,
  AMED_AARCH64_IFORM_FRINT32Xv,
  AMED_AARCH64_IFORM_FRINT32Xs,
  AMED_AARCH64_IFORM_FRINT32Xd,
  AMED_AARCH64_IFORM_FRINT32Zv,
  AMED_AARCH64_IFORM_FRINT32Zs,
  AMED_AARCH64_IFORM_FRINT32Zd,
  AMED_AARCH64_IFORM_FRINT64Xv,
  AMED_AARCH64_IFORM_FRINT64Xs,
  AMED_AARCH64_IFORM_FRINT64Xd,
  AMED_AARCH64_IFORM_FRINT64Zv,
  AMED_AARCH64_IFORM_FRINT64Zs,
  AMED_AARCH64_IFORM_FRINT64Zd,
  AMED_AARCH64_IFORM_FRINTAv,
  AMED_AARCH64_IFORM_FRINTAh,
  AMED_AARCH64_IFORM_FRINTAs,
  AMED_AARCH64_IFORM_FRINTAd,
  AMED_AARCH64_IFORM_FRINTIv,
  AMED_AARCH64_IFORM_FRINTIh,
  AMED_AARCH64_IFORM_FRINTIs,
  AMED_AARCH64_IFORM_FRINTId,
  AMED_AARCH64_IFORM_FRINTMv,
  AMED_AARCH64_IFORM_FRINTMh,
  AMED_AARCH64_IFORM_FRINTMs,
  AMED_AARCH64_IFORM_FRINTMd,
  AMED_AARCH64_IFORM_FRINTNv,
  AMED_AARCH64_IFORM_FRINTNh,
  AMED_AARCH64_IFORM_FRINTNs,
  AMED_AARCH64_IFORM_FRINTNd,
  AMED_AARCH64_IFORM_FRINTPv,
  AMED_AARCH64_IFORM_FRINTPh,
  AMED_AARCH64_IFORM_FRINTPs,
  AMED_AARCH64_IFORM_FRINTPd,
  AMED_AARCH64_IFORM_FRINTXv,
  AMED_AARCH64_IFORM_FRINTXh,
  AMED_AARCH64_IFORM_FRINTXs,
  AMED_AARCH64_IFORM_FRINTXd,
  AMED_AARCH64_IFORM_FRINTZv,
  AMED_AARCH64_IFORM_FRINTZh,
  AMED_AARCH64_IFORM_FRINTZs,
  AMED_AARCH64_IFORM_FRINTZd,
  AMED_AARCH64_IFORM_FRSQRTEh,
  AMED_AARCH64_IFORM_FRSQRTEs,
  AMED_AARCH64_IFORM_FRSQRTEd,
  AMED_AARCH64_IFORM_FRSQRTEv,
  AMED_AARCH64_IFORM_FRSQRTSh,
  AMED_AARCH64_IFORM_FRSQRTSs,
  AMED_AARCH64_IFORM_FRSQRTSd,
  AMED_AARCH64_IFORM_FRSQRTSv,
  AMED_AARCH64_IFORM_FSQRTv,
  AMED_AARCH64_IFORM_FSQRTh,
  AMED_AARCH64_IFORM_FSQRTs,
  AMED_AARCH64_IFORM_FSQRTd,
  AMED_AARCH64_IFORM_FSUBv,
  AMED_AARCH64_IFORM_FSUBh,
  AMED_AARCH64_IFORM_FSUBs,
  AMED_AARCH64_IFORM_FSUBd,
  AMED_AARCH64_IFORM_INSv,
  AMED_AARCH64_IFORM_INSvr,
  AMED_AARCH64_IFORM_LD1lm,
  AMED_AARCH64_IFORM_LD1Rlm,
  AMED_AARCH64_IFORM_LD2lm,
  AMED_AARCH64_IFORM_LD2Rlm,
  AMED_AARCH64_IFORM_LD3lm,
  AMED_AARCH64_IFORM_LD3Rlm,
  AMED_AARCH64_IFORM_LD4lm,
  AMED_AARCH64_IFORM_LD4Rlm,
  AMED_AARCH64_IFORM_LDNPsm,
  AMED_AARCH64_IFORM_LDNPdm,
  AMED_AARCH64_IFORM_LDNPqm,
  AMED_AARCH64_IFORM_LDPsm,
  AMED_AARCH64_IFORM_LDPdm,
  AMED_AARCH64_IFORM_LDPqm,
  AMED_AARCH64_IFORM_LDRbm,
  AMED_AARCH64_IFORM_LDRhm,
  AMED_AARCH64_IFORM_LDRsm,
  AMED_AARCH64_IFORM_LDRdm,
  AMED_AARCH64_IFORM_LDRqm,
  AMED_AARCH64_IFORM_LDRs,
  AMED_AARCH64_IFORM_LDRd,
  AMED_AARCH64_IFORM_LDRq,
  AMED_AARCH64_IFORM_LDURbm,
  AMED_AARCH64_IFORM_LDURhm,
  AMED_AARCH64_IFORM_LDURsm,
  AMED_AARCH64_IFORM_LDURdm,
  AMED_AARCH64_IFORM_LDURqm,
  AMED_AARCH64_IFORM_MLAv,
  AMED_AARCH64_IFORM_MLSv,
  AMED_AARCH64_IFORM_MOVIvi,
  AMED_AARCH64_IFORM_MOVIdi,
  AMED_AARCH64_IFORM_MULv,
  AMED_AARCH64_IFORM_MVNIvi,
  AMED_AARCH64_IFORM_NEGd,
  AMED_AARCH64_IFORM_NEGv,
  AMED_AARCH64_IFORM_NOTv,
  AMED_AARCH64_IFORM_ORNv,
  AMED_AARCH64_IFORM_ORRvi,
  AMED_AARCH64_IFORM_ORRv,
  AMED_AARCH64_IFORM_PMULv,
  AMED_AARCH64_IFORM_PMULLv,
  AMED_AARCH64_IFORM_PMULL2v,
  AMED_AARCH64_IFORM_RADDHNv,
  AMED_AARCH64_IFORM_RADDHN2v,
  AMED_AARCH64_IFORM_RAX1v,
  AMED_AARCH64_IFORM_RBITv,
  AMED_AARCH64_IFORM_REV16v,
  AMED_AARCH64_IFORM_REV32v,
  AMED_AARCH64_IFORM_REV64v,
  AMED_AARCH64_IFORM_RSHRNvi,
  AMED_AARCH64_IFORM_RSHRN2vi,
  AMED_AARCH64_IFORM_RSUBHNv,
  AMED_AARCH64_IFORM_RSUBHN2v,
  AMED_AARCH64_IFORM_SABAv,
  AMED_AARCH64_IFORM_SABALv,
  AMED_AARCH64_IFORM_SABAL2v,
  AMED_AARCH64_IFORM_SABDv,
  AMED_AARCH64_IFORM_SABDLv,
  AMED_AARCH64_IFORM_SABDL2v,
  AMED_AARCH64_IFORM_SADALPv,
  AMED_AARCH64_IFORM_SADDLv,
  AMED_AARCH64_IFORM_SADDL2v,
  AMED_AARCH64_IFORM_SADDLPv,
  AMED_AARCH64_IFORM_SADDLVhv,
  AMED_AARCH64_IFORM_SADDLVsv,
  AMED_AARCH64_IFORM_SADDLVdv,
  AMED_AARCH64_IFORM_SADDWv,
  AMED_AARCH64_IFORM_SADDW2v,
  AMED_AARCH64_IFORM_SCVTFhi,
  AMED_AARCH64_IFORM_SCVTFsi,
  AMED_AARCH64_IFORM_SCVTFdi,
  AMED_AARCH64_IFORM_SCVTFvi,
  AMED_AARCH64_IFORM_SCVTFh,
  AMED_AARCH64_IFORM_SCVTFs,
  AMED_AARCH64_IFORM_SCVTFd,
  AMED_AARCH64_IFORM_SCVTFv,
  AMED_AARCH64_IFORM_SCVTFhri,
  AMED_AARCH64_IFORM_SCVTFsri,
  AMED_AARCH64_IFORM_SCVTFdri,
  AMED_AARCH64_IFORM_SCVTFhr,
  AMED_AARCH64_IFORM_SCVTFsr,
  AMED_AARCH64_IFORM_SCVTFdr,
  AMED_AARCH64_IFORM_SDOTv,
  AMED_AARCH64_IFORM_SHA1Cqsv,
  AMED_AARCH64_IFORM_SHA1Hs,
  AMED_AARCH64_IFORM_SHA1Mqsv,
  AMED_AARCH64_IFORM_SHA1Pqsv,
  AMED_AARCH64_IFORM_SHA1SU0v,
  AMED_AARCH64_IFORM_SHA1SU1v,
  AMED_AARCH64_IFORM_SHA256H2qv,
  AMED_AARCH64_IFORM_SHA256Hqv,
  AMED_AARCH64_IFORM_SHA256SU0v,
  AMED_AARCH64_IFORM_SHA256SU1v,
  AMED_AARCH64_IFORM_SHA512H2qv,
  AMED_AARCH64_IFORM_SHA512Hqv,
  AMED_AARCH64_IFORM_SHA512SU0v,
  AMED_AARCH64_IFORM_SHA512SU1v,
  AMED_AARCH64_IFORM_SHADDv,
  AMED_AARCH64_IFORM_SHLdi,
  AMED_AARCH64_IFORM_SHLvi,
  AMED_AARCH64_IFORM_SHLLvi,
  AMED_AARCH64_IFORM_SHLL2vi,
  AMED_AARCH64_IFORM_SHRNvi,
  AMED_AARCH64_IFORM_SHRN2vi,
  AMED_AARCH64_IFORM_SHSUBv,
  AMED_AARCH64_IFORM_SLIdi,
  AMED_AARCH64_IFORM_SLIvi,
  AMED_AARCH64_IFORM_SM3PARTW1v,
  AMED_AARCH64_IFORM_SM3PARTW2v,
  AMED_AARCH64_IFORM_SM3SS1v,
  AMED_AARCH64_IFORM_SM3TT1Av,
  AMED_AARCH64_IFORM_SM3TT1Bv,
  AMED_AARCH64_IFORM_SM3TT2Av,
  AMED_AARCH64_IFORM_SM3TT2Bv,
  AMED_AARCH64_IFORM_SM4Ev,
  AMED_AARCH64_IFORM_SM4EKEYv,
  AMED_AARCH64_IFORM_SMAXv,
  AMED_AARCH64_IFORM_SMAXPv,
  AMED_AARCH64_IFORM_SMAXVbv,
  AMED_AARCH64_IFORM_SMAXVhv,
  AMED_AARCH64_IFORM_SMAXVsv,
  AMED_AARCH64_IFORM_SMINv,
  AMED_AARCH64_IFORM_SMINPv,
  AMED_AARCH64_IFORM_SMINVbv,
  AMED_AARCH64_IFORM_SMINVhv,
  AMED_AARCH64_IFORM_SMINVsv,
  AMED_AARCH64_IFORM_SMLALv,
  AMED_AARCH64_IFORM_SMLAL2v,
  AMED_AARCH64_IFORM_SMLSLv,
  AMED_AARCH64_IFORM_SMLSL2v,
  AMED_AARCH64_IFORM_SMMLAv,
  AMED_AARCH64_IFORM_SMOVrv,
  AMED_AARCH64_IFORM_SMULLv,
  AMED_AARCH64_IFORM_SMULL2v,
  AMED_AARCH64_IFORM_SQABSb,
  AMED_AARCH64_IFORM_SQABSh,
  AMED_AARCH64_IFORM_SQABSs,
  AMED_AARCH64_IFORM_SQABSd,
  AMED_AARCH64_IFORM_SQABSv,
  AMED_AARCH64_IFORM_SQADDb,
  AMED_AARCH64_IFORM_SQADDh,
  AMED_AARCH64_IFORM_SQADDs,
  AMED_AARCH64_IFORM_SQADDd,
  AMED_AARCH64_IFORM_SQADDv,
  AMED_AARCH64_IFORM_SQDMLALshv,
  AMED_AARCH64_IFORM_SQDMLALdsv,
  AMED_AARCH64_IFORM_SQDMLALv,
  AMED_AARCH64_IFORM_SQDMLAL2v,
  AMED_AARCH64_IFORM_SQDMLALsh,
  AMED_AARCH64_IFORM_SQDMLALds,
  AMED_AARCH64_IFORM_SQDMLSLshv,
  AMED_AARCH64_IFORM_SQDMLSLdsv,
  AMED_AARCH64_IFORM_SQDMLSLv,
  AMED_AARCH64_IFORM_SQDMLSL2v,
  AMED_AARCH64_IFORM_SQDMLSLsh,
  AMED_AARCH64_IFORM_SQDMLSLds,
  AMED_AARCH64_IFORM_SQDMULHhv,
  AMED_AARCH64_IFORM_SQDMULHsv,
  AMED_AARCH64_IFORM_SQDMULHv,
  AMED_AARCH64_IFORM_SQDMULHh,
  AMED_AARCH64_IFORM_SQDMULHs,
  AMED_AARCH64_IFORM_SQDMULLshv,
  AMED_AARCH64_IFORM_SQDMULLdsv,
  AMED_AARCH64_IFORM_SQDMULLv,
  AMED_AARCH64_IFORM_SQDMULL2v,
  AMED_AARCH64_IFORM_SQDMULLsh,
  AMED_AARCH64_IFORM_SQDMULLds,
  AMED_AARCH64_IFORM_SQNEGb,
  AMED_AARCH64_IFORM_SQNEGh,
  AMED_AARCH64_IFORM_SQNEGs,
  AMED_AARCH64_IFORM_SQNEGd,
  AMED_AARCH64_IFORM_SQNEGv,
  AMED_AARCH64_IFORM_SQRDMLAHhv,
  AMED_AARCH64_IFORM_SQRDMLAHsv,
  AMED_AARCH64_IFORM_SQRDMLAHv,
  AMED_AARCH64_IFORM_SQRDMLAHh,
  AMED_AARCH64_IFORM_SQRDMLAHs,
  AMED_AARCH64_IFORM_SQRDMLSHhv,
  AMED_AARCH64_IFORM_SQRDMLSHsv,
  AMED_AARCH64_IFORM_SQRDMLSHv,
  AMED_AARCH64_IFORM_SQRDMLSHh,
  AMED_AARCH64_IFORM_SQRDMLSHs,
  AMED_AARCH64_IFORM_SQRDMULHhv,
  AMED_AARCH64_IFORM_SQRDMULHsv,
  AMED_AARCH64_IFORM_SQRDMULHv,
  AMED_AARCH64_IFORM_SQRDMULHh,
  AMED_AARCH64_IFORM_SQRDMULHs,
  AMED_AARCH64_IFORM_SQRSHLb,
  AMED_AARCH64_IFORM_SQRSHLh,
  AMED_AARCH64_IFORM_SQRSHLs,
  AMED_AARCH64_IFORM_SQRSHLd,
  AMED_AARCH64_IFORM_SQRSHLv,
  AMED_AARCH64_IFORM_SQRSHRNbhi,
  AMED_AARCH64_IFORM_SQRSHRNhsi,
  AMED_AARCH64_IFORM_SQRSHRNsdi,
  AMED_AARCH64_IFORM_SQRSHRNvi,
  AMED_AARCH64_IFORM_SQRSHRN2vi,
  AMED_AARCH64_IFORM_SQRSHRUNbhi,
  AMED_AARCH64_IFORM_SQRSHRUNhsi,
  AMED_AARCH64_IFORM_SQRSHRUNsdi,
  AMED_AARCH64_IFORM_SQRSHRUNvi,
  AMED_AARCH64_IFORM_SQRSHRUN2vi,
  AMED_AARCH64_IFORM_SQSHLbi,
  AMED_AARCH64_IFORM_SQSHLhi,
  AMED_AARCH64_IFORM_SQSHLsi,
  AMED_AARCH64_IFORM_SQSHLdi,
  AMED_AARCH64_IFORM_SQSHLvi,
  AMED_AARCH64_IFORM_SQSHLb,
  AMED_AARCH64_IFORM_SQSHLh,
  AMED_AARCH64_IFORM_SQSHLs,
  AMED_AARCH64_IFORM_SQSHLd,
  AMED_AARCH64_IFORM_SQSHLv,
  AMED_AARCH64_IFORM_SQSHLUbi,
  AMED_AARCH64_IFORM_SQSHLUhi,
  AMED_AARCH64_IFORM_SQSHLUsi,
  AMED_AARCH64_IFORM_SQSHLUdi,
  AMED_AARCH64_IFORM_SQSHLUvi,
  AMED_AARCH64_IFORM_SQSHRNbhi,
  AMED_AARCH64_IFORM_SQSHRNhsi,
  AMED_AARCH64_IFORM_SQSHRNsdi,
  AMED_AARCH64_IFORM_SQSHRNvi,
  AMED_AARCH64_IFORM_SQSHRN2vi,
  AMED_AARCH64_IFORM_SQSHRUNbhi,
  AMED_AARCH64_IFORM_SQSHRUNhsi,
  AMED_AARCH64_IFORM_SQSHRUNsdi,
  AMED_AARCH64_IFORM_SQSHRUNvi,
  AMED_AARCH64_IFORM_SQSHRUN2vi,
  AMED_AARCH64_IFORM_SQSUBb,
  AMED_AARCH64_IFORM_SQSUBh,
  AMED_AARCH64_IFORM_SQSUBs,
  AMED_AARCH64_IFORM_SQSUBd,
  AMED_AARCH64_IFORM_SQSUBv,
  AMED_AARCH64_IFORM_SQXTNbh,
  AMED_AARCH64_IFORM_SQXTNhs,
  AMED_AARCH64_IFORM_SQXTNsd,
  AMED_AARCH64_IFORM_SQXTNv,
  AMED_AARCH64_IFORM_SQXTN2v,
  AMED_AARCH64_IFORM_SQXTUNbh,
  AMED_AARCH64_IFORM_SQXTUNhs,
  AMED_AARCH64_IFORM_SQXTUNsd,
  AMED_AARCH64_IFORM_SQXTUNv,
  AMED_AARCH64_IFORM_SQXTUN2v,
  AMED_AARCH64_IFORM_SRHADDv,
  AMED_AARCH64_IFORM_SRIdi,
  AMED_AARCH64_IFORM_SRIvi,
  AMED_AARCH64_IFORM_SRSHLd,
  AMED_AARCH64_IFORM_SRSHLv,
  AMED_AARCH64_IFORM_SRSHRdi,
  AMED_AARCH64_IFORM_SRSHRvi,
  AMED_AARCH64_IFORM_SRSRAdi,
  AMED_AARCH64_IFORM_SRSRAvi,
  AMED_AARCH64_IFORM_SSHLd,
  AMED_AARCH64_IFORM_SSHLv,
  AMED_AARCH64_IFORM_SSHLLvi,
  AMED_AARCH64_IFORM_SSHLL2vi,
  AMED_AARCH64_IFORM_SSHRdi,
  AMED_AARCH64_IFORM_SSHRvi,
  AMED_AARCH64_IFORM_SSRAdi,
  AMED_AARCH64_IFORM_SSRAvi,
  AMED_AARCH64_IFORM_SSUBLv,
  AMED_AARCH64_IFORM_SSUBL2v,
  AMED_AARCH64_IFORM_SSUBWv,
  AMED_AARCH64_IFORM_SSUBW2v,
  AMED_AARCH64_IFORM_ST1lm,
  AMED_AARCH64_IFORM_ST2lm,
  AMED_AARCH64_IFORM_ST3lm,
  AMED_AARCH64_IFORM_ST4lm,
  AMED_AARCH64_IFORM_STNPsm,
  AMED_AARCH64_IFORM_STNPdm,
  AMED_AARCH64_IFORM_STNPqm,
  AMED_AARCH64_IFORM_STPsm,
  AMED_AARCH64_IFORM_STPdm,
  AMED_AARCH64_IFORM_STPqm,
  AMED_AARCH64_IFORM_STRbm,
  AMED_AARCH64_IFORM_STRhm,
  AMED_AARCH64_IFORM_STRsm,
  AMED_AARCH64_IFORM_STRdm,
  AMED_AARCH64_IFORM_STRqm,
  AMED_AARCH64_IFORM_STURbm,
  AMED_AARCH64_IFORM_STURhm,
  AMED_AARCH64_IFORM_STURsm,
  AMED_AARCH64_IFORM_STURdm,
  AMED_AARCH64_IFORM_STURqm,
  AMED_AARCH64_IFORM_SUBd,
  AMED_AARCH64_IFORM_SUBv,
  AMED_AARCH64_IFORM_SUBHNv,
  AMED_AARCH64_IFORM_SUBHN2v,
  AMED_AARCH64_IFORM_SUDOTv,
  AMED_AARCH64_IFORM_SUQADDb,
  AMED_AARCH64_IFORM_SUQADDh,
  AMED_AARCH64_IFORM_SUQADDs,
  AMED_AARCH64_IFORM_SUQADDd,
  AMED_AARCH64_IFORM_SUQADDv,
  AMED_AARCH64_IFORM_TBLvl,
  AMED_AARCH64_IFORM_TBXvl,
  AMED_AARCH64_IFORM_TRN1v,
  AMED_AARCH64_IFORM_TRN2v,
  AMED_AARCH64_IFORM_UABAv,
  AMED_AARCH64_IFORM_UABALv,
  AMED_AARCH64_IFORM_UABAL2v,
  AMED_AARCH64_IFORM_UABDv,
  AMED_AARCH64_IFORM_UABDLv,
  AMED_AARCH64_IFORM_UABDL2v,
  AMED_AARCH64_IFORM_UADALPv,
  AMED_AARCH64_IFORM_UADDLv,
  AMED_AARCH64_IFORM_UADDL2v,
  AMED_AARCH64_IFORM_UADDLPv,
  AMED_AARCH64_IFORM_UADDLVhv,
  AMED_AARCH64_IFORM_UADDLVsv,
  AMED_AARCH64_IFORM_UADDLVdv,
  AMED_AARCH64_IFORM_UADDWv,
  AMED_AARCH64_IFORM_UADDW2v,
  AMED_AARCH64_IFORM_UCVTFhi,
  AMED_AARCH64_IFORM_UCVTFsi,
  AMED_AARCH64_IFORM_UCVTFdi,
  AMED_AARCH64_IFORM_UCVTFvi,
  AMED_AARCH64_IFORM_UCVTFh,
  AMED_AARCH64_IFORM_UCVTFs,
  AMED_AARCH64_IFORM_UCVTFd,
  AMED_AARCH64_IFORM_UCVTFv,
  AMED_AARCH64_IFORM_UCVTFhri,
  AMED_AARCH64_IFORM_UCVTFsri,
  AMED_AARCH64_IFORM_UCVTFdri,
  AMED_AARCH64_IFORM_UCVTFhr,
  AMED_AARCH64_IFORM_UCVTFsr,
  AMED_AARCH64_IFORM_UCVTFdr,
  AMED_AARCH64_IFORM_UDOTv,
  AMED_AARCH64_IFORM_UHADDv,
  AMED_AARCH64_IFORM_UHSUBv,
  AMED_AARCH64_IFORM_UMAXv,
  AMED_AARCH64_IFORM_UMAXPv,
  AMED_AARCH64_IFORM_UMAXVbv,
  AMED_AARCH64_IFORM_UMAXVhv,
  AMED_AARCH64_IFORM_UMAXVsv,
  AMED_AARCH64_IFORM_UMINv,
  AMED_AARCH64_IFORM_UMINPv,
  AMED_AARCH64_IFORM_UMINVbv,
  AMED_AARCH64_IFORM_UMINVhv,
  AMED_AARCH64_IFORM_UMINVsv,
  AMED_AARCH64_IFORM_UMLALv,
  AMED_AARCH64_IFORM_UMLAL2v,
  AMED_AARCH64_IFORM_UMLSLv,
  AMED_AARCH64_IFORM_UMLSL2v,
  AMED_AARCH64_IFORM_UMMLAv,
  AMED_AARCH64_IFORM_UMOVrv,
  AMED_AARCH64_IFORM_UMULLv,
  AMED_AARCH64_IFORM_UMULL2v,
  AMED_AARCH64_IFORM_UQADDb,
  AMED_AARCH64_IFORM_UQADDh,
  AMED_AARCH64_IFORM_UQADDs,
  AMED_AARCH64_IFORM_UQADDd,
  AMED_AARCH64_IFORM_UQADDv,
  AMED_AARCH64_IFORM_UQRSHLb,
  AMED_AARCH64_IFORM_UQRSHLh,
  AMED_AARCH64_IFORM_UQRSHLs,
  AMED_AARCH64_IFORM_UQRSHLd,
  AMED_AARCH64_IFORM_UQRSHLv,
  AMED_AARCH64_IFORM_UQRSHRNbhi,
  AMED_AARCH64_IFORM_UQRSHRNhsi,
  AMED_AARCH64_IFORM_UQRSHRNsdi,
  AMED_AARCH64_IFORM_UQRSHRNvi,
  AMED_AARCH64_IFORM_UQRSHRN2vi,
  AMED_AARCH64_IFORM_UQSHLbi,
  AMED_AARCH64_IFORM_UQSHLhi,
  AMED_AARCH64_IFORM_UQSHLsi,
  AMED_AARCH64_IFORM_UQSHLdi,
  AMED_AARCH64_IFORM_UQSHLvi,
  AMED_AARCH64_IFORM_UQSHLb,
  AMED_AARCH64_IFORM_UQSHLh,
  AMED_AARCH64_IFORM_UQSHLs,
  AMED_AARCH64_IFORM_UQSHLd,
  AMED_AARCH64_IFORM_UQSHLv,
  AMED_AARCH64_IFORM_UQSHRNbhi,
  AMED_AARCH64_IFORM_UQSHRNhsi,
  AMED_AARCH64_IFORM_UQSHRNsdi,
  AMED_AARCH64_IFORM_UQSHRNvi,
  AMED_AARCH64_IFORM_UQSHRN2vi,
  AMED_AARCH64_IFORM_UQSUBb,
  AMED_AARCH64_IFORM_UQSUBh,
  AMED_AARCH64_IFORM_UQSUBs,
  AMED_AARCH64_IFORM_UQSUBd,
  AMED_AARCH64_IFORM_UQSUBv,
  AMED_AARCH64_IFORM_UQXTNbh,
  AMED_AARCH64_IFORM_UQXTNhs,
  AMED_AARCH64_IFORM_UQXTNsd,
  AMED_AARCH64_IFORM_UQXTNv,
  AMED_AARCH64_IFORM_UQXTN2v,
  AMED_AARCH64_IFORM_URECPEv,
  AMED_AARCH64_IFORM_URHADDv,
  AMED_AARCH64_IFORM_URSHLd,
  AMED_AARCH64_IFORM_URSHLv,
  AMED_AARCH64_IFORM_URSHRdi,
  AMED_AARCH64_IFORM_URSHRvi,
  AMED_AARCH64_IFORM_URSQRTEv,
  AMED_AARCH64_IFORM_URSRAdi,
  AMED_AARCH64_IFORM_URSRAvi,
  AMED_AARCH64_IFORM_USDOTv,
  AMED_AARCH64_IFORM_USHLd,
  AMED_AARCH64_IFORM_USHLv,
  AMED_AARCH64_IFORM_USHLLvi,
  AMED_AARCH64_IFORM_USHLL2vi,
  AMED_AARCH64_IFORM_USHRdi,
  AMED_AARCH64_IFORM_USHRvi,
  AMED_AARCH64_IFORM_USMMLAv,
  AMED_AARCH64_IFORM_USQADDb,
  AMED_AARCH64_IFORM_USQADDh,
  AMED_AARCH64_IFORM_USQADDs,
  AMED_AARCH64_IFORM_USQADDd,
  AMED_AARCH64_IFORM_USQADDv,
  AMED_AARCH64_IFORM_USRAdi,
  AMED_AARCH64_IFORM_USRAvi,
  AMED_AARCH64_IFORM_USUBLv,
  AMED_AARCH64_IFORM_USUBL2v,
  AMED_AARCH64_IFORM_USUBWv,
  AMED_AARCH64_IFORM_USUBW2v,
  AMED_AARCH64_IFORM_UZP1v,
  AMED_AARCH64_IFORM_UZP2v,
  AMED_AARCH64_IFORM_XARvi,
  AMED_AARCH64_IFORM_XTNv,
  AMED_AARCH64_IFORM_XTN2v,
  AMED_AARCH64_IFORM_ZIP1v,
  AMED_AARCH64_IFORM_ZIP2v,
  AMED_AARCH64_IFORM_MOVbv,
  AMED_AARCH64_IFORM_MOVhv,
  AMED_AARCH64_IFORM_MOVsv,
  AMED_AARCH64_IFORM_MOVdv,
  AMED_AARCH64_IFORM_MOVv,
  AMED_AARCH64_IFORM_MOVvr,
  AMED_AARCH64_IFORM_MOVrv,
  AMED_AARCH64_IFORM_MVNv,
  AMED_AARCH64_IFORM_SXTLv,
  AMED_AARCH64_IFORM_SXTL2v,
  AMED_AARCH64_IFORM_UXTLv,
  AMED_AARCH64_IFORM_UXTL2v,
  AMED_AARCH64_IFORM_ABSzk,
  AMED_AARCH64_IFORM_ADCLBz,
  AMED_AARCH64_IFORM_ADCLTz,
  AMED_AARCH64_IFORM_ADDzk,
  AMED_AARCH64_IFORM_ADDzi,
  AMED_AARCH64_IFORM_ADDz,
  AMED_AARCH64_IFORM_ADDHNBz,
  AMED_AARCH64_IFORM_ADDHNTz,
  AMED_AARCH64_IFORM_ADDPzk,
  AMED_AARCH64_IFORM_ADDPLri,
  AMED_AARCH64_IFORM_ADDVLri,
  AMED_AARCH64_IFORM_ADRzm,
  AMED_AARCH64_IFORM_AESDz,
  AMED_AARCH64_IFORM_AESEz,
  AMED_AARCH64_IFORM_AESIMCz,
  AMED_AARCH64_IFORM_AESMCz,
  AMED_AARCH64_IFORM_ANDk,
  AMED_AARCH64_IFORM_ANDSk,
  AMED_AARCH64_IFORM_ANDzk,
  AMED_AARCH64_IFORM_ANDzi,
  AMED_AARCH64_IFORM_ANDz,
  AMED_AARCH64_IFORM_ANDVbkz,
  AMED_AARCH64_IFORM_ANDVhkz,
  AMED_AARCH64_IFORM_ANDVskz,
  AMED_AARCH64_IFORM_ANDVdkz,
  AMED_AARCH64_IFORM_ASRzki,
  AMED_AARCH64_IFORM_ASRzk,
  AMED_AARCH64_IFORM_ASRzi,
  AMED_AARCH64_IFORM_ASRz,
  AMED_AARCH64_IFORM_ASRDzki,
  AMED_AARCH64_IFORM_ASRRzk,
  AMED_AARCH64_IFORM_BCAXz,
  AMED_AARCH64_IFORM_BDEPz,
  AMED_AARCH64_IFORM_BEXTz,
  AMED_AARCH64_IFORM_BFCVTzk,
  AMED_AARCH64_IFORM_BFCVTNTzk,
  AMED_AARCH64_IFORM_BFDOTz,
  AMED_AARCH64_IFORM_BFMLALBz,
  AMED_AARCH64_IFORM_BFMLALTz,
  AMED_AARCH64_IFORM_BFMMLAz,
  AMED_AARCH64_IFORM_BGRPz,
  AMED_AARCH64_IFORM_BICk,
  AMED_AARCH64_IFORM_BICSk,
  AMED_AARCH64_IFORM_BICzk,
  AMED_AARCH64_IFORM_BICz,
  AMED_AARCH64_IFORM_BRKAk,
  AMED_AARCH64_IFORM_BRKASk,
  AMED_AARCH64_IFORM_BRKBk,
  AMED_AARCH64_IFORM_BRKBSk,
  AMED_AARCH64_IFORM_BRKNk,
  AMED_AARCH64_IFORM_BRKNSk,
  AMED_AARCH64_IFORM_BRKPAk,
  AMED_AARCH64_IFORM_BRKPASk,
  AMED_AARCH64_IFORM_BRKPBk,
  AMED_AARCH64_IFORM_BRKPBSk,
  AMED_AARCH64_IFORM_BSL1Nz,
  AMED_AARCH64_IFORM_BSL2Nz,
  AMED_AARCH64_IFORM_BSLz,
  AMED_AARCH64_IFORM_CADDzi,
  AMED_AARCH64_IFORM_CDOTzi,
  AMED_AARCH64_IFORM_CLASTArkz,
  AMED_AARCH64_IFORM_CLASTAbkz,
  AMED_AARCH64_IFORM_CLASTAhkz,
  AMED_AARCH64_IFORM_CLASTAskz,
  AMED_AARCH64_IFORM_CLASTAdkz,
  AMED_AARCH64_IFORM_CLASTAzk,
  AMED_AARCH64_IFORM_CLASTBrkz,
  AMED_AARCH64_IFORM_CLASTBbkz,
  AMED_AARCH64_IFORM_CLASTBhkz,
  AMED_AARCH64_IFORM_CLASTBskz,
  AMED_AARCH64_IFORM_CLASTBdkz,
  AMED_AARCH64_IFORM_CLASTBzk,
  AMED_AARCH64_IFORM_CLSzk,
  AMED_AARCH64_IFORM_CLZzk,
  AMED_AARCH64_IFORM_CMLAzi,
  AMED_AARCH64_IFORM_CMPEQkzi,
  AMED_AARCH64_IFORM_CMPGTkzi,
  AMED_AARCH64_IFORM_CMPGEkzi,
  AMED_AARCH64_IFORM_CMPHIkzi,
  AMED_AARCH64_IFORM_CMPHSkzi,
  AMED_AARCH64_IFORM_CMPLTkzi,
  AMED_AARCH64_IFORM_CMPLEkzi,
  AMED_AARCH64_IFORM_CMPLOkzi,
  AMED_AARCH64_IFORM_CMPLSkzi,
  AMED_AARCH64_IFORM_CMPNEkzi,
  AMED_AARCH64_IFORM_CMPEQkz,
  AMED_AARCH64_IFORM_CMPGTkz,
  AMED_AARCH64_IFORM_CMPGEkz,
  AMED_AARCH64_IFORM_CMPHIkz,
  AMED_AARCH64_IFORM_CMPHSkz,
  AMED_AARCH64_IFORM_CMPLTkz,
  AMED_AARCH64_IFORM_CMPLEkz,
  AMED_AARCH64_IFORM_CMPLOkz,
  AMED_AARCH64_IFORM_CMPLSkz,
  AMED_AARCH64_IFORM_CMPNEkz,
  AMED_AARCH64_IFORM_CNOTzk,
  AMED_AARCH64_IFORM_CNTzk,
  AMED_AARCH64_IFORM_CNTBr,
  AMED_AARCH64_IFORM_CNTDr,
  AMED_AARCH64_IFORM_CNTHr,
  AMED_AARCH64_IFORM_CNTWr,
  AMED_AARCH64_IFORM_CNTPrk,
  AMED_AARCH64_IFORM_COMPACTzk,
  AMED_AARCH64_IFORM_CPYzki,
  AMED_AARCH64_IFORM_CPYzkr,
  AMED_AARCH64_IFORM_CPYzkb,
  AMED_AARCH64_IFORM_CPYzkh,
  AMED_AARCH64_IFORM_CPYzks,
  AMED_AARCH64_IFORM_CPYzkd,
  AMED_AARCH64_IFORM_CTERMEQr,
  AMED_AARCH64_IFORM_CTERMNEr,
  AMED_AARCH64_IFORM_DECBr,
  AMED_AARCH64_IFORM_DECDr,
  AMED_AARCH64_IFORM_DECHr,
  AMED_AARCH64_IFORM_DECWr,
  AMED_AARCH64_IFORM_DECDz,
  AMED_AARCH64_IFORM_DECHz,
  AMED_AARCH64_IFORM_DECWz,
  AMED_AARCH64_IFORM_DECPrk,
  AMED_AARCH64_IFORM_DECPzk,
  AMED_AARCH64_IFORM_DUPzi,
  AMED_AARCH64_IFORM_DUPzr,
  AMED_AARCH64_IFORM_DUPz,
  AMED_AARCH64_IFORM_DUPMzi,
  AMED_AARCH64_IFORM_EOR3z,
  AMED_AARCH64_IFORM_EORk,
  AMED_AARCH64_IFORM_EORSk,
  AMED_AARCH64_IFORM_EORzk,
  AMED_AARCH64_IFORM_EORzi,
  AMED_AARCH64_IFORM_EORz,
  AMED_AARCH64_IFORM_EORBTz,
  AMED_AARCH64_IFORM_EORTBz,
  AMED_AARCH64_IFORM_EORVbkz,
  AMED_AARCH64_IFORM_EORVhkz,
  AMED_AARCH64_IFORM_EORVskz,
  AMED_AARCH64_IFORM_EORVdkz,
  AMED_AARCH64_IFORM_EXTzli,
  AMED_AARCH64_IFORM_EXTzi,
  AMED_AARCH64_IFORM_FABDzk,
  AMED_AARCH64_IFORM_FABSzk,
  AMED_AARCH64_IFORM_FACGTkz,
  AMED_AARCH64_IFORM_FACGEkz,
  AMED_AARCH64_IFORM_FADDzki,
  AMED_AARCH64_IFORM_FADDzk,
  AMED_AARCH64_IFORM_FADDz,
  AMED_AARCH64_IFORM_FADDAhkz,
  AMED_AARCH64_IFORM_FADDAskz,
  AMED_AARCH64_IFORM_FADDAdkz,
  AMED_AARCH64_IFORM_FADDPzk,
  AMED_AARCH64_IFORM_FADDVhkz,
  AMED_AARCH64_IFORM_FADDVskz,
  AMED_AARCH64_IFORM_FADDVdkz,
  AMED_AARCH64_IFORM_FCADDzki,
  AMED_AARCH64_IFORM_FCMEQkzi,
  AMED_AARCH64_IFORM_FCMGTkzi,
  AMED_AARCH64_IFORM_FCMGEkzi,
  AMED_AARCH64_IFORM_FCMLTkzi,
  AMED_AARCH64_IFORM_FCMLEkzi,
  AMED_AARCH64_IFORM_FCMNEkzi,
  AMED_AARCH64_IFORM_FCMEQkz,
  AMED_AARCH64_IFORM_FCMGTkz,
  AMED_AARCH64_IFORM_FCMGEkz,
  AMED_AARCH64_IFORM_FCMNEkz,
  AMED_AARCH64_IFORM_FCMUOkz,
  AMED_AARCH64_IFORM_FCMLAzki,
  AMED_AARCH64_IFORM_FCMLAzi,
  AMED_AARCH64_IFORM_FCPYzki,
  AMED_AARCH64_IFORM_FCVTzk,
  AMED_AARCH64_IFORM_FCVTLTzk,
  AMED_AARCH64_IFORM_FCVTNTzk,
  AMED_AARCH64_IFORM_FCVTXzk,
  AMED_AARCH64_IFORM_FCVTXNTzk,
  AMED_AARCH64_IFORM_FCVTZSzk,
  AMED_AARCH64_IFORM_FCVTZUzk,
  AMED_AARCH64_IFORM_FDIVzk,
  AMED_AARCH64_IFORM_FDIVRzk,
  AMED_AARCH64_IFORM_FDUPzi,
  AMED_AARCH64_IFORM_FEXPAz,
  AMED_AARCH64_IFORM_FLOGBzk,
  AMED_AARCH64_IFORM_FMADzk,
  AMED_AARCH64_IFORM_FMAXzki,
  AMED_AARCH64_IFORM_FMAXzk,
  AMED_AARCH64_IFORM_FMAXNMzki,
  AMED_AARCH64_IFORM_FMAXNMzk,
  AMED_AARCH64_IFORM_FMAXNMPzk,
  AMED_AARCH64_IFORM_FMAXNMVhkz,
  AMED_AARCH64_IFORM_FMAXNMVskz,
  AMED_AARCH64_IFORM_FMAXNMVdkz,
  AMED_AARCH64_IFORM_FMAXPzk,
  AMED_AARCH64_IFORM_FMAXVhkz,
  AMED_AARCH64_IFORM_FMAXVskz,
  AMED_AARCH64_IFORM_FMAXVdkz,
  AMED_AARCH64_IFORM_FMINzki,
  AMED_AARCH64_IFORM_FMINzk,
  AMED_AARCH64_IFORM_FMINNMzki,
  AMED_AARCH64_IFORM_FMINNMzk,
  AMED_AARCH64_IFORM_FMINNMPzk,
  AMED_AARCH64_IFORM_FMINNMVhkz,
  AMED_AARCH64_IFORM_FMINNMVskz,
  AMED_AARCH64_IFORM_FMINNMVdkz,
  AMED_AARCH64_IFORM_FMINPzk,
  AMED_AARCH64_IFORM_FMINVhkz,
  AMED_AARCH64_IFORM_FMINVskz,
  AMED_AARCH64_IFORM_FMINVdkz,
  AMED_AARCH64_IFORM_FMLAzk,
  AMED_AARCH64_IFORM_FMLAz,
  AMED_AARCH64_IFORM_FMLALBz,
  AMED_AARCH64_IFORM_FMLALTz,
  AMED_AARCH64_IFORM_FMLSzk,
  AMED_AARCH64_IFORM_FMLSz,
  AMED_AARCH64_IFORM_FMLSLBz,
  AMED_AARCH64_IFORM_FMLSLTz,
  AMED_AARCH64_IFORM_FMMLAz,
  AMED_AARCH64_IFORM_FMSBzk,
  AMED_AARCH64_IFORM_FMULzki,
  AMED_AARCH64_IFORM_FMULzk,
  AMED_AARCH64_IFORM_FMULz,
  AMED_AARCH64_IFORM_FMULXzk,
  AMED_AARCH64_IFORM_FNEGzk,
  AMED_AARCH64_IFORM_FNMADzk,
  AMED_AARCH64_IFORM_FNMLAzk,
  AMED_AARCH64_IFORM_FNMLSzk,
  AMED_AARCH64_IFORM_FNMSBzk,
  AMED_AARCH64_IFORM_FRECPEz,
  AMED_AARCH64_IFORM_FRECPSz,
  AMED_AARCH64_IFORM_FRECPXzk,
  AMED_AARCH64_IFORM_FRINTIzk,
  AMED_AARCH64_IFORM_FRINTXzk,
  AMED_AARCH64_IFORM_FRINTAzk,
  AMED_AARCH64_IFORM_FRINTNzk,
  AMED_AARCH64_IFORM_FRINTZzk,
  AMED_AARCH64_IFORM_FRINTMzk,
  AMED_AARCH64_IFORM_FRINTPzk,
  AMED_AARCH64_IFORM_FRSQRTEz,
  AMED_AARCH64_IFORM_FRSQRTSz,
  AMED_AARCH64_IFORM_FSCALEzk,
  AMED_AARCH64_IFORM_FSQRTzk,
  AMED_AARCH64_IFORM_FSUBzki,
  AMED_AARCH64_IFORM_FSUBzk,
  AMED_AARCH64_IFORM_FSUBz,
  AMED_AARCH64_IFORM_FSUBRzki,
  AMED_AARCH64_IFORM_FSUBRzk,
  AMED_AARCH64_IFORM_FTMADzi,
  AMED_AARCH64_IFORM_FTSMULz,
  AMED_AARCH64_IFORM_FTSSELz,
  AMED_AARCH64_IFORM_HISTCNTzk,
  AMED_AARCH64_IFORM_HISTSEGz,
  AMED_AARCH64_IFORM_INCBr,
  AMED_AARCH64_IFORM_INCDr,
  AMED_AARCH64_IFORM_INCHr,
  AMED_AARCH64_IFORM_INCWr,
  AMED_AARCH64_IFORM_INCDz,
  AMED_AARCH64_IFORM_INCHz,
  AMED_AARCH64_IFORM_INCWz,
  AMED_AARCH64_IFORM_INCPrk,
  AMED_AARCH64_IFORM_INCPzk,
  AMED_AARCH64_IFORM_INDEXzi,
  AMED_AARCH64_IFORM_INDEXzir,
  AMED_AARCH64_IFORM_INDEXzri,
  AMED_AARCH64_IFORM_INDEXzr,
  AMED_AARCH64_IFORM_INSRzr,
  AMED_AARCH64_IFORM_INSRzb,
  AMED_AARCH64_IFORM_INSRzh,
  AMED_AARCH64_IFORM_INSRzs,
  AMED_AARCH64_IFORM_INSRzd,
  AMED_AARCH64_IFORM_LASTArkz,
  AMED_AARCH64_IFORM_LASTAbkz,
  AMED_AARCH64_IFORM_LASTAhkz,
  AMED_AARCH64_IFORM_LASTAskz,
  AMED_AARCH64_IFORM_LASTAdkz,
  AMED_AARCH64_IFORM_LASTBrkz,
  AMED_AARCH64_IFORM_LASTBbkz,
  AMED_AARCH64_IFORM_LASTBhkz,
  AMED_AARCH64_IFORM_LASTBskz,
  AMED_AARCH64_IFORM_LASTBdkz,
  AMED_AARCH64_IFORM_LD1Blkm,
  AMED_AARCH64_IFORM_LD1Dlkm,
  AMED_AARCH64_IFORM_LD1Hlkm,
  AMED_AARCH64_IFORM_LD1RBlkm,
  AMED_AARCH64_IFORM_LD1RDlkm,
  AMED_AARCH64_IFORM_LD1RHlkm,
  AMED_AARCH64_IFORM_LD1ROBlkm,
  AMED_AARCH64_IFORM_LD1RODlkm,
  AMED_AARCH64_IFORM_LD1ROHlkm,
  AMED_AARCH64_IFORM_LD1ROWlkm,
  AMED_AARCH64_IFORM_LD1RQBlkm,
  AMED_AARCH64_IFORM_LD1RQDlkm,
  AMED_AARCH64_IFORM_LD1RQHlkm,
  AMED_AARCH64_IFORM_LD1RQWlkm,
  AMED_AARCH64_IFORM_LD1RSBlkm,
  AMED_AARCH64_IFORM_LD1RSHlkm,
  AMED_AARCH64_IFORM_LD1RSWlkm,
  AMED_AARCH64_IFORM_LD1RWlkm,
  AMED_AARCH64_IFORM_LD1SBlkm,
  AMED_AARCH64_IFORM_LD1SHlkm,
  AMED_AARCH64_IFORM_LD1SWlkm,
  AMED_AARCH64_IFORM_LD1Wlkm,
  AMED_AARCH64_IFORM_LD2Blkm,
  AMED_AARCH64_IFORM_LD2Dlkm,
  AMED_AARCH64_IFORM_LD2Hlkm,
  AMED_AARCH64_IFORM_LD2Wlkm,
  AMED_AARCH64_IFORM_LD3Blkm,
  AMED_AARCH64_IFORM_LD3Dlkm,
  AMED_AARCH64_IFORM_LD3Hlkm,
  AMED_AARCH64_IFORM_LD3Wlkm,
  AMED_AARCH64_IFORM_LD4Blkm,
  AMED_AARCH64_IFORM_LD4Dlkm,
  AMED_AARCH64_IFORM_LD4Hlkm,
  AMED_AARCH64_IFORM_LD4Wlkm,
  AMED_AARCH64_IFORM_LDFF1Blkm,
  AMED_AARCH64_IFORM_LDFF1Dlkm,
  AMED_AARCH64_IFORM_LDFF1Hlkm,
  AMED_AARCH64_IFORM_LDFF1SBlkm,
  AMED_AARCH64_IFORM_LDFF1SHlkm,
  AMED_AARCH64_IFORM_LDFF1SWlkm,
  AMED_AARCH64_IFORM_LDFF1Wlkm,
  AMED_AARCH64_IFORM_LDNF1Blkm,
  AMED_AARCH64_IFORM_LDNF1Dlkm,
  AMED_AARCH64_IFORM_LDNF1Hlkm,
  AMED_AARCH64_IFORM_LDNF1SBlkm,
  AMED_AARCH64_IFORM_LDNF1SHlkm,
  AMED_AARCH64_IFORM_LDNF1SWlkm,
  AMED_AARCH64_IFORM_LDNF1Wlkm,
  AMED_AARCH64_IFORM_LDNT1Blkm,
  AMED_AARCH64_IFORM_LDNT1Dlkm,
  AMED_AARCH64_IFORM_LDNT1Hlkm,
  AMED_AARCH64_IFORM_LDNT1SBlkm,
  AMED_AARCH64_IFORM_LDNT1SHlkm,
  AMED_AARCH64_IFORM_LDNT1SWlkm,
  AMED_AARCH64_IFORM_LDNT1Wlkm,
  AMED_AARCH64_IFORM_LDRkm,
  AMED_AARCH64_IFORM_LDRzm,
  AMED_AARCH64_IFORM_LSLzki,
  AMED_AARCH64_IFORM_LSLzk,
  AMED_AARCH64_IFORM_LSLzi,
  AMED_AARCH64_IFORM_LSLz,
  AMED_AARCH64_IFORM_LSLRzk,
  AMED_AARCH64_IFORM_LSRzki,
  AMED_AARCH64_IFORM_LSRzk,
  AMED_AARCH64_IFORM_LSRzi,
  AMED_AARCH64_IFORM_LSRz,
  AMED_AARCH64_IFORM_LSRRzk,
  AMED_AARCH64_IFORM_MADzk,
  AMED_AARCH64_IFORM_MATCHkz,
  AMED_AARCH64_IFORM_MLAzk,
  AMED_AARCH64_IFORM_MLAz,
  AMED_AARCH64_IFORM_MLSzk,
  AMED_AARCH64_IFORM_MLSz,
  AMED_AARCH64_IFORM_MOVPRFXzk,
  AMED_AARCH64_IFORM_MOVPRFXz,
  AMED_AARCH64_IFORM_MSBzk,
  AMED_AARCH64_IFORM_MULzk,
  AMED_AARCH64_IFORM_MULzi,
  AMED_AARCH64_IFORM_MULz,
  AMED_AARCH64_IFORM_NANDk,
  AMED_AARCH64_IFORM_NANDSk,
  AMED_AARCH64_IFORM_NBSLz,
  AMED_AARCH64_IFORM_NEGzk,
  AMED_AARCH64_IFORM_NMATCHkz,
  AMED_AARCH64_IFORM_NORk,
  AMED_AARCH64_IFORM_NORSk,
  AMED_AARCH64_IFORM_NOTzk,
  AMED_AARCH64_IFORM_ORNk,
  AMED_AARCH64_IFORM_ORNSk,
  AMED_AARCH64_IFORM_ORRk,
  AMED_AARCH64_IFORM_ORRSk,
  AMED_AARCH64_IFORM_ORRzk,
  AMED_AARCH64_IFORM_ORRzi,
  AMED_AARCH64_IFORM_ORRz,
  AMED_AARCH64_IFORM_ORVbkz,
  AMED_AARCH64_IFORM_ORVhkz,
  AMED_AARCH64_IFORM_ORVskz,
  AMED_AARCH64_IFORM_ORVdkz,
  AMED_AARCH64_IFORM_PFALSEk,
  AMED_AARCH64_IFORM_PFIRSTk,
  AMED_AARCH64_IFORM_PMULz,
  AMED_AARCH64_IFORM_PMULLBz,
  AMED_AARCH64_IFORM_PMULLTz,
  AMED_AARCH64_IFORM_PNEXTk,
  AMED_AARCH64_IFORM_PRFBkm,
  AMED_AARCH64_IFORM_PRFDkm,
  AMED_AARCH64_IFORM_PRFHkm,
  AMED_AARCH64_IFORM_PRFWkm,
  AMED_AARCH64_IFORM_PTESTk,
  AMED_AARCH64_IFORM_PTRUEk,
  AMED_AARCH64_IFORM_PTRUESk,
  AMED_AARCH64_IFORM_PUNPKHIk,
  AMED_AARCH64_IFORM_PUNPKLOk,
  AMED_AARCH64_IFORM_RADDHNBz,
  AMED_AARCH64_IFORM_RADDHNTz,
  AMED_AARCH64_IFORM_RAX1z,
  AMED_AARCH64_IFORM_RBITzk,
  AMED_AARCH64_IFORM_RDFFRk,
  AMED_AARCH64_IFORM_RDFFRSk,
  AMED_AARCH64_IFORM_RDVLri,
  AMED_AARCH64_IFORM_REVk,
  AMED_AARCH64_IFORM_REVz,
  AMED_AARCH64_IFORM_REVBzk,
  AMED_AARCH64_IFORM_REVHzk,
  AMED_AARCH64_IFORM_REVWzk,
  AMED_AARCH64_IFORM_RSHRNBzi,
  AMED_AARCH64_IFORM_RSHRNTzi,
  AMED_AARCH64_IFORM_RSUBHNBz,
  AMED_AARCH64_IFORM_RSUBHNTz,
  AMED_AARCH64_IFORM_SABAz,
  AMED_AARCH64_IFORM_SABALBz,
  AMED_AARCH64_IFORM_SABALTz,
  AMED_AARCH64_IFORM_SABDzk,
  AMED_AARCH64_IFORM_SABDLBz,
  AMED_AARCH64_IFORM_SABDLTz,
  AMED_AARCH64_IFORM_SADALPzk,
  AMED_AARCH64_IFORM_SADDLBz,
  AMED_AARCH64_IFORM_SADDLBTz,
  AMED_AARCH64_IFORM_SADDLTz,
  AMED_AARCH64_IFORM_SADDVdkz,
  AMED_AARCH64_IFORM_SADDWBz,
  AMED_AARCH64_IFORM_SADDWTz,
  AMED_AARCH64_IFORM_SBCLBz,
  AMED_AARCH64_IFORM_SBCLTz,
  AMED_AARCH64_IFORM_SCVTFzk,
  AMED_AARCH64_IFORM_SDIVzk,
  AMED_AARCH64_IFORM_SDIVRzk,
  AMED_AARCH64_IFORM_SDOTz,
  AMED_AARCH64_IFORM_SELk,
  AMED_AARCH64_IFORM_SELzk,
  AMED_AARCH64_IFORM_SETFFR,
  AMED_AARCH64_IFORM_SHADDzk,
  AMED_AARCH64_IFORM_SHRNBzi,
  AMED_AARCH64_IFORM_SHRNTzi,
  AMED_AARCH64_IFORM_SHSUBzk,
  AMED_AARCH64_IFORM_SHSUBRzk,
  AMED_AARCH64_IFORM_SLIzi,
  AMED_AARCH64_IFORM_SM4Ez,
  AMED_AARCH64_IFORM_SM4EKEYz,
  AMED_AARCH64_IFORM_SMAXzk,
  AMED_AARCH64_IFORM_SMAXzi,
  AMED_AARCH64_IFORM_SMAXPzk,
  AMED_AARCH64_IFORM_SMAXVbkz,
  AMED_AARCH64_IFORM_SMAXVhkz,
  AMED_AARCH64_IFORM_SMAXVskz,
  AMED_AARCH64_IFORM_SMAXVdkz,
  AMED_AARCH64_IFORM_SMINzk,
  AMED_AARCH64_IFORM_SMINzi,
  AMED_AARCH64_IFORM_SMINPzk,
  AMED_AARCH64_IFORM_SMINVbkz,
  AMED_AARCH64_IFORM_SMINVhkz,
  AMED_AARCH64_IFORM_SMINVskz,
  AMED_AARCH64_IFORM_SMINVdkz,
  AMED_AARCH64_IFORM_SMLALBz,
  AMED_AARCH64_IFORM_SMLALTz,
  AMED_AARCH64_IFORM_SMLSLBz,
  AMED_AARCH64_IFORM_SMLSLTz,
  AMED_AARCH64_IFORM_SMMLAz,
  AMED_AARCH64_IFORM_SMULHzk,
  AMED_AARCH64_IFORM_SMULHz,
  AMED_AARCH64_IFORM_SMULLBz,
  AMED_AARCH64_IFORM_SMULLTz,
  AMED_AARCH64_IFORM_SPLICEzkl,
  AMED_AARCH64_IFORM_SPLICEzk,
  AMED_AARCH64_IFORM_SQABSzk,
  AMED_AARCH64_IFORM_SQADDzk,
  AMED_AARCH64_IFORM_SQADDzi,
  AMED_AARCH64_IFORM_SQADDz,
  AMED_AARCH64_IFORM_SQCADDzi,
  AMED_AARCH64_IFORM_SQDECBr,
  AMED_AARCH64_IFORM_SQDECDr,
  AMED_AARCH64_IFORM_SQDECDz,
  AMED_AARCH64_IFORM_SQDECHr,
  AMED_AARCH64_IFORM_SQDECHz,
  AMED_AARCH64_IFORM_SQDECPrk,
  AMED_AARCH64_IFORM_SQDECPzk,
  AMED_AARCH64_IFORM_SQDECWr,
  AMED_AARCH64_IFORM_SQDECWz,
  AMED_AARCH64_IFORM_SQDMLALBz,
  AMED_AARCH64_IFORM_SQDMLALBTz,
  AMED_AARCH64_IFORM_SQDMLALTz,
  AMED_AARCH64_IFORM_SQDMLSLBz,
  AMED_AARCH64_IFORM_SQDMLSLBTz,
  AMED_AARCH64_IFORM_SQDMLSLTz,
  AMED_AARCH64_IFORM_SQDMULHz,
  AMED_AARCH64_IFORM_SQDMULLBz,
  AMED_AARCH64_IFORM_SQDMULLTz,
  AMED_AARCH64_IFORM_SQINCBr,
  AMED_AARCH64_IFORM_SQINCDr,
  AMED_AARCH64_IFORM_SQINCDz,
  AMED_AARCH64_IFORM_SQINCHr,
  AMED_AARCH64_IFORM_SQINCHz,
  AMED_AARCH64_IFORM_SQINCPrk,
  AMED_AARCH64_IFORM_SQINCPzk,
  AMED_AARCH64_IFORM_SQINCWr,
  AMED_AARCH64_IFORM_SQINCWz,
  AMED_AARCH64_IFORM_SQNEGzk,
  AMED_AARCH64_IFORM_SQRDCMLAHzi,
  AMED_AARCH64_IFORM_SQRDMLAHz,
  AMED_AARCH64_IFORM_SQRDMLSHz,
  AMED_AARCH64_IFORM_SQRDMULHz,
  AMED_AARCH64_IFORM_SQRSHLzk,
  AMED_AARCH64_IFORM_SQRSHLRzk,
  AMED_AARCH64_IFORM_SQRSHRNBzi,
  AMED_AARCH64_IFORM_SQRSHRNTzi,
  AMED_AARCH64_IFORM_SQRSHRUNBzi,
  AMED_AARCH64_IFORM_SQRSHRUNTzi,
  AMED_AARCH64_IFORM_SQSHLzki,
  AMED_AARCH64_IFORM_SQSHLzk,
  AMED_AARCH64_IFORM_SQSHLRzk,
  AMED_AARCH64_IFORM_SQSHLUzki,
  AMED_AARCH64_IFORM_SQSHRNBzi,
  AMED_AARCH64_IFORM_SQSHRNTzi,
  AMED_AARCH64_IFORM_SQSHRUNBzi,
  AMED_AARCH64_IFORM_SQSHRUNTzi,
  AMED_AARCH64_IFORM_SQSUBzk,
  AMED_AARCH64_IFORM_SQSUBzi,
  AMED_AARCH64_IFORM_SQSUBz,
  AMED_AARCH64_IFORM_SQSUBRzk,
  AMED_AARCH64_IFORM_SQXTNBz,
  AMED_AARCH64_IFORM_SQXTNTz,
  AMED_AARCH64_IFORM_SQXTUNBz,
  AMED_AARCH64_IFORM_SQXTUNTz,
  AMED_AARCH64_IFORM_SRHADDzk,
  AMED_AARCH64_IFORM_SRIzi,
  AMED_AARCH64_IFORM_SRSHLzk,
  AMED_AARCH64_IFORM_SRSHLRzk,
  AMED_AARCH64_IFORM_SRSHRzki,
  AMED_AARCH64_IFORM_SRSRAzi,
  AMED_AARCH64_IFORM_SSHLLBzi,
  AMED_AARCH64_IFORM_SSHLLTzi,
  AMED_AARCH64_IFORM_SSRAzi,
  AMED_AARCH64_IFORM_SSUBLBz,
  AMED_AARCH64_IFORM_SSUBLBTz,
  AMED_AARCH64_IFORM_SSUBLTz,
  AMED_AARCH64_IFORM_SSUBLTBz,
  AMED_AARCH64_IFORM_SSUBWBz,
  AMED_AARCH64_IFORM_SSUBWTz,
  AMED_AARCH64_IFORM_ST1Blkm,
  AMED_AARCH64_IFORM_ST1Dlkm,
  AMED_AARCH64_IFORM_ST1Hlkm,
  AMED_AARCH64_IFORM_ST1Wlkm,
  AMED_AARCH64_IFORM_ST2Blkm,
  AMED_AARCH64_IFORM_ST2Dlkm,
  AMED_AARCH64_IFORM_ST2Hlkm,
  AMED_AARCH64_IFORM_ST2Wlkm,
  AMED_AARCH64_IFORM_ST3Blkm,
  AMED_AARCH64_IFORM_ST3Dlkm,
  AMED_AARCH64_IFORM_ST3Hlkm,
  AMED_AARCH64_IFORM_ST3Wlkm,
  AMED_AARCH64_IFORM_ST4Blkm,
  AMED_AARCH64_IFORM_ST4Dlkm,
  AMED_AARCH64_IFORM_ST4Hlkm,
  AMED_AARCH64_IFORM_ST4Wlkm,
  AMED_AARCH64_IFORM_STNT1Blkm,
  AMED_AARCH64_IFORM_STNT1Dlkm,
  AMED_AARCH64_IFORM_STNT1Hlkm,
  AMED_AARCH64_IFORM_STNT1Wlkm,
  AMED_AARCH64_IFORM_STRkm,
  AMED_AARCH64_IFORM_STRzm,
  AMED_AARCH64_IFORM_SUBzk,
  AMED_AARCH64_IFORM_SUBzi,
  AMED_AARCH64_IFORM_SUBz,
  AMED_AARCH64_IFORM_SUBHNBz,
  AMED_AARCH64_IFORM_SUBHNTz,
  AMED_AARCH64_IFORM_SUBRzk,
  AMED_AARCH64_IFORM_SUBRzi,
  AMED_AARCH64_IFORM_SUDOTz,
  AMED_AARCH64_IFORM_SUNPKHIz,
  AMED_AARCH64_IFORM_SUNPKLOz,
  AMED_AARCH64_IFORM_SUQADDzk,
  AMED_AARCH64_IFORM_SXTBzk,
  AMED_AARCH64_IFORM_SXTHzk,
  AMED_AARCH64_IFORM_SXTWzk,
  AMED_AARCH64_IFORM_TBLzl,
  AMED_AARCH64_IFORM_TBXz,
  AMED_AARCH64_IFORM_TRN1k,
  AMED_AARCH64_IFORM_TRN2k,
  AMED_AARCH64_IFORM_TRN1z,
  AMED_AARCH64_IFORM_TRN2z,
  AMED_AARCH64_IFORM_UABAz,
  AMED_AARCH64_IFORM_UABALBz,
  AMED_AARCH64_IFORM_UABALTz,
  AMED_AARCH64_IFORM_UABDzk,
  AMED_AARCH64_IFORM_UABDLBz,
  AMED_AARCH64_IFORM_UABDLTz,
  AMED_AARCH64_IFORM_UADALPzk,
  AMED_AARCH64_IFORM_UADDLBz,
  AMED_AARCH64_IFORM_UADDLTz,
  AMED_AARCH64_IFORM_UADDVdkz,
  AMED_AARCH64_IFORM_UADDWBz,
  AMED_AARCH64_IFORM_UADDWTz,
  AMED_AARCH64_IFORM_UCVTFzk,
  AMED_AARCH64_IFORM_UDIVzk,
  AMED_AARCH64_IFORM_UDIVRzk,
  AMED_AARCH64_IFORM_UDOTz,
  AMED_AARCH64_IFORM_UHADDzk,
  AMED_AARCH64_IFORM_UHSUBzk,
  AMED_AARCH64_IFORM_UHSUBRzk,
  AMED_AARCH64_IFORM_UMAXzk,
  AMED_AARCH64_IFORM_UMAXzi,
  AMED_AARCH64_IFORM_UMAXPzk,
  AMED_AARCH64_IFORM_UMAXVbkz,
  AMED_AARCH64_IFORM_UMAXVhkz,
  AMED_AARCH64_IFORM_UMAXVskz,
  AMED_AARCH64_IFORM_UMAXVdkz,
  AMED_AARCH64_IFORM_UMINzk,
  AMED_AARCH64_IFORM_UMINzi,
  AMED_AARCH64_IFORM_UMINPzk,
  AMED_AARCH64_IFORM_UMINVbkz,
  AMED_AARCH64_IFORM_UMINVhkz,
  AMED_AARCH64_IFORM_UMINVskz,
  AMED_AARCH64_IFORM_UMINVdkz,
  AMED_AARCH64_IFORM_UMLALBz,
  AMED_AARCH64_IFORM_UMLALTz,
  AMED_AARCH64_IFORM_UMLSLBz,
  AMED_AARCH64_IFORM_UMLSLTz,
  AMED_AARCH64_IFORM_UMMLAz,
  AMED_AARCH64_IFORM_UMULHzk,
  AMED_AARCH64_IFORM_UMULHz,
  AMED_AARCH64_IFORM_UMULLBz,
  AMED_AARCH64_IFORM_UMULLTz,
  AMED_AARCH64_IFORM_UQADDzk,
  AMED_AARCH64_IFORM_UQADDzi,
  AMED_AARCH64_IFORM_UQADDz,
  AMED_AARCH64_IFORM_UQDECBr,
  AMED_AARCH64_IFORM_UQDECDr,
  AMED_AARCH64_IFORM_UQDECDz,
  AMED_AARCH64_IFORM_UQDECHr,
  AMED_AARCH64_IFORM_UQDECHz,
  AMED_AARCH64_IFORM_UQDECPrk,
  AMED_AARCH64_IFORM_UQDECPzk,
  AMED_AARCH64_IFORM_UQDECWr,
  AMED_AARCH64_IFORM_UQDECWz,
  AMED_AARCH64_IFORM_UQINCBr,
  AMED_AARCH64_IFORM_UQINCDr,
  AMED_AARCH64_IFORM_UQINCDz,
  AMED_AARCH64_IFORM_UQINCHr,
  AMED_AARCH64_IFORM_UQINCHz,
  AMED_AARCH64_IFORM_UQINCPrk,
  AMED_AARCH64_IFORM_UQINCPzk,
  AMED_AARCH64_IFORM_UQINCWr,
  AMED_AARCH64_IFORM_UQINCWz,
  AMED_AARCH64_IFORM_UQRSHLzk,
  AMED_AARCH64_IFORM_UQRSHLRzk,
  AMED_AARCH64_IFORM_UQRSHRNBzi,
  AMED_AARCH64_IFORM_UQRSHRNTzi,
  AMED_AARCH64_IFORM_UQSHLzki,
  AMED_AARCH64_IFORM_UQSHLzk,
  AMED_AARCH64_IFORM_UQSHLRzk,
  AMED_AARCH64_IFORM_UQSHRNBzi,
  AMED_AARCH64_IFORM_UQSHRNTzi,
  AMED_AARCH64_IFORM_UQSUBzk,
  AMED_AARCH64_IFORM_UQSUBzi,
  AMED_AARCH64_IFORM_UQSUBz,
  AMED_AARCH64_IFORM_UQSUBRzk,
  AMED_AARCH64_IFORM_UQXTNBz,
  AMED_AARCH64_IFORM_UQXTNTz,
  AMED_AARCH64_IFORM_URECPEzk,
  AMED_AARCH64_IFORM_URHADDzk,
  AMED_AARCH64_IFORM_URSHLzk,
  AMED_AARCH64_IFORM_URSHLRzk,
  AMED_AARCH64_IFORM_URSHRzki,
  AMED_AARCH64_IFORM_URSQRTEzk,
  AMED_AARCH64_IFORM_URSRAzi,
  AMED_AARCH64_IFORM_USDOTz,
  AMED_AARCH64_IFORM_USHLLBzi,
  AMED_AARCH64_IFORM_USHLLTzi,
  AMED_AARCH64_IFORM_USMMLAz,
  AMED_AARCH64_IFORM_USQADDzk,
  AMED_AARCH64_IFORM_USRAzi,
  AMED_AARCH64_IFORM_USUBLBz,
  AMED_AARCH64_IFORM_USUBLTz,
  AMED_AARCH64_IFORM_USUBWBz,
  AMED_AARCH64_IFORM_USUBWTz,
  AMED_AARCH64_IFORM_UUNPKHIz,
  AMED_AARCH64_IFORM_UUNPKLOz,
  AMED_AARCH64_IFORM_UXTBzk,
  AMED_AARCH64_IFORM_UXTHzk,
  AMED_AARCH64_IFORM_UXTWzk,
  AMED_AARCH64_IFORM_UZP1k,
  AMED_AARCH64_IFORM_UZP2k,
  AMED_AARCH64_IFORM_UZP1z,
  AMED_AARCH64_IFORM_UZP2z,
  AMED_AARCH64_IFORM_WHILEGEkr,
  AMED_AARCH64_IFORM_WHILEGTkr,
  AMED_AARCH64_IFORM_WHILEHIkr,
  AMED_AARCH64_IFORM_WHILEHSkr,
  AMED_AARCH64_IFORM_WHILELEkr,
  AMED_AARCH64_IFORM_WHILELOkr,
  AMED_AARCH64_IFORM_WHILELSkr,
  AMED_AARCH64_IFORM_WHILELTkr,
  AMED_AARCH64_IFORM_WHILERWkr,
  AMED_AARCH64_IFORM_WHILEWRkr,
  AMED_AARCH64_IFORM_WRFFRk,
  AMED_AARCH64_IFORM_XARzi,
  AMED_AARCH64_IFORM_ZIP2k,
  AMED_AARCH64_IFORM_ZIP1k,
  AMED_AARCH64_IFORM_ZIP2z,
  AMED_AARCH64_IFORM_ZIP1z,
  AMED_AARCH64_IFORM_BICzi,
  AMED_AARCH64_IFORM_EONzi,
  AMED_AARCH64_IFORM_FACLEkz,
  AMED_AARCH64_IFORM_FACLTkz,
  AMED_AARCH64_IFORM_FCMLEkz,
  AMED_AARCH64_IFORM_FCMLTkz,
  AMED_AARCH64_IFORM_FMOVzki,
  AMED_AARCH64_IFORM_FMOVzi,
  AMED_AARCH64_IFORM_MOVk,
  AMED_AARCH64_IFORM_MOVzki,
  AMED_AARCH64_IFORM_MOVzkr,
  AMED_AARCH64_IFORM_MOVzkb,
  AMED_AARCH64_IFORM_MOVzkh,
  AMED_AARCH64_IFORM_MOVzks,
  AMED_AARCH64_IFORM_MOVzkd,
  AMED_AARCH64_IFORM_MOVzi,
  AMED_AARCH64_IFORM_MOVzr,
  AMED_AARCH64_IFORM_MOVz,
  AMED_AARCH64_IFORM_MOVzb,
  AMED_AARCH64_IFORM_MOVzh,
  AMED_AARCH64_IFORM_MOVzs,
  AMED_AARCH64_IFORM_MOVzd,
  AMED_AARCH64_IFORM_MOVzq,
  AMED_AARCH64_IFORM_MOVzk,
  AMED_AARCH64_IFORM_MOVSk,
  AMED_AARCH64_IFORM_NOTk,
  AMED_AARCH64_IFORM_NOTSk,
  AMED_AARCH64_IFORM_ORNzi,
} amed_aarch64_iform;

#define AMED_AARCH64_VDT_MAX_TEXT_LENGTH (4 + 1)

typedef enum _amed_aarch64_vdt
{
  AMED_AARCH64_VDT_NONE,
  AMED_AARCH64_VDT_16B,
  AMED_AARCH64_VDT_1D,
  AMED_AARCH64_VDT_1Q,
  AMED_AARCH64_VDT_2D,
  AMED_AARCH64_VDT_2H,
  AMED_AARCH64_VDT_2S,
  AMED_AARCH64_VDT_4B,
  AMED_AARCH64_VDT_4H,
  AMED_AARCH64_VDT_4S,
  AMED_AARCH64_VDT_8B,
  AMED_AARCH64_VDT_8H,
  AMED_AARCH64_VDT_B,
  AMED_AARCH64_VDT_D,
  AMED_AARCH64_VDT_H,
  AMED_AARCH64_VDT_Q,
  AMED_AARCH64_VDT_S,
} amed_aarch64_vdt;

#define AMED_AARCH64_PRF_OP_MAX_TEXT_LENGTH (9 + 1)

typedef enum _amed_aarch64_prf_op
{
  AMED_AARCH64_PRF_OP_NONE,
  AMED_AARCH64_PRF_OP_PLDL1KEEP,
  AMED_AARCH64_PRF_OP_PLDL1STRM,
  AMED_AARCH64_PRF_OP_PLDL2KEEP,
  AMED_AARCH64_PRF_OP_PLDL2STRM,
  AMED_AARCH64_PRF_OP_PLDL3KEEP,
  AMED_AARCH64_PRF_OP_PLDL3STRM,
  AMED_AARCH64_PRF_OP_PSTL1KEEP,
  AMED_AARCH64_PRF_OP_PSTL1STRM,
  AMED_AARCH64_PRF_OP_PSTL2KEEP,
  AMED_AARCH64_PRF_OP_PSTL2STRM,
  AMED_AARCH64_PRF_OP_PSTL3KEEP,
  AMED_AARCH64_PRF_OP_PSTL3STRM,
  AMED_AARCH64_PRF_OP_PLIL1KEEP,
  AMED_AARCH64_PRF_OP_PLIL1STRM,
  AMED_AARCH64_PRF_OP_PLIL2KEEP,
  AMED_AARCH64_PRF_OP_PLIL2STRM,
  AMED_AARCH64_PRF_OP_PLIL3KEEP,
  AMED_AARCH64_PRF_OP_PLIL3STRM,
  AMED_AARCH64_PRF_OP_uimm4,
} amed_aarch64_prf_op;

#define AMED_AARCH64_ENCODING_MAX_TEXT_LENGTH (29 + 1)

typedef enum _amed_aarch64_encoding
{
  AMED_AARCH64_ENCODING_NONE,
  AMED_AARCH64_ENCODING_invalid, //!< <a href="../target/aarch64/invalid.html#invalid">INVALID</a>
  AMED_AARCH64_ENCODING_ADC_32_addsub_carry, //!< <a href="../target/aarch64/ADC.html#ADC_32_addsub_carry">32-bit</a>
  AMED_AARCH64_ENCODING_ADC_64_addsub_carry, //!< <a href="../target/aarch64/ADC.html#ADC_64_addsub_carry">64-bit</a>
  AMED_AARCH64_ENCODING_ADCS_32_addsub_carry, //!< <a href="../target/aarch64/ADCS.html#ADCS_32_addsub_carry">32-bit</a>
  AMED_AARCH64_ENCODING_ADCS_64_addsub_carry, //!< <a href="../target/aarch64/ADCS.html#ADCS_64_addsub_carry">64-bit</a>
  AMED_AARCH64_ENCODING_ADD_32_addsub_ext, //!< <a href="../target/aarch64/ADD_addsub_ext.html#ADD_32_addsub_ext">32-bit</a>
  AMED_AARCH64_ENCODING_ADD_64_addsub_ext, //!< <a href="../target/aarch64/ADD_addsub_ext.html#ADD_64_addsub_ext">64-bit</a>
  AMED_AARCH64_ENCODING_ADD_32_addsub_imm, //!< <a href="../target/aarch64/ADD_addsub_imm.html#ADD_32_addsub_imm">32-bit</a>
  AMED_AARCH64_ENCODING_ADD_64_addsub_imm, //!< <a href="../target/aarch64/ADD_addsub_imm.html#ADD_64_addsub_imm">64-bit</a>
  AMED_AARCH64_ENCODING_ADD_32_addsub_shift, //!< <a href="../target/aarch64/ADD_addsub_shift.html#ADD_32_addsub_shift">32-bit</a>
  AMED_AARCH64_ENCODING_ADD_64_addsub_shift, //!< <a href="../target/aarch64/ADD_addsub_shift.html#ADD_64_addsub_shift">64-bit</a>
  AMED_AARCH64_ENCODING_ADDG_64_addsub_immtags, //!< <a href="../target/aarch64/ADDG.html#ADDG_64_addsub_immtags">Integer</a>
  AMED_AARCH64_ENCODING_ADDS_32S_addsub_ext, //!< <a href="../target/aarch64/ADDS_addsub_ext.html#ADDS_32S_addsub_ext">32-bit</a>
  AMED_AARCH64_ENCODING_ADDS_64S_addsub_ext, //!< <a href="../target/aarch64/ADDS_addsub_ext.html#ADDS_64S_addsub_ext">64-bit</a>
  AMED_AARCH64_ENCODING_ADDS_32S_addsub_imm, //!< <a href="../target/aarch64/ADDS_addsub_imm.html#ADDS_32S_addsub_imm">32-bit</a>
  AMED_AARCH64_ENCODING_ADDS_64S_addsub_imm, //!< <a href="../target/aarch64/ADDS_addsub_imm.html#ADDS_64S_addsub_imm">64-bit</a>
  AMED_AARCH64_ENCODING_ADDS_32_addsub_shift, //!< <a href="../target/aarch64/ADDS_addsub_shift.html#ADDS_32_addsub_shift">32-bit</a>
  AMED_AARCH64_ENCODING_ADDS_64_addsub_shift, //!< <a href="../target/aarch64/ADDS_addsub_shift.html#ADDS_64_addsub_shift">64-bit</a>
  AMED_AARCH64_ENCODING_ADR_only_pcreladdr, //!< <a href="../target/aarch64/ADR.html#ADR_only_pcreladdr">Literal</a>
  AMED_AARCH64_ENCODING_ADRP_only_pcreladdr, //!< <a href="../target/aarch64/ADRP.html#ADRP_only_pcreladdr">Literal</a>
  AMED_AARCH64_ENCODING_AND_32_log_imm, //!< <a href="../target/aarch64/AND_log_imm.html#AND_32_log_imm">32-bit</a>
  AMED_AARCH64_ENCODING_AND_64_log_imm, //!< <a href="../target/aarch64/AND_log_imm.html#AND_64_log_imm">64-bit</a>
  AMED_AARCH64_ENCODING_AND_32_log_shift, //!< <a href="../target/aarch64/AND_log_shift.html#AND_32_log_shift">32-bit</a>
  AMED_AARCH64_ENCODING_AND_64_log_shift, //!< <a href="../target/aarch64/AND_log_shift.html#AND_64_log_shift">64-bit</a>
  AMED_AARCH64_ENCODING_ANDS_32S_log_imm, //!< <a href="../target/aarch64/ANDS_log_imm.html#ANDS_32S_log_imm">32-bit</a>
  AMED_AARCH64_ENCODING_ANDS_64S_log_imm, //!< <a href="../target/aarch64/ANDS_log_imm.html#ANDS_64S_log_imm">64-bit</a>
  AMED_AARCH64_ENCODING_ANDS_32_log_shift, //!< <a href="../target/aarch64/ANDS_log_shift.html#ANDS_32_log_shift">32-bit</a>
  AMED_AARCH64_ENCODING_ANDS_64_log_shift, //!< <a href="../target/aarch64/ANDS_log_shift.html#ANDS_64_log_shift">64-bit</a>
  AMED_AARCH64_ENCODING_ASRV_32_dp_2src, //!< <a href="../target/aarch64/ASRV.html#ASRV_32_dp_2src">32-bit</a>
  AMED_AARCH64_ENCODING_ASRV_64_dp_2src, //!< <a href="../target/aarch64/ASRV.html#ASRV_64_dp_2src">64-bit</a>
  AMED_AARCH64_ENCODING_AUTDA_64P_dp_1src, //!< <a href="../target/aarch64/AUTDA.html#AUTDA_64P_dp_1src">AUTDA</a>
  AMED_AARCH64_ENCODING_AUTDZA_64Z_dp_1src, //!< <a href="../target/aarch64/AUTDA.html#AUTDZA_64Z_dp_1src">AUTDZA</a>
  AMED_AARCH64_ENCODING_AUTDB_64P_dp_1src, //!< <a href="../target/aarch64/AUTDB.html#AUTDB_64P_dp_1src">AUTDB</a>
  AMED_AARCH64_ENCODING_AUTDZB_64Z_dp_1src, //!< <a href="../target/aarch64/AUTDB.html#AUTDZB_64Z_dp_1src">AUTDZB</a>
  AMED_AARCH64_ENCODING_AUTIA_64P_dp_1src, //!< <a href="../target/aarch64/AUTIA.html#AUTIA_64P_dp_1src">AUTIA</a>
  AMED_AARCH64_ENCODING_AUTIZA_64Z_dp_1src, //!< <a href="../target/aarch64/AUTIA.html#AUTIZA_64Z_dp_1src">AUTIZA</a>
  AMED_AARCH64_ENCODING_AUTIA1716_HI_hints, //!< <a href="../target/aarch64/AUTIA.html#AUTIA1716_HI_hints">AUTIA1716</a>
  AMED_AARCH64_ENCODING_AUTIASP_HI_hints, //!< <a href="../target/aarch64/AUTIA.html#AUTIASP_HI_hints">AUTIASP</a>
  AMED_AARCH64_ENCODING_AUTIAZ_HI_hints, //!< <a href="../target/aarch64/AUTIA.html#AUTIAZ_HI_hints">AUTIAZ</a>
  AMED_AARCH64_ENCODING_AUTIB_64P_dp_1src, //!< <a href="../target/aarch64/AUTIB.html#AUTIB_64P_dp_1src">AUTIB</a>
  AMED_AARCH64_ENCODING_AUTIZB_64Z_dp_1src, //!< <a href="../target/aarch64/AUTIB.html#AUTIZB_64Z_dp_1src">AUTIZB</a>
  AMED_AARCH64_ENCODING_AUTIB1716_HI_hints, //!< <a href="../target/aarch64/AUTIB.html#AUTIB1716_HI_hints">AUTIB1716</a>
  AMED_AARCH64_ENCODING_AUTIBSP_HI_hints, //!< <a href="../target/aarch64/AUTIB.html#AUTIBSP_HI_hints">AUTIBSP</a>
  AMED_AARCH64_ENCODING_AUTIBZ_HI_hints, //!< <a href="../target/aarch64/AUTIB.html#AUTIBZ_HI_hints">AUTIBZ</a>
  AMED_AARCH64_ENCODING_AXFLAG_M_pstate, //!< <a href="../target/aarch64/AXFLAG.html#AXFLAG_M_pstate">System</a>
  AMED_AARCH64_ENCODING_B_only_condbranch, //!< <a href="../target/aarch64/B_cond.html#B_only_condbranch">19-bit signed PC-relative branch offset</a>
  AMED_AARCH64_ENCODING_B_only_branch_imm, //!< <a href="../target/aarch64/B_uncond.html#B_only_branch_imm">26-bit signed PC-relative branch offset</a>
  AMED_AARCH64_ENCODING_BFM_32M_bitfield, //!< <a href="../target/aarch64/BFM.html#BFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_BFM_64M_bitfield, //!< <a href="../target/aarch64/BFM.html#BFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_BIC_32_log_shift, //!< <a href="../target/aarch64/BIC_log_shift.html#BIC_32_log_shift">32-bit</a>
  AMED_AARCH64_ENCODING_BIC_64_log_shift, //!< <a href="../target/aarch64/BIC_log_shift.html#BIC_64_log_shift">64-bit</a>
  AMED_AARCH64_ENCODING_BICS_32_log_shift, //!< <a href="../target/aarch64/BICS.html#BICS_32_log_shift">32-bit</a>
  AMED_AARCH64_ENCODING_BICS_64_log_shift, //!< <a href="../target/aarch64/BICS.html#BICS_64_log_shift">64-bit</a>
  AMED_AARCH64_ENCODING_BL_only_branch_imm, //!< <a href="../target/aarch64/BL.html#BL_only_branch_imm">26-bit signed PC-relative branch offset</a>
  AMED_AARCH64_ENCODING_BLR_64_branch_reg, //!< <a href="../target/aarch64/BLR.html#BLR_64_branch_reg">Integer</a>
  AMED_AARCH64_ENCODING_BLRAAZ_64_branch_reg, //!< <a href="../target/aarch64/BLRA.html#BLRAAZ_64_branch_reg">Key A, zero modifier</a>
  AMED_AARCH64_ENCODING_BLRAA_64P_branch_reg, //!< <a href="../target/aarch64/BLRA.html#BLRAA_64P_branch_reg">Key A, register modifier</a>
  AMED_AARCH64_ENCODING_BLRABZ_64_branch_reg, //!< <a href="../target/aarch64/BLRA.html#BLRABZ_64_branch_reg">Key B, zero modifier</a>
  AMED_AARCH64_ENCODING_BLRAB_64P_branch_reg, //!< <a href="../target/aarch64/BLRA.html#BLRAB_64P_branch_reg">Key B, register modifier</a>
  AMED_AARCH64_ENCODING_BR_64_branch_reg, //!< <a href="../target/aarch64/BR.html#BR_64_branch_reg">Integer</a>
  AMED_AARCH64_ENCODING_BRAAZ_64_branch_reg, //!< <a href="../target/aarch64/BRA.html#BRAAZ_64_branch_reg">Key A, zero modifier</a>
  AMED_AARCH64_ENCODING_BRAA_64P_branch_reg, //!< <a href="../target/aarch64/BRA.html#BRAA_64P_branch_reg">Key A, register modifier</a>
  AMED_AARCH64_ENCODING_BRABZ_64_branch_reg, //!< <a href="../target/aarch64/BRA.html#BRABZ_64_branch_reg">Key B, zero modifier</a>
  AMED_AARCH64_ENCODING_BRAB_64P_branch_reg, //!< <a href="../target/aarch64/BRA.html#BRAB_64P_branch_reg">Key B, register modifier</a>
  AMED_AARCH64_ENCODING_BRK_EX_exception, //!< <a href="../target/aarch64/BRK.html#BRK_EX_exception">System</a>
  AMED_AARCH64_ENCODING_BTI_HB_hints, //!< <a href="../target/aarch64/BTI.html#BTI_HB_hints">System</a>
  AMED_AARCH64_ENCODING_CAS_C32_ldstexcl, //!< <a href="../target/aarch64/CAS.html#CAS_C32_ldstexcl">32-bit CAS</a>
  AMED_AARCH64_ENCODING_CASA_C32_ldstexcl, //!< <a href="../target/aarch64/CAS.html#CASA_C32_ldstexcl">32-bit CASA</a>
  AMED_AARCH64_ENCODING_CASAL_C32_ldstexcl, //!< <a href="../target/aarch64/CAS.html#CASAL_C32_ldstexcl">32-bit CASAL</a>
  AMED_AARCH64_ENCODING_CASL_C32_ldstexcl, //!< <a href="../target/aarch64/CAS.html#CASL_C32_ldstexcl">32-bit CASL</a>
  AMED_AARCH64_ENCODING_CAS_C64_ldstexcl, //!< <a href="../target/aarch64/CAS.html#CAS_C64_ldstexcl">64-bit CAS</a>
  AMED_AARCH64_ENCODING_CASA_C64_ldstexcl, //!< <a href="../target/aarch64/CAS.html#CASA_C64_ldstexcl">64-bit CASA</a>
  AMED_AARCH64_ENCODING_CASAL_C64_ldstexcl, //!< <a href="../target/aarch64/CAS.html#CASAL_C64_ldstexcl">64-bit CASAL</a>
  AMED_AARCH64_ENCODING_CASL_C64_ldstexcl, //!< <a href="../target/aarch64/CAS.html#CASL_C64_ldstexcl">64-bit CASL</a>
  AMED_AARCH64_ENCODING_CASAB_C32_ldstexcl, //!< <a href="../target/aarch64/CASB.html#CASAB_C32_ldstexcl">CASAB</a>
  AMED_AARCH64_ENCODING_CASALB_C32_ldstexcl, //!< <a href="../target/aarch64/CASB.html#CASALB_C32_ldstexcl">CASALB</a>
  AMED_AARCH64_ENCODING_CASB_C32_ldstexcl, //!< <a href="../target/aarch64/CASB.html#CASB_C32_ldstexcl">CASB</a>
  AMED_AARCH64_ENCODING_CASLB_C32_ldstexcl, //!< <a href="../target/aarch64/CASB.html#CASLB_C32_ldstexcl">CASLB</a>
  AMED_AARCH64_ENCODING_CASAH_C32_ldstexcl, //!< <a href="../target/aarch64/CASH.html#CASAH_C32_ldstexcl">CASAH</a>
  AMED_AARCH64_ENCODING_CASALH_C32_ldstexcl, //!< <a href="../target/aarch64/CASH.html#CASALH_C32_ldstexcl">CASALH</a>
  AMED_AARCH64_ENCODING_CASH_C32_ldstexcl, //!< <a href="../target/aarch64/CASH.html#CASH_C32_ldstexcl">CASH</a>
  AMED_AARCH64_ENCODING_CASLH_C32_ldstexcl, //!< <a href="../target/aarch64/CASH.html#CASLH_C32_ldstexcl">CASLH</a>
  AMED_AARCH64_ENCODING_CASP_CP32_ldstexcl, //!< <a href="../target/aarch64/CASP.html#CASP_CP32_ldstexcl">32-bit CASP</a>
  AMED_AARCH64_ENCODING_CASPA_CP32_ldstexcl, //!< <a href="../target/aarch64/CASP.html#CASPA_CP32_ldstexcl">32-bit CASPA</a>
  AMED_AARCH64_ENCODING_CASPAL_CP32_ldstexcl, //!< <a href="../target/aarch64/CASP.html#CASPAL_CP32_ldstexcl">32-bit CASPAL</a>
  AMED_AARCH64_ENCODING_CASPL_CP32_ldstexcl, //!< <a href="../target/aarch64/CASP.html#CASPL_CP32_ldstexcl">32-bit CASPL</a>
  AMED_AARCH64_ENCODING_CASP_CP64_ldstexcl, //!< <a href="../target/aarch64/CASP.html#CASP_CP64_ldstexcl">64-bit CASP</a>
  AMED_AARCH64_ENCODING_CASPA_CP64_ldstexcl, //!< <a href="../target/aarch64/CASP.html#CASPA_CP64_ldstexcl">64-bit CASPA</a>
  AMED_AARCH64_ENCODING_CASPAL_CP64_ldstexcl, //!< <a href="../target/aarch64/CASP.html#CASPAL_CP64_ldstexcl">64-bit CASPAL</a>
  AMED_AARCH64_ENCODING_CASPL_CP64_ldstexcl, //!< <a href="../target/aarch64/CASP.html#CASPL_CP64_ldstexcl">64-bit CASPL</a>
  AMED_AARCH64_ENCODING_CBNZ_32_compbranch, //!< <a href="../target/aarch64/CBNZ.html#CBNZ_32_compbranch">32-bit</a>
  AMED_AARCH64_ENCODING_CBNZ_64_compbranch, //!< <a href="../target/aarch64/CBNZ.html#CBNZ_64_compbranch">64-bit</a>
  AMED_AARCH64_ENCODING_CBZ_32_compbranch, //!< <a href="../target/aarch64/CBZ.html#CBZ_32_compbranch">32-bit</a>
  AMED_AARCH64_ENCODING_CBZ_64_compbranch, //!< <a href="../target/aarch64/CBZ.html#CBZ_64_compbranch">64-bit</a>
  AMED_AARCH64_ENCODING_CCMN_32_condcmp_imm, //!< <a href="../target/aarch64/CCMN_imm.html#CCMN_32_condcmp_imm">32-bit</a>
  AMED_AARCH64_ENCODING_CCMN_64_condcmp_imm, //!< <a href="../target/aarch64/CCMN_imm.html#CCMN_64_condcmp_imm">64-bit</a>
  AMED_AARCH64_ENCODING_CCMN_32_condcmp_reg, //!< <a href="../target/aarch64/CCMN_reg.html#CCMN_32_condcmp_reg">32-bit</a>
  AMED_AARCH64_ENCODING_CCMN_64_condcmp_reg, //!< <a href="../target/aarch64/CCMN_reg.html#CCMN_64_condcmp_reg">64-bit</a>
  AMED_AARCH64_ENCODING_CCMP_32_condcmp_imm, //!< <a href="../target/aarch64/CCMP_imm.html#CCMP_32_condcmp_imm">32-bit</a>
  AMED_AARCH64_ENCODING_CCMP_64_condcmp_imm, //!< <a href="../target/aarch64/CCMP_imm.html#CCMP_64_condcmp_imm">64-bit</a>
  AMED_AARCH64_ENCODING_CCMP_32_condcmp_reg, //!< <a href="../target/aarch64/CCMP_reg.html#CCMP_32_condcmp_reg">32-bit</a>
  AMED_AARCH64_ENCODING_CCMP_64_condcmp_reg, //!< <a href="../target/aarch64/CCMP_reg.html#CCMP_64_condcmp_reg">64-bit</a>
  AMED_AARCH64_ENCODING_CFINV_M_pstate, //!< <a href="../target/aarch64/CFINV.html#CFINV_M_pstate">System</a>
  AMED_AARCH64_ENCODING_CLREX_BN_barriers, //!< <a href="../target/aarch64/CLREX.html#CLREX_BN_barriers">System</a>
  AMED_AARCH64_ENCODING_CLS_32_dp_1src, //!< <a href="../target/aarch64/CLS_int.html#CLS_32_dp_1src">32-bit</a>
  AMED_AARCH64_ENCODING_CLS_64_dp_1src, //!< <a href="../target/aarch64/CLS_int.html#CLS_64_dp_1src">64-bit</a>
  AMED_AARCH64_ENCODING_CLZ_32_dp_1src, //!< <a href="../target/aarch64/CLZ_int.html#CLZ_32_dp_1src">32-bit</a>
  AMED_AARCH64_ENCODING_CLZ_64_dp_1src, //!< <a href="../target/aarch64/CLZ_int.html#CLZ_64_dp_1src">64-bit</a>
  AMED_AARCH64_ENCODING_CRC32B_32C_dp_2src, //!< <a href="../target/aarch64/CRC32.html#CRC32B_32C_dp_2src">CRC32B</a>
  AMED_AARCH64_ENCODING_CRC32H_32C_dp_2src, //!< <a href="../target/aarch64/CRC32.html#CRC32H_32C_dp_2src">CRC32H</a>
  AMED_AARCH64_ENCODING_CRC32W_32C_dp_2src, //!< <a href="../target/aarch64/CRC32.html#CRC32W_32C_dp_2src">CRC32W</a>
  AMED_AARCH64_ENCODING_CRC32X_64C_dp_2src, //!< <a href="../target/aarch64/CRC32.html#CRC32X_64C_dp_2src">CRC32X</a>
  AMED_AARCH64_ENCODING_CRC32CB_32C_dp_2src, //!< <a href="../target/aarch64/CRC32C.html#CRC32CB_32C_dp_2src">CRC32CB</a>
  AMED_AARCH64_ENCODING_CRC32CH_32C_dp_2src, //!< <a href="../target/aarch64/CRC32C.html#CRC32CH_32C_dp_2src">CRC32CH</a>
  AMED_AARCH64_ENCODING_CRC32CW_32C_dp_2src, //!< <a href="../target/aarch64/CRC32C.html#CRC32CW_32C_dp_2src">CRC32CW</a>
  AMED_AARCH64_ENCODING_CRC32CX_64C_dp_2src, //!< <a href="../target/aarch64/CRC32C.html#CRC32CX_64C_dp_2src">CRC32CX</a>
  AMED_AARCH64_ENCODING_CSDB_HI_hints, //!< <a href="../target/aarch64/CSDB.html#CSDB_HI_hints">System</a>
  AMED_AARCH64_ENCODING_CSEL_32_condsel, //!< <a href="../target/aarch64/CSEL.html#CSEL_32_condsel">32-bit</a>
  AMED_AARCH64_ENCODING_CSEL_64_condsel, //!< <a href="../target/aarch64/CSEL.html#CSEL_64_condsel">64-bit</a>
  AMED_AARCH64_ENCODING_CSINC_32_condsel, //!< <a href="../target/aarch64/CSINC.html#CSINC_32_condsel">32-bit</a>
  AMED_AARCH64_ENCODING_CSINC_64_condsel, //!< <a href="../target/aarch64/CSINC.html#CSINC_64_condsel">64-bit</a>
  AMED_AARCH64_ENCODING_CSINV_32_condsel, //!< <a href="../target/aarch64/CSINV.html#CSINV_32_condsel">32-bit</a>
  AMED_AARCH64_ENCODING_CSINV_64_condsel, //!< <a href="../target/aarch64/CSINV.html#CSINV_64_condsel">64-bit</a>
  AMED_AARCH64_ENCODING_CSNEG_32_condsel, //!< <a href="../target/aarch64/CSNEG.html#CSNEG_32_condsel">32-bit</a>
  AMED_AARCH64_ENCODING_CSNEG_64_condsel, //!< <a href="../target/aarch64/CSNEG.html#CSNEG_64_condsel">64-bit</a>
  AMED_AARCH64_ENCODING_DCPS1_DC_exception, //!< <a href="../target/aarch64/DCPS1.html#DCPS1_DC_exception">System</a>
  AMED_AARCH64_ENCODING_DCPS2_DC_exception, //!< <a href="../target/aarch64/DCPS2.html#DCPS2_DC_exception">System</a>
  AMED_AARCH64_ENCODING_DCPS3_DC_exception, //!< <a href="../target/aarch64/DCPS3.html#DCPS3_DC_exception">System</a>
  AMED_AARCH64_ENCODING_DGH_HI_hints, //!< <a href="../target/aarch64/DGH.html#DGH_HI_hints">System</a>
  AMED_AARCH64_ENCODING_DMB_BO_barriers, //!< <a href="../target/aarch64/DMB.html#DMB_BO_barriers">System</a>
  AMED_AARCH64_ENCODING_DRPS_64E_branch_reg, //!< <a href="../target/aarch64/DRPS.html#DRPS_64E_branch_reg">System</a>
  AMED_AARCH64_ENCODING_DSB_BO_barriers, //!< <a href="../target/aarch64/DSB.html#DSB_BO_barriers">System</a>
  AMED_AARCH64_ENCODING_EON_32_log_shift, //!< <a href="../target/aarch64/EON.html#EON_32_log_shift">32-bit</a>
  AMED_AARCH64_ENCODING_EON_64_log_shift, //!< <a href="../target/aarch64/EON.html#EON_64_log_shift">64-bit</a>
  AMED_AARCH64_ENCODING_EOR_32_log_imm, //!< <a href="../target/aarch64/EOR_log_imm.html#EOR_32_log_imm">32-bit</a>
  AMED_AARCH64_ENCODING_EOR_64_log_imm, //!< <a href="../target/aarch64/EOR_log_imm.html#EOR_64_log_imm">64-bit</a>
  AMED_AARCH64_ENCODING_EOR_32_log_shift, //!< <a href="../target/aarch64/EOR_log_shift.html#EOR_32_log_shift">32-bit</a>
  AMED_AARCH64_ENCODING_EOR_64_log_shift, //!< <a href="../target/aarch64/EOR_log_shift.html#EOR_64_log_shift">64-bit</a>
  AMED_AARCH64_ENCODING_ERET_64E_branch_reg, //!< <a href="../target/aarch64/ERET.html#ERET_64E_branch_reg">System</a>
  AMED_AARCH64_ENCODING_ERETAA_64E_branch_reg, //!< <a href="../target/aarch64/ERETA.html#ERETAA_64E_branch_reg">ERETAA</a>
  AMED_AARCH64_ENCODING_ERETAB_64E_branch_reg, //!< <a href="../target/aarch64/ERETA.html#ERETAB_64E_branch_reg">ERETAB</a>
  AMED_AARCH64_ENCODING_ESB_HI_hints, //!< <a href="../target/aarch64/ESB.html#ESB_HI_hints">System</a>
  AMED_AARCH64_ENCODING_EXTR_32_extract, //!< <a href="../target/aarch64/EXTR.html#EXTR_32_extract">32-bit</a>
  AMED_AARCH64_ENCODING_EXTR_64_extract, //!< <a href="../target/aarch64/EXTR.html#EXTR_64_extract">64-bit</a>
  AMED_AARCH64_ENCODING_GMI_64G_dp_2src, //!< <a href="../target/aarch64/GMI.html#GMI_64G_dp_2src">Integer</a>
  AMED_AARCH64_ENCODING_HINT_HM_hints, //!< <a href="../target/aarch64/HINT.html#HINT_HM_hints">System</a>
  AMED_AARCH64_ENCODING_HLT_EX_exception, //!< <a href="../target/aarch64/HLT.html#HLT_EX_exception">System</a>
  AMED_AARCH64_ENCODING_HVC_EX_exception, //!< <a href="../target/aarch64/HVC.html#HVC_EX_exception">System</a>
  AMED_AARCH64_ENCODING_IRG_64I_dp_2src, //!< <a href="../target/aarch64/IRG.html#IRG_64I_dp_2src">Integer</a>
  AMED_AARCH64_ENCODING_ISB_BI_barriers, //!< <a href="../target/aarch64/ISB.html#ISB_BI_barriers">System</a>
  AMED_AARCH64_ENCODING_LDADD_32_memop, //!< <a href="../target/aarch64/LDADD.html#LDADD_32_memop">32-bit LDADD</a>
  AMED_AARCH64_ENCODING_LDADDA_32_memop, //!< <a href="../target/aarch64/LDADD.html#LDADDA_32_memop">32-bit LDADDA</a>
  AMED_AARCH64_ENCODING_LDADDAL_32_memop, //!< <a href="../target/aarch64/LDADD.html#LDADDAL_32_memop">32-bit LDADDAL</a>
  AMED_AARCH64_ENCODING_LDADDL_32_memop, //!< <a href="../target/aarch64/LDADD.html#LDADDL_32_memop">32-bit LDADDL</a>
  AMED_AARCH64_ENCODING_LDADD_64_memop, //!< <a href="../target/aarch64/LDADD.html#LDADD_64_memop">64-bit LDADD</a>
  AMED_AARCH64_ENCODING_LDADDA_64_memop, //!< <a href="../target/aarch64/LDADD.html#LDADDA_64_memop">64-bit LDADDA</a>
  AMED_AARCH64_ENCODING_LDADDAL_64_memop, //!< <a href="../target/aarch64/LDADD.html#LDADDAL_64_memop">64-bit LDADDAL</a>
  AMED_AARCH64_ENCODING_LDADDL_64_memop, //!< <a href="../target/aarch64/LDADD.html#LDADDL_64_memop">64-bit LDADDL</a>
  AMED_AARCH64_ENCODING_LDADDAB_32_memop, //!< <a href="../target/aarch64/LDADDB.html#LDADDAB_32_memop">LDADDAB</a>
  AMED_AARCH64_ENCODING_LDADDALB_32_memop, //!< <a href="../target/aarch64/LDADDB.html#LDADDALB_32_memop">LDADDALB</a>
  AMED_AARCH64_ENCODING_LDADDB_32_memop, //!< <a href="../target/aarch64/LDADDB.html#LDADDB_32_memop">LDADDB</a>
  AMED_AARCH64_ENCODING_LDADDLB_32_memop, //!< <a href="../target/aarch64/LDADDB.html#LDADDLB_32_memop">LDADDLB</a>
  AMED_AARCH64_ENCODING_LDADDAH_32_memop, //!< <a href="../target/aarch64/LDADDH.html#LDADDAH_32_memop">LDADDAH</a>
  AMED_AARCH64_ENCODING_LDADDALH_32_memop, //!< <a href="../target/aarch64/LDADDH.html#LDADDALH_32_memop">LDADDALH</a>
  AMED_AARCH64_ENCODING_LDADDH_32_memop, //!< <a href="../target/aarch64/LDADDH.html#LDADDH_32_memop">LDADDH</a>
  AMED_AARCH64_ENCODING_LDADDLH_32_memop, //!< <a href="../target/aarch64/LDADDH.html#LDADDLH_32_memop">LDADDLH</a>
  AMED_AARCH64_ENCODING_LDAPR_32L_memop, //!< <a href="../target/aarch64/LDAPR.html#LDAPR_32L_memop">32-bit</a>
  AMED_AARCH64_ENCODING_LDAPR_64L_memop, //!< <a href="../target/aarch64/LDAPR.html#LDAPR_64L_memop">64-bit</a>
  AMED_AARCH64_ENCODING_LDAPRB_32L_memop, //!< <a href="../target/aarch64/LDAPRB.html#LDAPRB_32L_memop">Integer</a>
  AMED_AARCH64_ENCODING_LDAPRH_32L_memop, //!< <a href="../target/aarch64/LDAPRH.html#LDAPRH_32L_memop">Integer</a>
  AMED_AARCH64_ENCODING_LDAPUR_32_ldapstl_unscaled, //!< <a href="../target/aarch64/LDAPUR_gen.html#LDAPUR_32_ldapstl_unscaled">32-bit</a>
  AMED_AARCH64_ENCODING_LDAPUR_64_ldapstl_unscaled, //!< <a href="../target/aarch64/LDAPUR_gen.html#LDAPUR_64_ldapstl_unscaled">64-bit</a>
  AMED_AARCH64_ENCODING_LDAPURB_32_ldapstl_unscaled, //!< <a href="../target/aarch64/LDAPURB.html#LDAPURB_32_ldapstl_unscaled">Unscaled offset</a>
  AMED_AARCH64_ENCODING_LDAPURH_32_ldapstl_unscaled, //!< <a href="../target/aarch64/LDAPURH.html#LDAPURH_32_ldapstl_unscaled">Unscaled offset</a>
  AMED_AARCH64_ENCODING_LDAPURSB_32_ldapstl_unscaled, //!< <a href="../target/aarch64/LDAPURSB.html#LDAPURSB_32_ldapstl_unscaled">32-bit</a>
  AMED_AARCH64_ENCODING_LDAPURSB_64_ldapstl_unscaled, //!< <a href="../target/aarch64/LDAPURSB.html#LDAPURSB_64_ldapstl_unscaled">64-bit</a>
  AMED_AARCH64_ENCODING_LDAPURSH_32_ldapstl_unscaled, //!< <a href="../target/aarch64/LDAPURSH.html#LDAPURSH_32_ldapstl_unscaled">32-bit</a>
  AMED_AARCH64_ENCODING_LDAPURSH_64_ldapstl_unscaled, //!< <a href="../target/aarch64/LDAPURSH.html#LDAPURSH_64_ldapstl_unscaled">64-bit</a>
  AMED_AARCH64_ENCODING_LDAPURSW_64_ldapstl_unscaled, //!< <a href="../target/aarch64/LDAPURSW.html#LDAPURSW_64_ldapstl_unscaled">Unscaled offset</a>
  AMED_AARCH64_ENCODING_LDAR_LR32_ldstexcl, //!< <a href="../target/aarch64/LDAR.html#LDAR_LR32_ldstexcl">32-bit</a>
  AMED_AARCH64_ENCODING_LDAR_LR64_ldstexcl, //!< <a href="../target/aarch64/LDAR.html#LDAR_LR64_ldstexcl">64-bit</a>
  AMED_AARCH64_ENCODING_LDARB_LR32_ldstexcl, //!< <a href="../target/aarch64/LDARB.html#LDARB_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_LDARH_LR32_ldstexcl, //!< <a href="../target/aarch64/LDARH.html#LDARH_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_LDAXP_LP32_ldstexcl, //!< <a href="../target/aarch64/LDAXP.html#LDAXP_LP32_ldstexcl">32-bit</a>
  AMED_AARCH64_ENCODING_LDAXP_LP64_ldstexcl, //!< <a href="../target/aarch64/LDAXP.html#LDAXP_LP64_ldstexcl">64-bit</a>
  AMED_AARCH64_ENCODING_LDAXR_LR32_ldstexcl, //!< <a href="../target/aarch64/LDAXR.html#LDAXR_LR32_ldstexcl">32-bit</a>
  AMED_AARCH64_ENCODING_LDAXR_LR64_ldstexcl, //!< <a href="../target/aarch64/LDAXR.html#LDAXR_LR64_ldstexcl">64-bit</a>
  AMED_AARCH64_ENCODING_LDAXRB_LR32_ldstexcl, //!< <a href="../target/aarch64/LDAXRB.html#LDAXRB_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_LDAXRH_LR32_ldstexcl, //!< <a href="../target/aarch64/LDAXRH.html#LDAXRH_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_LDCLR_32_memop, //!< <a href="../target/aarch64/LDCLR.html#LDCLR_32_memop">32-bit LDCLR</a>
  AMED_AARCH64_ENCODING_LDCLRA_32_memop, //!< <a href="../target/aarch64/LDCLR.html#LDCLRA_32_memop">32-bit LDCLRA</a>
  AMED_AARCH64_ENCODING_LDCLRAL_32_memop, //!< <a href="../target/aarch64/LDCLR.html#LDCLRAL_32_memop">32-bit LDCLRAL</a>
  AMED_AARCH64_ENCODING_LDCLRL_32_memop, //!< <a href="../target/aarch64/LDCLR.html#LDCLRL_32_memop">32-bit LDCLRL</a>
  AMED_AARCH64_ENCODING_LDCLR_64_memop, //!< <a href="../target/aarch64/LDCLR.html#LDCLR_64_memop">64-bit LDCLR</a>
  AMED_AARCH64_ENCODING_LDCLRA_64_memop, //!< <a href="../target/aarch64/LDCLR.html#LDCLRA_64_memop">64-bit LDCLRA</a>
  AMED_AARCH64_ENCODING_LDCLRAL_64_memop, //!< <a href="../target/aarch64/LDCLR.html#LDCLRAL_64_memop">64-bit LDCLRAL</a>
  AMED_AARCH64_ENCODING_LDCLRL_64_memop, //!< <a href="../target/aarch64/LDCLR.html#LDCLRL_64_memop">64-bit LDCLRL</a>
  AMED_AARCH64_ENCODING_LDCLRAB_32_memop, //!< <a href="../target/aarch64/LDCLRB.html#LDCLRAB_32_memop">LDCLRAB</a>
  AMED_AARCH64_ENCODING_LDCLRALB_32_memop, //!< <a href="../target/aarch64/LDCLRB.html#LDCLRALB_32_memop">LDCLRALB</a>
  AMED_AARCH64_ENCODING_LDCLRB_32_memop, //!< <a href="../target/aarch64/LDCLRB.html#LDCLRB_32_memop">LDCLRB</a>
  AMED_AARCH64_ENCODING_LDCLRLB_32_memop, //!< <a href="../target/aarch64/LDCLRB.html#LDCLRLB_32_memop">LDCLRLB</a>
  AMED_AARCH64_ENCODING_LDCLRAH_32_memop, //!< <a href="../target/aarch64/LDCLRH.html#LDCLRAH_32_memop">LDCLRAH</a>
  AMED_AARCH64_ENCODING_LDCLRALH_32_memop, //!< <a href="../target/aarch64/LDCLRH.html#LDCLRALH_32_memop">LDCLRALH</a>
  AMED_AARCH64_ENCODING_LDCLRH_32_memop, //!< <a href="../target/aarch64/LDCLRH.html#LDCLRH_32_memop">LDCLRH</a>
  AMED_AARCH64_ENCODING_LDCLRLH_32_memop, //!< <a href="../target/aarch64/LDCLRH.html#LDCLRLH_32_memop">LDCLRLH</a>
  AMED_AARCH64_ENCODING_LDEOR_32_memop, //!< <a href="../target/aarch64/LDEOR.html#LDEOR_32_memop">32-bit LDEOR</a>
  AMED_AARCH64_ENCODING_LDEORA_32_memop, //!< <a href="../target/aarch64/LDEOR.html#LDEORA_32_memop">32-bit LDEORA</a>
  AMED_AARCH64_ENCODING_LDEORAL_32_memop, //!< <a href="../target/aarch64/LDEOR.html#LDEORAL_32_memop">32-bit LDEORAL</a>
  AMED_AARCH64_ENCODING_LDEORL_32_memop, //!< <a href="../target/aarch64/LDEOR.html#LDEORL_32_memop">32-bit LDEORL</a>
  AMED_AARCH64_ENCODING_LDEOR_64_memop, //!< <a href="../target/aarch64/LDEOR.html#LDEOR_64_memop">64-bit LDEOR</a>
  AMED_AARCH64_ENCODING_LDEORA_64_memop, //!< <a href="../target/aarch64/LDEOR.html#LDEORA_64_memop">64-bit LDEORA</a>
  AMED_AARCH64_ENCODING_LDEORAL_64_memop, //!< <a href="../target/aarch64/LDEOR.html#LDEORAL_64_memop">64-bit LDEORAL</a>
  AMED_AARCH64_ENCODING_LDEORL_64_memop, //!< <a href="../target/aarch64/LDEOR.html#LDEORL_64_memop">64-bit LDEORL</a>
  AMED_AARCH64_ENCODING_LDEORAB_32_memop, //!< <a href="../target/aarch64/LDEORB.html#LDEORAB_32_memop">LDEORAB</a>
  AMED_AARCH64_ENCODING_LDEORALB_32_memop, //!< <a href="../target/aarch64/LDEORB.html#LDEORALB_32_memop">LDEORALB</a>
  AMED_AARCH64_ENCODING_LDEORB_32_memop, //!< <a href="../target/aarch64/LDEORB.html#LDEORB_32_memop">LDEORB</a>
  AMED_AARCH64_ENCODING_LDEORLB_32_memop, //!< <a href="../target/aarch64/LDEORB.html#LDEORLB_32_memop">LDEORLB</a>
  AMED_AARCH64_ENCODING_LDEORAH_32_memop, //!< <a href="../target/aarch64/LDEORH.html#LDEORAH_32_memop">LDEORAH</a>
  AMED_AARCH64_ENCODING_LDEORALH_32_memop, //!< <a href="../target/aarch64/LDEORH.html#LDEORALH_32_memop">LDEORALH</a>
  AMED_AARCH64_ENCODING_LDEORH_32_memop, //!< <a href="../target/aarch64/LDEORH.html#LDEORH_32_memop">LDEORH</a>
  AMED_AARCH64_ENCODING_LDEORLH_32_memop, //!< <a href="../target/aarch64/LDEORH.html#LDEORLH_32_memop">LDEORLH</a>
  AMED_AARCH64_ENCODING_LDG_64Loffset_ldsttags, //!< <a href="../target/aarch64/LDG.html#LDG_64Loffset_ldsttags">Integer</a>
  AMED_AARCH64_ENCODING_LDGM_64bulk_ldsttags, //!< <a href="../target/aarch64/LDGM.html#LDGM_64bulk_ldsttags">Integer</a>
  AMED_AARCH64_ENCODING_LDLAR_LR32_ldstexcl, //!< <a href="../target/aarch64/LDLAR.html#LDLAR_LR32_ldstexcl">32-bit</a>
  AMED_AARCH64_ENCODING_LDLAR_LR64_ldstexcl, //!< <a href="../target/aarch64/LDLAR.html#LDLAR_LR64_ldstexcl">64-bit</a>
  AMED_AARCH64_ENCODING_LDLARB_LR32_ldstexcl, //!< <a href="../target/aarch64/LDLARB.html#LDLARB_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_LDLARH_LR32_ldstexcl, //!< <a href="../target/aarch64/LDLARH.html#LDLARH_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_LDNP_32_ldstnapair_offs, //!< <a href="../target/aarch64/LDNP_gen.html#LDNP_32_ldstnapair_offs">32-bit</a>
  AMED_AARCH64_ENCODING_LDNP_64_ldstnapair_offs, //!< <a href="../target/aarch64/LDNP_gen.html#LDNP_64_ldstnapair_offs">64-bit</a>
  AMED_AARCH64_ENCODING_LDP_32_ldstpair_post, //!< <a href="../target/aarch64/LDP_gen.html#LDP_32_ldstpair_post">32-bit</a>
  AMED_AARCH64_ENCODING_LDP_64_ldstpair_post, //!< <a href="../target/aarch64/LDP_gen.html#LDP_64_ldstpair_post">64-bit</a>
  AMED_AARCH64_ENCODING_LDP_32_ldstpair_pre, //!< <a href="../target/aarch64/LDP_gen.html#LDP_32_ldstpair_pre">32-bit</a>
  AMED_AARCH64_ENCODING_LDP_64_ldstpair_pre, //!< <a href="../target/aarch64/LDP_gen.html#LDP_64_ldstpair_pre">64-bit</a>
  AMED_AARCH64_ENCODING_LDP_32_ldstpair_off, //!< <a href="../target/aarch64/LDP_gen.html#LDP_32_ldstpair_off">32-bit</a>
  AMED_AARCH64_ENCODING_LDP_64_ldstpair_off, //!< <a href="../target/aarch64/LDP_gen.html#LDP_64_ldstpair_off">64-bit</a>
  AMED_AARCH64_ENCODING_LDPSW_64_ldstpair_post, //!< <a href="../target/aarch64/LDPSW.html#LDPSW_64_ldstpair_post">Post-index</a>
  AMED_AARCH64_ENCODING_LDPSW_64_ldstpair_pre, //!< <a href="../target/aarch64/LDPSW.html#LDPSW_64_ldstpair_pre">Pre-index</a>
  AMED_AARCH64_ENCODING_LDPSW_64_ldstpair_off, //!< <a href="../target/aarch64/LDPSW.html#LDPSW_64_ldstpair_off">Signed offset</a>
  AMED_AARCH64_ENCODING_LDR_32_ldst_immpost, //!< <a href="../target/aarch64/LDR_imm_gen.html#LDR_32_ldst_immpost">32-bit</a>
  AMED_AARCH64_ENCODING_LDR_64_ldst_immpost, //!< <a href="../target/aarch64/LDR_imm_gen.html#LDR_64_ldst_immpost">64-bit</a>
  AMED_AARCH64_ENCODING_LDR_32_ldst_immpre, //!< <a href="../target/aarch64/LDR_imm_gen.html#LDR_32_ldst_immpre">32-bit</a>
  AMED_AARCH64_ENCODING_LDR_64_ldst_immpre, //!< <a href="../target/aarch64/LDR_imm_gen.html#LDR_64_ldst_immpre">64-bit</a>
  AMED_AARCH64_ENCODING_LDR_32_ldst_pos, //!< <a href="../target/aarch64/LDR_imm_gen.html#LDR_32_ldst_pos">32-bit</a>
  AMED_AARCH64_ENCODING_LDR_64_ldst_pos, //!< <a href="../target/aarch64/LDR_imm_gen.html#LDR_64_ldst_pos">64-bit</a>
  AMED_AARCH64_ENCODING_LDR_32_loadlit, //!< <a href="../target/aarch64/LDR_lit_gen.html#LDR_32_loadlit">32-bit</a>
  AMED_AARCH64_ENCODING_LDR_64_loadlit, //!< <a href="../target/aarch64/LDR_lit_gen.html#LDR_64_loadlit">64-bit</a>
  AMED_AARCH64_ENCODING_LDR_32_ldst_regoff, //!< <a href="../target/aarch64/LDR_reg_gen.html#LDR_32_ldst_regoff">32-bit</a>
  AMED_AARCH64_ENCODING_LDR_64_ldst_regoff, //!< <a href="../target/aarch64/LDR_reg_gen.html#LDR_64_ldst_regoff">64-bit</a>
  AMED_AARCH64_ENCODING_LDRAA_64_ldst_pac, //!< <a href="../target/aarch64/LDRA.html#LDRAA_64_ldst_pac">Key A, offset</a>
  AMED_AARCH64_ENCODING_LDRAA_64W_ldst_pac, //!< <a href="../target/aarch64/LDRA.html#LDRAA_64W_ldst_pac">Key A, pre-indexed</a>
  AMED_AARCH64_ENCODING_LDRAB_64_ldst_pac, //!< <a href="../target/aarch64/LDRA.html#LDRAB_64_ldst_pac">Key B, offset</a>
  AMED_AARCH64_ENCODING_LDRAB_64W_ldst_pac, //!< <a href="../target/aarch64/LDRA.html#LDRAB_64W_ldst_pac">Key B, pre-indexed</a>
  AMED_AARCH64_ENCODING_LDRB_32_ldst_immpost, //!< <a href="../target/aarch64/LDRB_imm.html#LDRB_32_ldst_immpost">Post-index</a>
  AMED_AARCH64_ENCODING_LDRB_32_ldst_immpre, //!< <a href="../target/aarch64/LDRB_imm.html#LDRB_32_ldst_immpre">Pre-index</a>
  AMED_AARCH64_ENCODING_LDRB_32_ldst_pos, //!< <a href="../target/aarch64/LDRB_imm.html#LDRB_32_ldst_pos">Unsigned offset</a>
  AMED_AARCH64_ENCODING_LDRB_32B_ldst_regoff, //!< <a href="../target/aarch64/LDRB_reg.html#LDRB_32B_ldst_regoff">Extended register</a>
  AMED_AARCH64_ENCODING_LDRB_32BL_ldst_regoff, //!< <a href="../target/aarch64/LDRB_reg.html#LDRB_32BL_ldst_regoff">Shifted register</a>
  AMED_AARCH64_ENCODING_LDRH_32_ldst_immpost, //!< <a href="../target/aarch64/LDRH_imm.html#LDRH_32_ldst_immpost">Post-index</a>
  AMED_AARCH64_ENCODING_LDRH_32_ldst_immpre, //!< <a href="../target/aarch64/LDRH_imm.html#LDRH_32_ldst_immpre">Pre-index</a>
  AMED_AARCH64_ENCODING_LDRH_32_ldst_pos, //!< <a href="../target/aarch64/LDRH_imm.html#LDRH_32_ldst_pos">Unsigned offset</a>
  AMED_AARCH64_ENCODING_LDRH_32_ldst_regoff, //!< <a href="../target/aarch64/LDRH_reg.html#LDRH_32_ldst_regoff">32-bit</a>
  AMED_AARCH64_ENCODING_LDRSB_32_ldst_immpost, //!< <a href="../target/aarch64/LDRSB_imm.html#LDRSB_32_ldst_immpost">32-bit</a>
  AMED_AARCH64_ENCODING_LDRSB_64_ldst_immpost, //!< <a href="../target/aarch64/LDRSB_imm.html#LDRSB_64_ldst_immpost">64-bit</a>
  AMED_AARCH64_ENCODING_LDRSB_32_ldst_immpre, //!< <a href="../target/aarch64/LDRSB_imm.html#LDRSB_32_ldst_immpre">32-bit</a>
  AMED_AARCH64_ENCODING_LDRSB_64_ldst_immpre, //!< <a href="../target/aarch64/LDRSB_imm.html#LDRSB_64_ldst_immpre">64-bit</a>
  AMED_AARCH64_ENCODING_LDRSB_32_ldst_pos, //!< <a href="../target/aarch64/LDRSB_imm.html#LDRSB_32_ldst_pos">32-bit</a>
  AMED_AARCH64_ENCODING_LDRSB_64_ldst_pos, //!< <a href="../target/aarch64/LDRSB_imm.html#LDRSB_64_ldst_pos">64-bit</a>
  AMED_AARCH64_ENCODING_LDRSB_32B_ldst_regoff, //!< <a href="../target/aarch64/LDRSB_reg.html#LDRSB_32B_ldst_regoff">32-bit with extended register offset</a>
  AMED_AARCH64_ENCODING_LDRSB_32BL_ldst_regoff, //!< <a href="../target/aarch64/LDRSB_reg.html#LDRSB_32BL_ldst_regoff">32-bit with shifted register offset</a>
  AMED_AARCH64_ENCODING_LDRSB_64B_ldst_regoff, //!< <a href="../target/aarch64/LDRSB_reg.html#LDRSB_64B_ldst_regoff">64-bit with extended register offset</a>
  AMED_AARCH64_ENCODING_LDRSB_64BL_ldst_regoff, //!< <a href="../target/aarch64/LDRSB_reg.html#LDRSB_64BL_ldst_regoff">64-bit with shifted register offset</a>
  AMED_AARCH64_ENCODING_LDRSH_32_ldst_immpost, //!< <a href="../target/aarch64/LDRSH_imm.html#LDRSH_32_ldst_immpost">32-bit</a>
  AMED_AARCH64_ENCODING_LDRSH_64_ldst_immpost, //!< <a href="../target/aarch64/LDRSH_imm.html#LDRSH_64_ldst_immpost">64-bit</a>
  AMED_AARCH64_ENCODING_LDRSH_32_ldst_immpre, //!< <a href="../target/aarch64/LDRSH_imm.html#LDRSH_32_ldst_immpre">32-bit</a>
  AMED_AARCH64_ENCODING_LDRSH_64_ldst_immpre, //!< <a href="../target/aarch64/LDRSH_imm.html#LDRSH_64_ldst_immpre">64-bit</a>
  AMED_AARCH64_ENCODING_LDRSH_32_ldst_pos, //!< <a href="../target/aarch64/LDRSH_imm.html#LDRSH_32_ldst_pos">32-bit</a>
  AMED_AARCH64_ENCODING_LDRSH_64_ldst_pos, //!< <a href="../target/aarch64/LDRSH_imm.html#LDRSH_64_ldst_pos">64-bit</a>
  AMED_AARCH64_ENCODING_LDRSH_32_ldst_regoff, //!< <a href="../target/aarch64/LDRSH_reg.html#LDRSH_32_ldst_regoff">32-bit</a>
  AMED_AARCH64_ENCODING_LDRSH_64_ldst_regoff, //!< <a href="../target/aarch64/LDRSH_reg.html#LDRSH_64_ldst_regoff">64-bit</a>
  AMED_AARCH64_ENCODING_LDRSW_64_ldst_immpost, //!< <a href="../target/aarch64/LDRSW_imm.html#LDRSW_64_ldst_immpost">Post-index</a>
  AMED_AARCH64_ENCODING_LDRSW_64_ldst_immpre, //!< <a href="../target/aarch64/LDRSW_imm.html#LDRSW_64_ldst_immpre">Pre-index</a>
  AMED_AARCH64_ENCODING_LDRSW_64_ldst_pos, //!< <a href="../target/aarch64/LDRSW_imm.html#LDRSW_64_ldst_pos">Unsigned offset</a>
  AMED_AARCH64_ENCODING_LDRSW_64_loadlit, //!< <a href="../target/aarch64/LDRSW_lit.html#LDRSW_64_loadlit">Literal</a>
  AMED_AARCH64_ENCODING_LDRSW_64_ldst_regoff, //!< <a href="../target/aarch64/LDRSW_reg.html#LDRSW_64_ldst_regoff">64-bit</a>
  AMED_AARCH64_ENCODING_LDSET_32_memop, //!< <a href="../target/aarch64/LDSET.html#LDSET_32_memop">32-bit LDSET</a>
  AMED_AARCH64_ENCODING_LDSETA_32_memop, //!< <a href="../target/aarch64/LDSET.html#LDSETA_32_memop">32-bit LDSETA</a>
  AMED_AARCH64_ENCODING_LDSETAL_32_memop, //!< <a href="../target/aarch64/LDSET.html#LDSETAL_32_memop">32-bit LDSETAL</a>
  AMED_AARCH64_ENCODING_LDSETL_32_memop, //!< <a href="../target/aarch64/LDSET.html#LDSETL_32_memop">32-bit LDSETL</a>
  AMED_AARCH64_ENCODING_LDSET_64_memop, //!< <a href="../target/aarch64/LDSET.html#LDSET_64_memop">64-bit LDSET</a>
  AMED_AARCH64_ENCODING_LDSETA_64_memop, //!< <a href="../target/aarch64/LDSET.html#LDSETA_64_memop">64-bit LDSETA</a>
  AMED_AARCH64_ENCODING_LDSETAL_64_memop, //!< <a href="../target/aarch64/LDSET.html#LDSETAL_64_memop">64-bit LDSETAL</a>
  AMED_AARCH64_ENCODING_LDSETL_64_memop, //!< <a href="../target/aarch64/LDSET.html#LDSETL_64_memop">64-bit LDSETL</a>
  AMED_AARCH64_ENCODING_LDSETAB_32_memop, //!< <a href="../target/aarch64/LDSETB.html#LDSETAB_32_memop">LDSETAB</a>
  AMED_AARCH64_ENCODING_LDSETALB_32_memop, //!< <a href="../target/aarch64/LDSETB.html#LDSETALB_32_memop">LDSETALB</a>
  AMED_AARCH64_ENCODING_LDSETB_32_memop, //!< <a href="../target/aarch64/LDSETB.html#LDSETB_32_memop">LDSETB</a>
  AMED_AARCH64_ENCODING_LDSETLB_32_memop, //!< <a href="../target/aarch64/LDSETB.html#LDSETLB_32_memop">LDSETLB</a>
  AMED_AARCH64_ENCODING_LDSETAH_32_memop, //!< <a href="../target/aarch64/LDSETH.html#LDSETAH_32_memop">LDSETAH</a>
  AMED_AARCH64_ENCODING_LDSETALH_32_memop, //!< <a href="../target/aarch64/LDSETH.html#LDSETALH_32_memop">LDSETALH</a>
  AMED_AARCH64_ENCODING_LDSETH_32_memop, //!< <a href="../target/aarch64/LDSETH.html#LDSETH_32_memop">LDSETH</a>
  AMED_AARCH64_ENCODING_LDSETLH_32_memop, //!< <a href="../target/aarch64/LDSETH.html#LDSETLH_32_memop">LDSETLH</a>
  AMED_AARCH64_ENCODING_LDSMAX_32_memop, //!< <a href="../target/aarch64/LDSMAX.html#LDSMAX_32_memop">32-bit LDSMAX</a>
  AMED_AARCH64_ENCODING_LDSMAXA_32_memop, //!< <a href="../target/aarch64/LDSMAX.html#LDSMAXA_32_memop">32-bit LDSMAXA</a>
  AMED_AARCH64_ENCODING_LDSMAXAL_32_memop, //!< <a href="../target/aarch64/LDSMAX.html#LDSMAXAL_32_memop">32-bit LDSMAXAL</a>
  AMED_AARCH64_ENCODING_LDSMAXL_32_memop, //!< <a href="../target/aarch64/LDSMAX.html#LDSMAXL_32_memop">32-bit LDSMAXL</a>
  AMED_AARCH64_ENCODING_LDSMAX_64_memop, //!< <a href="../target/aarch64/LDSMAX.html#LDSMAX_64_memop">64-bit LDSMAX</a>
  AMED_AARCH64_ENCODING_LDSMAXA_64_memop, //!< <a href="../target/aarch64/LDSMAX.html#LDSMAXA_64_memop">64-bit LDSMAXA</a>
  AMED_AARCH64_ENCODING_LDSMAXAL_64_memop, //!< <a href="../target/aarch64/LDSMAX.html#LDSMAXAL_64_memop">64-bit LDSMAXAL</a>
  AMED_AARCH64_ENCODING_LDSMAXL_64_memop, //!< <a href="../target/aarch64/LDSMAX.html#LDSMAXL_64_memop">64-bit LDSMAXL</a>
  AMED_AARCH64_ENCODING_LDSMAXAB_32_memop, //!< <a href="../target/aarch64/LDSMAXB.html#LDSMAXAB_32_memop">LDSMAXAB</a>
  AMED_AARCH64_ENCODING_LDSMAXALB_32_memop, //!< <a href="../target/aarch64/LDSMAXB.html#LDSMAXALB_32_memop">LDSMAXALB</a>
  AMED_AARCH64_ENCODING_LDSMAXB_32_memop, //!< <a href="../target/aarch64/LDSMAXB.html#LDSMAXB_32_memop">LDSMAXB</a>
  AMED_AARCH64_ENCODING_LDSMAXLB_32_memop, //!< <a href="../target/aarch64/LDSMAXB.html#LDSMAXLB_32_memop">LDSMAXLB</a>
  AMED_AARCH64_ENCODING_LDSMAXAH_32_memop, //!< <a href="../target/aarch64/LDSMAXH.html#LDSMAXAH_32_memop">LDSMAXAH</a>
  AMED_AARCH64_ENCODING_LDSMAXALH_32_memop, //!< <a href="../target/aarch64/LDSMAXH.html#LDSMAXALH_32_memop">LDSMAXALH</a>
  AMED_AARCH64_ENCODING_LDSMAXH_32_memop, //!< <a href="../target/aarch64/LDSMAXH.html#LDSMAXH_32_memop">LDSMAXH</a>
  AMED_AARCH64_ENCODING_LDSMAXLH_32_memop, //!< <a href="../target/aarch64/LDSMAXH.html#LDSMAXLH_32_memop">LDSMAXLH</a>
  AMED_AARCH64_ENCODING_LDSMIN_32_memop, //!< <a href="../target/aarch64/LDSMIN.html#LDSMIN_32_memop">32-bit LDSMIN</a>
  AMED_AARCH64_ENCODING_LDSMINA_32_memop, //!< <a href="../target/aarch64/LDSMIN.html#LDSMINA_32_memop">32-bit LDSMINA</a>
  AMED_AARCH64_ENCODING_LDSMINAL_32_memop, //!< <a href="../target/aarch64/LDSMIN.html#LDSMINAL_32_memop">32-bit LDSMINAL</a>
  AMED_AARCH64_ENCODING_LDSMINL_32_memop, //!< <a href="../target/aarch64/LDSMIN.html#LDSMINL_32_memop">32-bit LDSMINL</a>
  AMED_AARCH64_ENCODING_LDSMIN_64_memop, //!< <a href="../target/aarch64/LDSMIN.html#LDSMIN_64_memop">64-bit LDSMIN</a>
  AMED_AARCH64_ENCODING_LDSMINA_64_memop, //!< <a href="../target/aarch64/LDSMIN.html#LDSMINA_64_memop">64-bit LDSMINA</a>
  AMED_AARCH64_ENCODING_LDSMINAL_64_memop, //!< <a href="../target/aarch64/LDSMIN.html#LDSMINAL_64_memop">64-bit LDSMINAL</a>
  AMED_AARCH64_ENCODING_LDSMINL_64_memop, //!< <a href="../target/aarch64/LDSMIN.html#LDSMINL_64_memop">64-bit LDSMINL</a>
  AMED_AARCH64_ENCODING_LDSMINAB_32_memop, //!< <a href="../target/aarch64/LDSMINB.html#LDSMINAB_32_memop">LDSMINAB</a>
  AMED_AARCH64_ENCODING_LDSMINALB_32_memop, //!< <a href="../target/aarch64/LDSMINB.html#LDSMINALB_32_memop">LDSMINALB</a>
  AMED_AARCH64_ENCODING_LDSMINB_32_memop, //!< <a href="../target/aarch64/LDSMINB.html#LDSMINB_32_memop">LDSMINB</a>
  AMED_AARCH64_ENCODING_LDSMINLB_32_memop, //!< <a href="../target/aarch64/LDSMINB.html#LDSMINLB_32_memop">LDSMINLB</a>
  AMED_AARCH64_ENCODING_LDSMINAH_32_memop, //!< <a href="../target/aarch64/LDSMINH.html#LDSMINAH_32_memop">LDSMINAH</a>
  AMED_AARCH64_ENCODING_LDSMINALH_32_memop, //!< <a href="../target/aarch64/LDSMINH.html#LDSMINALH_32_memop">LDSMINALH</a>
  AMED_AARCH64_ENCODING_LDSMINH_32_memop, //!< <a href="../target/aarch64/LDSMINH.html#LDSMINH_32_memop">LDSMINH</a>
  AMED_AARCH64_ENCODING_LDSMINLH_32_memop, //!< <a href="../target/aarch64/LDSMINH.html#LDSMINLH_32_memop">LDSMINLH</a>
  AMED_AARCH64_ENCODING_LDTR_32_ldst_unpriv, //!< <a href="../target/aarch64/LDTR.html#LDTR_32_ldst_unpriv">32-bit</a>
  AMED_AARCH64_ENCODING_LDTR_64_ldst_unpriv, //!< <a href="../target/aarch64/LDTR.html#LDTR_64_ldst_unpriv">64-bit</a>
  AMED_AARCH64_ENCODING_LDTRB_32_ldst_unpriv, //!< <a href="../target/aarch64/LDTRB.html#LDTRB_32_ldst_unpriv">Unscaled offset</a>
  AMED_AARCH64_ENCODING_LDTRH_32_ldst_unpriv, //!< <a href="../target/aarch64/LDTRH.html#LDTRH_32_ldst_unpriv">Unscaled offset</a>
  AMED_AARCH64_ENCODING_LDTRSB_32_ldst_unpriv, //!< <a href="../target/aarch64/LDTRSB.html#LDTRSB_32_ldst_unpriv">32-bit</a>
  AMED_AARCH64_ENCODING_LDTRSB_64_ldst_unpriv, //!< <a href="../target/aarch64/LDTRSB.html#LDTRSB_64_ldst_unpriv">64-bit</a>
  AMED_AARCH64_ENCODING_LDTRSH_32_ldst_unpriv, //!< <a href="../target/aarch64/LDTRSH.html#LDTRSH_32_ldst_unpriv">32-bit</a>
  AMED_AARCH64_ENCODING_LDTRSH_64_ldst_unpriv, //!< <a href="../target/aarch64/LDTRSH.html#LDTRSH_64_ldst_unpriv">64-bit</a>
  AMED_AARCH64_ENCODING_LDTRSW_64_ldst_unpriv, //!< <a href="../target/aarch64/LDTRSW.html#LDTRSW_64_ldst_unpriv">Unscaled offset</a>
  AMED_AARCH64_ENCODING_LDUMAX_32_memop, //!< <a href="../target/aarch64/LDUMAX.html#LDUMAX_32_memop">32-bit LDUMAX</a>
  AMED_AARCH64_ENCODING_LDUMAXA_32_memop, //!< <a href="../target/aarch64/LDUMAX.html#LDUMAXA_32_memop">32-bit LDUMAXA</a>
  AMED_AARCH64_ENCODING_LDUMAXAL_32_memop, //!< <a href="../target/aarch64/LDUMAX.html#LDUMAXAL_32_memop">32-bit LDUMAXAL</a>
  AMED_AARCH64_ENCODING_LDUMAXL_32_memop, //!< <a href="../target/aarch64/LDUMAX.html#LDUMAXL_32_memop">32-bit LDUMAXL</a>
  AMED_AARCH64_ENCODING_LDUMAX_64_memop, //!< <a href="../target/aarch64/LDUMAX.html#LDUMAX_64_memop">64-bit LDUMAX</a>
  AMED_AARCH64_ENCODING_LDUMAXA_64_memop, //!< <a href="../target/aarch64/LDUMAX.html#LDUMAXA_64_memop">64-bit LDUMAXA</a>
  AMED_AARCH64_ENCODING_LDUMAXAL_64_memop, //!< <a href="../target/aarch64/LDUMAX.html#LDUMAXAL_64_memop">64-bit LDUMAXAL</a>
  AMED_AARCH64_ENCODING_LDUMAXL_64_memop, //!< <a href="../target/aarch64/LDUMAX.html#LDUMAXL_64_memop">64-bit LDUMAXL</a>
  AMED_AARCH64_ENCODING_LDUMAXAB_32_memop, //!< <a href="../target/aarch64/LDUMAXB.html#LDUMAXAB_32_memop">LDUMAXAB</a>
  AMED_AARCH64_ENCODING_LDUMAXALB_32_memop, //!< <a href="../target/aarch64/LDUMAXB.html#LDUMAXALB_32_memop">LDUMAXALB</a>
  AMED_AARCH64_ENCODING_LDUMAXB_32_memop, //!< <a href="../target/aarch64/LDUMAXB.html#LDUMAXB_32_memop">LDUMAXB</a>
  AMED_AARCH64_ENCODING_LDUMAXLB_32_memop, //!< <a href="../target/aarch64/LDUMAXB.html#LDUMAXLB_32_memop">LDUMAXLB</a>
  AMED_AARCH64_ENCODING_LDUMAXAH_32_memop, //!< <a href="../target/aarch64/LDUMAXH.html#LDUMAXAH_32_memop">LDUMAXAH</a>
  AMED_AARCH64_ENCODING_LDUMAXALH_32_memop, //!< <a href="../target/aarch64/LDUMAXH.html#LDUMAXALH_32_memop">LDUMAXALH</a>
  AMED_AARCH64_ENCODING_LDUMAXH_32_memop, //!< <a href="../target/aarch64/LDUMAXH.html#LDUMAXH_32_memop">LDUMAXH</a>
  AMED_AARCH64_ENCODING_LDUMAXLH_32_memop, //!< <a href="../target/aarch64/LDUMAXH.html#LDUMAXLH_32_memop">LDUMAXLH</a>
  AMED_AARCH64_ENCODING_LDUMIN_32_memop, //!< <a href="../target/aarch64/LDUMIN.html#LDUMIN_32_memop">32-bit LDUMIN</a>
  AMED_AARCH64_ENCODING_LDUMINA_32_memop, //!< <a href="../target/aarch64/LDUMIN.html#LDUMINA_32_memop">32-bit LDUMINA</a>
  AMED_AARCH64_ENCODING_LDUMINAL_32_memop, //!< <a href="../target/aarch64/LDUMIN.html#LDUMINAL_32_memop">32-bit LDUMINAL</a>
  AMED_AARCH64_ENCODING_LDUMINL_32_memop, //!< <a href="../target/aarch64/LDUMIN.html#LDUMINL_32_memop">32-bit LDUMINL</a>
  AMED_AARCH64_ENCODING_LDUMIN_64_memop, //!< <a href="../target/aarch64/LDUMIN.html#LDUMIN_64_memop">64-bit LDUMIN</a>
  AMED_AARCH64_ENCODING_LDUMINA_64_memop, //!< <a href="../target/aarch64/LDUMIN.html#LDUMINA_64_memop">64-bit LDUMINA</a>
  AMED_AARCH64_ENCODING_LDUMINAL_64_memop, //!< <a href="../target/aarch64/LDUMIN.html#LDUMINAL_64_memop">64-bit LDUMINAL</a>
  AMED_AARCH64_ENCODING_LDUMINL_64_memop, //!< <a href="../target/aarch64/LDUMIN.html#LDUMINL_64_memop">64-bit LDUMINL</a>
  AMED_AARCH64_ENCODING_LDUMINAB_32_memop, //!< <a href="../target/aarch64/LDUMINB.html#LDUMINAB_32_memop">LDUMINAB</a>
  AMED_AARCH64_ENCODING_LDUMINALB_32_memop, //!< <a href="../target/aarch64/LDUMINB.html#LDUMINALB_32_memop">LDUMINALB</a>
  AMED_AARCH64_ENCODING_LDUMINB_32_memop, //!< <a href="../target/aarch64/LDUMINB.html#LDUMINB_32_memop">LDUMINB</a>
  AMED_AARCH64_ENCODING_LDUMINLB_32_memop, //!< <a href="../target/aarch64/LDUMINB.html#LDUMINLB_32_memop">LDUMINLB</a>
  AMED_AARCH64_ENCODING_LDUMINAH_32_memop, //!< <a href="../target/aarch64/LDUMINH.html#LDUMINAH_32_memop">LDUMINAH</a>
  AMED_AARCH64_ENCODING_LDUMINALH_32_memop, //!< <a href="../target/aarch64/LDUMINH.html#LDUMINALH_32_memop">LDUMINALH</a>
  AMED_AARCH64_ENCODING_LDUMINH_32_memop, //!< <a href="../target/aarch64/LDUMINH.html#LDUMINH_32_memop">LDUMINH</a>
  AMED_AARCH64_ENCODING_LDUMINLH_32_memop, //!< <a href="../target/aarch64/LDUMINH.html#LDUMINLH_32_memop">LDUMINLH</a>
  AMED_AARCH64_ENCODING_LDUR_32_ldst_unscaled, //!< <a href="../target/aarch64/LDUR_gen.html#LDUR_32_ldst_unscaled">32-bit</a>
  AMED_AARCH64_ENCODING_LDUR_64_ldst_unscaled, //!< <a href="../target/aarch64/LDUR_gen.html#LDUR_64_ldst_unscaled">64-bit</a>
  AMED_AARCH64_ENCODING_LDURB_32_ldst_unscaled, //!< <a href="../target/aarch64/LDURB.html#LDURB_32_ldst_unscaled">Unscaled offset</a>
  AMED_AARCH64_ENCODING_LDURH_32_ldst_unscaled, //!< <a href="../target/aarch64/LDURH.html#LDURH_32_ldst_unscaled">Unscaled offset</a>
  AMED_AARCH64_ENCODING_LDURSB_32_ldst_unscaled, //!< <a href="../target/aarch64/LDURSB.html#LDURSB_32_ldst_unscaled">32-bit</a>
  AMED_AARCH64_ENCODING_LDURSB_64_ldst_unscaled, //!< <a href="../target/aarch64/LDURSB.html#LDURSB_64_ldst_unscaled">64-bit</a>
  AMED_AARCH64_ENCODING_LDURSH_32_ldst_unscaled, //!< <a href="../target/aarch64/LDURSH.html#LDURSH_32_ldst_unscaled">32-bit</a>
  AMED_AARCH64_ENCODING_LDURSH_64_ldst_unscaled, //!< <a href="../target/aarch64/LDURSH.html#LDURSH_64_ldst_unscaled">64-bit</a>
  AMED_AARCH64_ENCODING_LDURSW_64_ldst_unscaled, //!< <a href="../target/aarch64/LDURSW.html#LDURSW_64_ldst_unscaled">Unscaled offset</a>
  AMED_AARCH64_ENCODING_LDXP_LP32_ldstexcl, //!< <a href="../target/aarch64/LDXP.html#LDXP_LP32_ldstexcl">32-bit</a>
  AMED_AARCH64_ENCODING_LDXP_LP64_ldstexcl, //!< <a href="../target/aarch64/LDXP.html#LDXP_LP64_ldstexcl">64-bit</a>
  AMED_AARCH64_ENCODING_LDXR_LR32_ldstexcl, //!< <a href="../target/aarch64/LDXR.html#LDXR_LR32_ldstexcl">32-bit</a>
  AMED_AARCH64_ENCODING_LDXR_LR64_ldstexcl, //!< <a href="../target/aarch64/LDXR.html#LDXR_LR64_ldstexcl">64-bit</a>
  AMED_AARCH64_ENCODING_LDXRB_LR32_ldstexcl, //!< <a href="../target/aarch64/LDXRB.html#LDXRB_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_LDXRH_LR32_ldstexcl, //!< <a href="../target/aarch64/LDXRH.html#LDXRH_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_LSLV_32_dp_2src, //!< <a href="../target/aarch64/LSLV.html#LSLV_32_dp_2src">32-bit</a>
  AMED_AARCH64_ENCODING_LSLV_64_dp_2src, //!< <a href="../target/aarch64/LSLV.html#LSLV_64_dp_2src">64-bit</a>
  AMED_AARCH64_ENCODING_LSRV_32_dp_2src, //!< <a href="../target/aarch64/LSRV.html#LSRV_32_dp_2src">32-bit</a>
  AMED_AARCH64_ENCODING_LSRV_64_dp_2src, //!< <a href="../target/aarch64/LSRV.html#LSRV_64_dp_2src">64-bit</a>
  AMED_AARCH64_ENCODING_MADD_32A_dp_3src, //!< <a href="../target/aarch64/MADD.html#MADD_32A_dp_3src">32-bit</a>
  AMED_AARCH64_ENCODING_MADD_64A_dp_3src, //!< <a href="../target/aarch64/MADD.html#MADD_64A_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_MOVK_32_movewide, //!< <a href="../target/aarch64/MOVK.html#MOVK_32_movewide">32-bit</a>
  AMED_AARCH64_ENCODING_MOVK_64_movewide, //!< <a href="../target/aarch64/MOVK.html#MOVK_64_movewide">64-bit</a>
  AMED_AARCH64_ENCODING_MOVN_32_movewide, //!< <a href="../target/aarch64/MOVN.html#MOVN_32_movewide">32-bit</a>
  AMED_AARCH64_ENCODING_MOVN_64_movewide, //!< <a href="../target/aarch64/MOVN.html#MOVN_64_movewide">64-bit</a>
  AMED_AARCH64_ENCODING_MOVZ_32_movewide, //!< <a href="../target/aarch64/MOVZ.html#MOVZ_32_movewide">32-bit</a>
  AMED_AARCH64_ENCODING_MOVZ_64_movewide, //!< <a href="../target/aarch64/MOVZ.html#MOVZ_64_movewide">64-bit</a>
  AMED_AARCH64_ENCODING_MRS_RS_systemmove, //!< <a href="../target/aarch64/MRS.html#MRS_RS_systemmove">System</a>
  AMED_AARCH64_ENCODING_MSR_SI_pstate, //!< <a href="../target/aarch64/MSR_imm.html#MSR_SI_pstate">System</a>
  AMED_AARCH64_ENCODING_MSR_SR_systemmove, //!< <a href="../target/aarch64/MSR_reg.html#MSR_SR_systemmove">System</a>
  AMED_AARCH64_ENCODING_MSUB_32A_dp_3src, //!< <a href="../target/aarch64/MSUB.html#MSUB_32A_dp_3src">32-bit</a>
  AMED_AARCH64_ENCODING_MSUB_64A_dp_3src, //!< <a href="../target/aarch64/MSUB.html#MSUB_64A_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_NOP_HI_hints, //!< <a href="../target/aarch64/NOP.html#NOP_HI_hints">System</a>
  AMED_AARCH64_ENCODING_ORN_32_log_shift, //!< <a href="../target/aarch64/ORN_log_shift.html#ORN_32_log_shift">32-bit</a>
  AMED_AARCH64_ENCODING_ORN_64_log_shift, //!< <a href="../target/aarch64/ORN_log_shift.html#ORN_64_log_shift">64-bit</a>
  AMED_AARCH64_ENCODING_ORR_32_log_imm, //!< <a href="../target/aarch64/ORR_log_imm.html#ORR_32_log_imm">32-bit</a>
  AMED_AARCH64_ENCODING_ORR_64_log_imm, //!< <a href="../target/aarch64/ORR_log_imm.html#ORR_64_log_imm">64-bit</a>
  AMED_AARCH64_ENCODING_ORR_32_log_shift, //!< <a href="../target/aarch64/ORR_log_shift.html#ORR_32_log_shift">32-bit</a>
  AMED_AARCH64_ENCODING_ORR_64_log_shift, //!< <a href="../target/aarch64/ORR_log_shift.html#ORR_64_log_shift">64-bit</a>
  AMED_AARCH64_ENCODING_PACDA_64P_dp_1src, //!< <a href="../target/aarch64/PACDA.html#PACDA_64P_dp_1src">PACDA</a>
  AMED_AARCH64_ENCODING_PACDZA_64Z_dp_1src, //!< <a href="../target/aarch64/PACDA.html#PACDZA_64Z_dp_1src">PACDZA</a>
  AMED_AARCH64_ENCODING_PACDB_64P_dp_1src, //!< <a href="../target/aarch64/PACDB.html#PACDB_64P_dp_1src">PACDB</a>
  AMED_AARCH64_ENCODING_PACDZB_64Z_dp_1src, //!< <a href="../target/aarch64/PACDB.html#PACDZB_64Z_dp_1src">PACDZB</a>
  AMED_AARCH64_ENCODING_PACGA_64P_dp_2src, //!< <a href="../target/aarch64/PACGA.html#PACGA_64P_dp_2src">Integer</a>
  AMED_AARCH64_ENCODING_PACIA_64P_dp_1src, //!< <a href="../target/aarch64/PACIA.html#PACIA_64P_dp_1src">PACIA</a>
  AMED_AARCH64_ENCODING_PACIZA_64Z_dp_1src, //!< <a href="../target/aarch64/PACIA.html#PACIZA_64Z_dp_1src">PACIZA</a>
  AMED_AARCH64_ENCODING_PACIA1716_HI_hints, //!< <a href="../target/aarch64/PACIA.html#PACIA1716_HI_hints">PACIA1716</a>
  AMED_AARCH64_ENCODING_PACIASP_HI_hints, //!< <a href="../target/aarch64/PACIA.html#PACIASP_HI_hints">PACIASP</a>
  AMED_AARCH64_ENCODING_PACIAZ_HI_hints, //!< <a href="../target/aarch64/PACIA.html#PACIAZ_HI_hints">PACIAZ</a>
  AMED_AARCH64_ENCODING_PACIB_64P_dp_1src, //!< <a href="../target/aarch64/PACIB.html#PACIB_64P_dp_1src">PACIB</a>
  AMED_AARCH64_ENCODING_PACIZB_64Z_dp_1src, //!< <a href="../target/aarch64/PACIB.html#PACIZB_64Z_dp_1src">PACIZB</a>
  AMED_AARCH64_ENCODING_PACIB1716_HI_hints, //!< <a href="../target/aarch64/PACIB.html#PACIB1716_HI_hints">PACIB1716</a>
  AMED_AARCH64_ENCODING_PACIBSP_HI_hints, //!< <a href="../target/aarch64/PACIB.html#PACIBSP_HI_hints">PACIBSP</a>
  AMED_AARCH64_ENCODING_PACIBZ_HI_hints, //!< <a href="../target/aarch64/PACIB.html#PACIBZ_HI_hints">PACIBZ</a>
  AMED_AARCH64_ENCODING_PRFM_P_ldst_pos, //!< <a href="../target/aarch64/PRFM_imm.html#PRFM_P_ldst_pos">Unsigned offset</a>
  AMED_AARCH64_ENCODING_PRFM_P_loadlit, //!< <a href="../target/aarch64/PRFM_lit.html#PRFM_P_loadlit">Literal</a>
  AMED_AARCH64_ENCODING_PRFM_P_ldst_regoff, //!< <a href="../target/aarch64/PRFM_reg.html#PRFM_P_ldst_regoff">Integer</a>
  AMED_AARCH64_ENCODING_PRFUM_P_ldst_unscaled, //!< <a href="../target/aarch64/PRFUM.html#PRFUM_P_ldst_unscaled">Unscaled offset</a>
  AMED_AARCH64_ENCODING_PSB_HC_hints, //!< <a href="../target/aarch64/PSB.html#PSB_HC_hints">System</a>
  AMED_AARCH64_ENCODING_PSSBB_only_barriers, //!< <a href="../target/aarch64/PSSBB.html#PSSBB_only_barriers">System</a>
  AMED_AARCH64_ENCODING_RBIT_32_dp_1src, //!< <a href="../target/aarch64/RBIT_int.html#RBIT_32_dp_1src">32-bit</a>
  AMED_AARCH64_ENCODING_RBIT_64_dp_1src, //!< <a href="../target/aarch64/RBIT_int.html#RBIT_64_dp_1src">64-bit</a>
  AMED_AARCH64_ENCODING_RET_64R_branch_reg, //!< <a href="../target/aarch64/RET.html#RET_64R_branch_reg">Integer</a>
  AMED_AARCH64_ENCODING_RETAA_64E_branch_reg, //!< <a href="../target/aarch64/RETA.html#RETAA_64E_branch_reg">RETAA</a>
  AMED_AARCH64_ENCODING_RETAB_64E_branch_reg, //!< <a href="../target/aarch64/RETA.html#RETAB_64E_branch_reg">RETAB</a>
  AMED_AARCH64_ENCODING_REV_32_dp_1src, //!< <a href="../target/aarch64/REV.html#REV_32_dp_1src">32-bit</a>
  AMED_AARCH64_ENCODING_REV_64_dp_1src, //!< <a href="../target/aarch64/REV.html#REV_64_dp_1src">64-bit</a>
  AMED_AARCH64_ENCODING_REV16_32_dp_1src, //!< <a href="../target/aarch64/REV16_int.html#REV16_32_dp_1src">32-bit</a>
  AMED_AARCH64_ENCODING_REV16_64_dp_1src, //!< <a href="../target/aarch64/REV16_int.html#REV16_64_dp_1src">64-bit</a>
  AMED_AARCH64_ENCODING_REV32_64_dp_1src, //!< <a href="../target/aarch64/REV32_int.html#REV32_64_dp_1src">64-bit</a>
  AMED_AARCH64_ENCODING_RMIF_only_rmif, //!< <a href="../target/aarch64/RMIF.html#RMIF_only_rmif">Integer</a>
  AMED_AARCH64_ENCODING_RORV_32_dp_2src, //!< <a href="../target/aarch64/RORV.html#RORV_32_dp_2src">32-bit</a>
  AMED_AARCH64_ENCODING_RORV_64_dp_2src, //!< <a href="../target/aarch64/RORV.html#RORV_64_dp_2src">64-bit</a>
  AMED_AARCH64_ENCODING_SB_only_barriers, //!< <a href="../target/aarch64/SB.html#SB_only_barriers">System</a>
  AMED_AARCH64_ENCODING_SBC_32_addsub_carry, //!< <a href="../target/aarch64/SBC.html#SBC_32_addsub_carry">32-bit</a>
  AMED_AARCH64_ENCODING_SBC_64_addsub_carry, //!< <a href="../target/aarch64/SBC.html#SBC_64_addsub_carry">64-bit</a>
  AMED_AARCH64_ENCODING_SBCS_32_addsub_carry, //!< <a href="../target/aarch64/SBCS.html#SBCS_32_addsub_carry">32-bit</a>
  AMED_AARCH64_ENCODING_SBCS_64_addsub_carry, //!< <a href="../target/aarch64/SBCS.html#SBCS_64_addsub_carry">64-bit</a>
  AMED_AARCH64_ENCODING_SBFM_32M_bitfield, //!< <a href="../target/aarch64/SBFM.html#SBFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_SBFM_64M_bitfield, //!< <a href="../target/aarch64/SBFM.html#SBFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_SDIV_32_dp_2src, //!< <a href="../target/aarch64/SDIV.html#SDIV_32_dp_2src">32-bit</a>
  AMED_AARCH64_ENCODING_SDIV_64_dp_2src, //!< <a href="../target/aarch64/SDIV.html#SDIV_64_dp_2src">64-bit</a>
  AMED_AARCH64_ENCODING_SETF8_only_setf, //!< <a href="../target/aarch64/SETF.html#SETF8_only_setf">SETF8</a>
  AMED_AARCH64_ENCODING_SETF16_only_setf, //!< <a href="../target/aarch64/SETF.html#SETF16_only_setf">SETF16</a>
  AMED_AARCH64_ENCODING_SEV_HI_hints, //!< <a href="../target/aarch64/SEV.html#SEV_HI_hints">System</a>
  AMED_AARCH64_ENCODING_SEVL_HI_hints, //!< <a href="../target/aarch64/SEVL.html#SEVL_HI_hints">System</a>
  AMED_AARCH64_ENCODING_SMADDL_64WA_dp_3src, //!< <a href="../target/aarch64/SMADDL.html#SMADDL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_SMC_EX_exception, //!< <a href="../target/aarch64/SMC.html#SMC_EX_exception">System</a>
  AMED_AARCH64_ENCODING_SMSUBL_64WA_dp_3src, //!< <a href="../target/aarch64/SMSUBL.html#SMSUBL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_SMULH_64_dp_3src, //!< <a href="../target/aarch64/SMULH.html#SMULH_64_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_SSBB_only_barriers, //!< <a href="../target/aarch64/SSBB.html#SSBB_only_barriers">System</a>
  AMED_AARCH64_ENCODING_ST2G_64Spost_ldsttags, //!< <a href="../target/aarch64/ST2G.html#ST2G_64Spost_ldsttags">Post-index</a>
  AMED_AARCH64_ENCODING_ST2G_64Spre_ldsttags, //!< <a href="../target/aarch64/ST2G.html#ST2G_64Spre_ldsttags">Pre-index</a>
  AMED_AARCH64_ENCODING_ST2G_64Soffset_ldsttags, //!< <a href="../target/aarch64/ST2G.html#ST2G_64Soffset_ldsttags">Signed offset</a>
  AMED_AARCH64_ENCODING_STG_64Spost_ldsttags, //!< <a href="../target/aarch64/STG.html#STG_64Spost_ldsttags">Post-index</a>
  AMED_AARCH64_ENCODING_STG_64Spre_ldsttags, //!< <a href="../target/aarch64/STG.html#STG_64Spre_ldsttags">Pre-index</a>
  AMED_AARCH64_ENCODING_STG_64Soffset_ldsttags, //!< <a href="../target/aarch64/STG.html#STG_64Soffset_ldsttags">Signed offset</a>
  AMED_AARCH64_ENCODING_STGM_64bulk_ldsttags, //!< <a href="../target/aarch64/STGM.html#STGM_64bulk_ldsttags">Integer</a>
  AMED_AARCH64_ENCODING_STGP_64_ldstpair_post, //!< <a href="../target/aarch64/STGP.html#STGP_64_ldstpair_post">Post-index</a>
  AMED_AARCH64_ENCODING_STGP_64_ldstpair_pre, //!< <a href="../target/aarch64/STGP.html#STGP_64_ldstpair_pre">Pre-index</a>
  AMED_AARCH64_ENCODING_STGP_64_ldstpair_off, //!< <a href="../target/aarch64/STGP.html#STGP_64_ldstpair_off">Signed offset</a>
  AMED_AARCH64_ENCODING_STLLR_SL32_ldstexcl, //!< <a href="../target/aarch64/STLLR.html#STLLR_SL32_ldstexcl">32-bit</a>
  AMED_AARCH64_ENCODING_STLLR_SL64_ldstexcl, //!< <a href="../target/aarch64/STLLR.html#STLLR_SL64_ldstexcl">64-bit</a>
  AMED_AARCH64_ENCODING_STLLRB_SL32_ldstexcl, //!< <a href="../target/aarch64/STLLRB.html#STLLRB_SL32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_STLLRH_SL32_ldstexcl, //!< <a href="../target/aarch64/STLLRH.html#STLLRH_SL32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_STLR_SL32_ldstexcl, //!< <a href="../target/aarch64/STLR.html#STLR_SL32_ldstexcl">32-bit</a>
  AMED_AARCH64_ENCODING_STLR_SL64_ldstexcl, //!< <a href="../target/aarch64/STLR.html#STLR_SL64_ldstexcl">64-bit</a>
  AMED_AARCH64_ENCODING_STLRB_SL32_ldstexcl, //!< <a href="../target/aarch64/STLRB.html#STLRB_SL32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_STLRH_SL32_ldstexcl, //!< <a href="../target/aarch64/STLRH.html#STLRH_SL32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_STLUR_32_ldapstl_unscaled, //!< <a href="../target/aarch64/STLUR_gen.html#STLUR_32_ldapstl_unscaled">32-bit</a>
  AMED_AARCH64_ENCODING_STLUR_64_ldapstl_unscaled, //!< <a href="../target/aarch64/STLUR_gen.html#STLUR_64_ldapstl_unscaled">64-bit</a>
  AMED_AARCH64_ENCODING_STLURB_32_ldapstl_unscaled, //!< <a href="../target/aarch64/STLURB.html#STLURB_32_ldapstl_unscaled">Unscaled offset</a>
  AMED_AARCH64_ENCODING_STLURH_32_ldapstl_unscaled, //!< <a href="../target/aarch64/STLURH.html#STLURH_32_ldapstl_unscaled">Unscaled offset</a>
  AMED_AARCH64_ENCODING_STLXP_SP32_ldstexcl, //!< <a href="../target/aarch64/STLXP.html#STLXP_SP32_ldstexcl">32-bit</a>
  AMED_AARCH64_ENCODING_STLXP_SP64_ldstexcl, //!< <a href="../target/aarch64/STLXP.html#STLXP_SP64_ldstexcl">64-bit</a>
  AMED_AARCH64_ENCODING_STLXR_SR32_ldstexcl, //!< <a href="../target/aarch64/STLXR.html#STLXR_SR32_ldstexcl">32-bit</a>
  AMED_AARCH64_ENCODING_STLXR_SR64_ldstexcl, //!< <a href="../target/aarch64/STLXR.html#STLXR_SR64_ldstexcl">64-bit</a>
  AMED_AARCH64_ENCODING_STLXRB_SR32_ldstexcl, //!< <a href="../target/aarch64/STLXRB.html#STLXRB_SR32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_STLXRH_SR32_ldstexcl, //!< <a href="../target/aarch64/STLXRH.html#STLXRH_SR32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_STNP_32_ldstnapair_offs, //!< <a href="../target/aarch64/STNP_gen.html#STNP_32_ldstnapair_offs">32-bit</a>
  AMED_AARCH64_ENCODING_STNP_64_ldstnapair_offs, //!< <a href="../target/aarch64/STNP_gen.html#STNP_64_ldstnapair_offs">64-bit</a>
  AMED_AARCH64_ENCODING_STP_32_ldstpair_post, //!< <a href="../target/aarch64/STP_gen.html#STP_32_ldstpair_post">32-bit</a>
  AMED_AARCH64_ENCODING_STP_64_ldstpair_post, //!< <a href="../target/aarch64/STP_gen.html#STP_64_ldstpair_post">64-bit</a>
  AMED_AARCH64_ENCODING_STP_32_ldstpair_pre, //!< <a href="../target/aarch64/STP_gen.html#STP_32_ldstpair_pre">32-bit</a>
  AMED_AARCH64_ENCODING_STP_64_ldstpair_pre, //!< <a href="../target/aarch64/STP_gen.html#STP_64_ldstpair_pre">64-bit</a>
  AMED_AARCH64_ENCODING_STP_32_ldstpair_off, //!< <a href="../target/aarch64/STP_gen.html#STP_32_ldstpair_off">32-bit</a>
  AMED_AARCH64_ENCODING_STP_64_ldstpair_off, //!< <a href="../target/aarch64/STP_gen.html#STP_64_ldstpair_off">64-bit</a>
  AMED_AARCH64_ENCODING_STR_32_ldst_immpost, //!< <a href="../target/aarch64/STR_imm_gen.html#STR_32_ldst_immpost">32-bit</a>
  AMED_AARCH64_ENCODING_STR_64_ldst_immpost, //!< <a href="../target/aarch64/STR_imm_gen.html#STR_64_ldst_immpost">64-bit</a>
  AMED_AARCH64_ENCODING_STR_32_ldst_immpre, //!< <a href="../target/aarch64/STR_imm_gen.html#STR_32_ldst_immpre">32-bit</a>
  AMED_AARCH64_ENCODING_STR_64_ldst_immpre, //!< <a href="../target/aarch64/STR_imm_gen.html#STR_64_ldst_immpre">64-bit</a>
  AMED_AARCH64_ENCODING_STR_32_ldst_pos, //!< <a href="../target/aarch64/STR_imm_gen.html#STR_32_ldst_pos">32-bit</a>
  AMED_AARCH64_ENCODING_STR_64_ldst_pos, //!< <a href="../target/aarch64/STR_imm_gen.html#STR_64_ldst_pos">64-bit</a>
  AMED_AARCH64_ENCODING_STR_32_ldst_regoff, //!< <a href="../target/aarch64/STR_reg_gen.html#STR_32_ldst_regoff">32-bit</a>
  AMED_AARCH64_ENCODING_STR_64_ldst_regoff, //!< <a href="../target/aarch64/STR_reg_gen.html#STR_64_ldst_regoff">64-bit</a>
  AMED_AARCH64_ENCODING_STRB_32_ldst_immpost, //!< <a href="../target/aarch64/STRB_imm.html#STRB_32_ldst_immpost">Post-index</a>
  AMED_AARCH64_ENCODING_STRB_32_ldst_immpre, //!< <a href="../target/aarch64/STRB_imm.html#STRB_32_ldst_immpre">Pre-index</a>
  AMED_AARCH64_ENCODING_STRB_32_ldst_pos, //!< <a href="../target/aarch64/STRB_imm.html#STRB_32_ldst_pos">Unsigned offset</a>
  AMED_AARCH64_ENCODING_STRB_32B_ldst_regoff, //!< <a href="../target/aarch64/STRB_reg.html#STRB_32B_ldst_regoff">Extended register</a>
  AMED_AARCH64_ENCODING_STRB_32BL_ldst_regoff, //!< <a href="../target/aarch64/STRB_reg.html#STRB_32BL_ldst_regoff">Shifted register</a>
  AMED_AARCH64_ENCODING_STRH_32_ldst_immpost, //!< <a href="../target/aarch64/STRH_imm.html#STRH_32_ldst_immpost">Post-index</a>
  AMED_AARCH64_ENCODING_STRH_32_ldst_immpre, //!< <a href="../target/aarch64/STRH_imm.html#STRH_32_ldst_immpre">Pre-index</a>
  AMED_AARCH64_ENCODING_STRH_32_ldst_pos, //!< <a href="../target/aarch64/STRH_imm.html#STRH_32_ldst_pos">Unsigned offset</a>
  AMED_AARCH64_ENCODING_STRH_32_ldst_regoff, //!< <a href="../target/aarch64/STRH_reg.html#STRH_32_ldst_regoff">32-bit</a>
  AMED_AARCH64_ENCODING_STTR_32_ldst_unpriv, //!< <a href="../target/aarch64/STTR.html#STTR_32_ldst_unpriv">32-bit</a>
  AMED_AARCH64_ENCODING_STTR_64_ldst_unpriv, //!< <a href="../target/aarch64/STTR.html#STTR_64_ldst_unpriv">64-bit</a>
  AMED_AARCH64_ENCODING_STTRB_32_ldst_unpriv, //!< <a href="../target/aarch64/STTRB.html#STTRB_32_ldst_unpriv">Unscaled offset</a>
  AMED_AARCH64_ENCODING_STTRH_32_ldst_unpriv, //!< <a href="../target/aarch64/STTRH.html#STTRH_32_ldst_unpriv">Unscaled offset</a>
  AMED_AARCH64_ENCODING_STUR_32_ldst_unscaled, //!< <a href="../target/aarch64/STUR_gen.html#STUR_32_ldst_unscaled">32-bit</a>
  AMED_AARCH64_ENCODING_STUR_64_ldst_unscaled, //!< <a href="../target/aarch64/STUR_gen.html#STUR_64_ldst_unscaled">64-bit</a>
  AMED_AARCH64_ENCODING_STURB_32_ldst_unscaled, //!< <a href="../target/aarch64/STURB.html#STURB_32_ldst_unscaled">Unscaled offset</a>
  AMED_AARCH64_ENCODING_STURH_32_ldst_unscaled, //!< <a href="../target/aarch64/STURH.html#STURH_32_ldst_unscaled">Unscaled offset</a>
  AMED_AARCH64_ENCODING_STXP_SP32_ldstexcl, //!< <a href="../target/aarch64/STXP.html#STXP_SP32_ldstexcl">32-bit</a>
  AMED_AARCH64_ENCODING_STXP_SP64_ldstexcl, //!< <a href="../target/aarch64/STXP.html#STXP_SP64_ldstexcl">64-bit</a>
  AMED_AARCH64_ENCODING_STXR_SR32_ldstexcl, //!< <a href="../target/aarch64/STXR.html#STXR_SR32_ldstexcl">32-bit</a>
  AMED_AARCH64_ENCODING_STXR_SR64_ldstexcl, //!< <a href="../target/aarch64/STXR.html#STXR_SR64_ldstexcl">64-bit</a>
  AMED_AARCH64_ENCODING_STXRB_SR32_ldstexcl, //!< <a href="../target/aarch64/STXRB.html#STXRB_SR32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_STXRH_SR32_ldstexcl, //!< <a href="../target/aarch64/STXRH.html#STXRH_SR32_ldstexcl">No offset</a>
  AMED_AARCH64_ENCODING_STZ2G_64Spost_ldsttags, //!< <a href="../target/aarch64/STZ2G.html#STZ2G_64Spost_ldsttags">Post-index</a>
  AMED_AARCH64_ENCODING_STZ2G_64Spre_ldsttags, //!< <a href="../target/aarch64/STZ2G.html#STZ2G_64Spre_ldsttags">Pre-index</a>
  AMED_AARCH64_ENCODING_STZ2G_64Soffset_ldsttags, //!< <a href="../target/aarch64/STZ2G.html#STZ2G_64Soffset_ldsttags">Signed offset</a>
  AMED_AARCH64_ENCODING_STZG_64Spost_ldsttags, //!< <a href="../target/aarch64/STZG.html#STZG_64Spost_ldsttags">Post-index</a>
  AMED_AARCH64_ENCODING_STZG_64Spre_ldsttags, //!< <a href="../target/aarch64/STZG.html#STZG_64Spre_ldsttags">Pre-index</a>
  AMED_AARCH64_ENCODING_STZG_64Soffset_ldsttags, //!< <a href="../target/aarch64/STZG.html#STZG_64Soffset_ldsttags">Signed offset</a>
  AMED_AARCH64_ENCODING_STZGM_64bulk_ldsttags, //!< <a href="../target/aarch64/STZGM.html#STZGM_64bulk_ldsttags">Integer</a>
  AMED_AARCH64_ENCODING_SUB_32_addsub_ext, //!< <a href="../target/aarch64/SUB_addsub_ext.html#SUB_32_addsub_ext">32-bit</a>
  AMED_AARCH64_ENCODING_SUB_64_addsub_ext, //!< <a href="../target/aarch64/SUB_addsub_ext.html#SUB_64_addsub_ext">64-bit</a>
  AMED_AARCH64_ENCODING_SUB_32_addsub_imm, //!< <a href="../target/aarch64/SUB_addsub_imm.html#SUB_32_addsub_imm">32-bit</a>
  AMED_AARCH64_ENCODING_SUB_64_addsub_imm, //!< <a href="../target/aarch64/SUB_addsub_imm.html#SUB_64_addsub_imm">64-bit</a>
  AMED_AARCH64_ENCODING_SUB_32_addsub_shift, //!< <a href="../target/aarch64/SUB_addsub_shift.html#SUB_32_addsub_shift">32-bit</a>
  AMED_AARCH64_ENCODING_SUB_64_addsub_shift, //!< <a href="../target/aarch64/SUB_addsub_shift.html#SUB_64_addsub_shift">64-bit</a>
  AMED_AARCH64_ENCODING_SUBG_64_addsub_immtags, //!< <a href="../target/aarch64/SUBG.html#SUBG_64_addsub_immtags">Integer</a>
  AMED_AARCH64_ENCODING_SUBP_64S_dp_2src, //!< <a href="../target/aarch64/SUBP.html#SUBP_64S_dp_2src">Integer</a>
  AMED_AARCH64_ENCODING_SUBPS_64S_dp_2src, //!< <a href="../target/aarch64/SUBPS.html#SUBPS_64S_dp_2src">Integer</a>
  AMED_AARCH64_ENCODING_SUBS_32S_addsub_ext, //!< <a href="../target/aarch64/SUBS_addsub_ext.html#SUBS_32S_addsub_ext">32-bit</a>
  AMED_AARCH64_ENCODING_SUBS_64S_addsub_ext, //!< <a href="../target/aarch64/SUBS_addsub_ext.html#SUBS_64S_addsub_ext">64-bit</a>
  AMED_AARCH64_ENCODING_SUBS_32S_addsub_imm, //!< <a href="../target/aarch64/SUBS_addsub_imm.html#SUBS_32S_addsub_imm">32-bit</a>
  AMED_AARCH64_ENCODING_SUBS_64S_addsub_imm, //!< <a href="../target/aarch64/SUBS_addsub_imm.html#SUBS_64S_addsub_imm">64-bit</a>
  AMED_AARCH64_ENCODING_SUBS_32_addsub_shift, //!< <a href="../target/aarch64/SUBS_addsub_shift.html#SUBS_32_addsub_shift">32-bit</a>
  AMED_AARCH64_ENCODING_SUBS_64_addsub_shift, //!< <a href="../target/aarch64/SUBS_addsub_shift.html#SUBS_64_addsub_shift">64-bit</a>
  AMED_AARCH64_ENCODING_SVC_EX_exception, //!< <a href="../target/aarch64/SVC.html#SVC_EX_exception">System</a>
  AMED_AARCH64_ENCODING_SWP_32_memop, //!< <a href="../target/aarch64/SWP.html#SWP_32_memop">32-bit SWP</a>
  AMED_AARCH64_ENCODING_SWPA_32_memop, //!< <a href="../target/aarch64/SWP.html#SWPA_32_memop">32-bit SWPA</a>
  AMED_AARCH64_ENCODING_SWPAL_32_memop, //!< <a href="../target/aarch64/SWP.html#SWPAL_32_memop">32-bit SWPAL</a>
  AMED_AARCH64_ENCODING_SWPL_32_memop, //!< <a href="../target/aarch64/SWP.html#SWPL_32_memop">32-bit SWPL</a>
  AMED_AARCH64_ENCODING_SWP_64_memop, //!< <a href="../target/aarch64/SWP.html#SWP_64_memop">64-bit SWP</a>
  AMED_AARCH64_ENCODING_SWPA_64_memop, //!< <a href="../target/aarch64/SWP.html#SWPA_64_memop">64-bit SWPA</a>
  AMED_AARCH64_ENCODING_SWPAL_64_memop, //!< <a href="../target/aarch64/SWP.html#SWPAL_64_memop">64-bit SWPAL</a>
  AMED_AARCH64_ENCODING_SWPL_64_memop, //!< <a href="../target/aarch64/SWP.html#SWPL_64_memop">64-bit SWPL</a>
  AMED_AARCH64_ENCODING_SWPAB_32_memop, //!< <a href="../target/aarch64/SWPB.html#SWPAB_32_memop">SWPAB</a>
  AMED_AARCH64_ENCODING_SWPALB_32_memop, //!< <a href="../target/aarch64/SWPB.html#SWPALB_32_memop">SWPALB</a>
  AMED_AARCH64_ENCODING_SWPB_32_memop, //!< <a href="../target/aarch64/SWPB.html#SWPB_32_memop">SWPB</a>
  AMED_AARCH64_ENCODING_SWPLB_32_memop, //!< <a href="../target/aarch64/SWPB.html#SWPLB_32_memop">SWPLB</a>
  AMED_AARCH64_ENCODING_SWPAH_32_memop, //!< <a href="../target/aarch64/SWPH.html#SWPAH_32_memop">SWPAH</a>
  AMED_AARCH64_ENCODING_SWPALH_32_memop, //!< <a href="../target/aarch64/SWPH.html#SWPALH_32_memop">SWPALH</a>
  AMED_AARCH64_ENCODING_SWPH_32_memop, //!< <a href="../target/aarch64/SWPH.html#SWPH_32_memop">SWPH</a>
  AMED_AARCH64_ENCODING_SWPLH_32_memop, //!< <a href="../target/aarch64/SWPH.html#SWPLH_32_memop">SWPLH</a>
  AMED_AARCH64_ENCODING_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/SYS.html#SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_ENCODING_SYSL_RC_systeminstrs, //!< <a href="../target/aarch64/SYSL.html#SYSL_RC_systeminstrs">System</a>
  AMED_AARCH64_ENCODING_TBNZ_only_testbranch, //!< <a href="../target/aarch64/TBNZ.html#TBNZ_only_testbranch">14-bit signed PC-relative branch offset</a>
  AMED_AARCH64_ENCODING_TBZ_only_testbranch, //!< <a href="../target/aarch64/TBZ.html#TBZ_only_testbranch">14-bit signed PC-relative branch offset</a>
  AMED_AARCH64_ENCODING_TCANCEL_EX_exception, //!< <a href="../target/aarch64/TCANCEL.html#TCANCEL_EX_exception">System</a>
  AMED_AARCH64_ENCODING_TCOMMIT_only_barriers, //!< <a href="../target/aarch64/TCOMMIT.html#TCOMMIT_only_barriers">System</a>
  AMED_AARCH64_ENCODING_TSB_HC_hints, //!< <a href="../target/aarch64/TSB.html#TSB_HC_hints">System</a>
  AMED_AARCH64_ENCODING_TSTART_BR_systemresult, //!< <a href="../target/aarch64/TSTART.html#TSTART_BR_systemresult">System</a>
  AMED_AARCH64_ENCODING_TTEST_BR_systemresult, //!< <a href="../target/aarch64/TTEST.html#TTEST_BR_systemresult">System</a>
  AMED_AARCH64_ENCODING_UBFM_32M_bitfield, //!< <a href="../target/aarch64/UBFM.html#UBFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_UBFM_64M_bitfield, //!< <a href="../target/aarch64/UBFM.html#UBFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_UDF_only_perm_undef, //!< <a href="../target/aarch64/UDF_perm_undef.html#UDF_only_perm_undef">Integer</a>
  AMED_AARCH64_ENCODING_UDIV_32_dp_2src, //!< <a href="../target/aarch64/UDIV.html#UDIV_32_dp_2src">32-bit</a>
  AMED_AARCH64_ENCODING_UDIV_64_dp_2src, //!< <a href="../target/aarch64/UDIV.html#UDIV_64_dp_2src">64-bit</a>
  AMED_AARCH64_ENCODING_UMADDL_64WA_dp_3src, //!< <a href="../target/aarch64/UMADDL.html#UMADDL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_UMSUBL_64WA_dp_3src, //!< <a href="../target/aarch64/UMSUBL.html#UMSUBL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_UMULH_64_dp_3src, //!< <a href="../target/aarch64/UMULH.html#UMULH_64_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_WFE_HI_hints, //!< <a href="../target/aarch64/WFE.html#WFE_HI_hints">System</a>
  AMED_AARCH64_ENCODING_WFI_HI_hints, //!< <a href="../target/aarch64/WFI.html#WFI_HI_hints">System</a>
  AMED_AARCH64_ENCODING_XAFLAG_M_pstate, //!< <a href="../target/aarch64/XAFLAG.html#XAFLAG_M_pstate">System</a>
  AMED_AARCH64_ENCODING_XPACD_64Z_dp_1src, //!< <a href="../target/aarch64/XPAC.html#XPACD_64Z_dp_1src">XPACD</a>
  AMED_AARCH64_ENCODING_XPACI_64Z_dp_1src, //!< <a href="../target/aarch64/XPAC.html#XPACI_64Z_dp_1src">XPACI</a>
  AMED_AARCH64_ENCODING_XPACLRI_HI_hints, //!< <a href="../target/aarch64/XPAC.html#XPACLRI_HI_hints">System</a>
  AMED_AARCH64_ENCODING_YIELD_HI_hints, //!< <a href="../target/aarch64/YIELD.html#YIELD_HI_hints">System</a>
  AMED_AARCH64_ENCODING_ASR_ASRV_32_dp_2src, //!< <a href="../target/aarch64/ASR_ASRV.html#ASR_ASRV_32_dp_2src">32-bit</a>
  AMED_AARCH64_ENCODING_ASR_ASRV_64_dp_2src, //!< <a href="../target/aarch64/ASR_ASRV.html#ASR_ASRV_64_dp_2src">64-bit</a>
  AMED_AARCH64_ENCODING_ASR_SBFM_32M_bitfield, //!< <a href="../target/aarch64/ASR_SBFM.html#ASR_SBFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_ASR_SBFM_64M_bitfield, //!< <a href="../target/aarch64/ASR_SBFM.html#ASR_SBFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_AT_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/AT_SYS.html#AT_SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_ENCODING_BFC_BFM_32M_bitfield, //!< <a href="../target/aarch64/BFC_BFM.html#BFC_BFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_BFC_BFM_64M_bitfield, //!< <a href="../target/aarch64/BFC_BFM.html#BFC_BFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_BFI_BFM_32M_bitfield, //!< <a href="../target/aarch64/BFI_BFM.html#BFI_BFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_BFI_BFM_64M_bitfield, //!< <a href="../target/aarch64/BFI_BFM.html#BFI_BFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_BFXIL_BFM_32M_bitfield, //!< <a href="../target/aarch64/BFXIL_BFM.html#BFXIL_BFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_BFXIL_BFM_64M_bitfield, //!< <a href="../target/aarch64/BFXIL_BFM.html#BFXIL_BFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_CFP_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/CFP_SYS.html#CFP_SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_ENCODING_CINC_CSINC_32_condsel, //!< <a href="../target/aarch64/CINC_CSINC.html#CINC_CSINC_32_condsel">32-bit</a>
  AMED_AARCH64_ENCODING_CINC_CSINC_64_condsel, //!< <a href="../target/aarch64/CINC_CSINC.html#CINC_CSINC_64_condsel">64-bit</a>
  AMED_AARCH64_ENCODING_CINV_CSINV_32_condsel, //!< <a href="../target/aarch64/CINV_CSINV.html#CINV_CSINV_32_condsel">32-bit</a>
  AMED_AARCH64_ENCODING_CINV_CSINV_64_condsel, //!< <a href="../target/aarch64/CINV_CSINV.html#CINV_CSINV_64_condsel">64-bit</a>
  AMED_AARCH64_ENCODING_CMN_ADDS_32S_addsub_ext, //!< <a href="../target/aarch64/CMN_ADDS_addsub_ext.html#CMN_ADDS_32S_addsub_ext">32-bit</a>
  AMED_AARCH64_ENCODING_CMN_ADDS_64S_addsub_ext, //!< <a href="../target/aarch64/CMN_ADDS_addsub_ext.html#CMN_ADDS_64S_addsub_ext">64-bit</a>
  AMED_AARCH64_ENCODING_CMN_ADDS_32S_addsub_imm, //!< <a href="../target/aarch64/CMN_ADDS_addsub_imm.html#CMN_ADDS_32S_addsub_imm">32-bit</a>
  AMED_AARCH64_ENCODING_CMN_ADDS_64S_addsub_imm, //!< <a href="../target/aarch64/CMN_ADDS_addsub_imm.html#CMN_ADDS_64S_addsub_imm">64-bit</a>
  AMED_AARCH64_ENCODING_CMN_ADDS_32_addsub_shift, //!< <a href="../target/aarch64/CMN_ADDS_addsub_shift.html#CMN_ADDS_32_addsub_shift">32-bit</a>
  AMED_AARCH64_ENCODING_CMN_ADDS_64_addsub_shift, //!< <a href="../target/aarch64/CMN_ADDS_addsub_shift.html#CMN_ADDS_64_addsub_shift">64-bit</a>
  AMED_AARCH64_ENCODING_CMP_SUBS_32S_addsub_ext, //!< <a href="../target/aarch64/CMP_SUBS_addsub_ext.html#CMP_SUBS_32S_addsub_ext">32-bit</a>
  AMED_AARCH64_ENCODING_CMP_SUBS_64S_addsub_ext, //!< <a href="../target/aarch64/CMP_SUBS_addsub_ext.html#CMP_SUBS_64S_addsub_ext">64-bit</a>
  AMED_AARCH64_ENCODING_CMP_SUBS_32S_addsub_imm, //!< <a href="../target/aarch64/CMP_SUBS_addsub_imm.html#CMP_SUBS_32S_addsub_imm">32-bit</a>
  AMED_AARCH64_ENCODING_CMP_SUBS_64S_addsub_imm, //!< <a href="../target/aarch64/CMP_SUBS_addsub_imm.html#CMP_SUBS_64S_addsub_imm">64-bit</a>
  AMED_AARCH64_ENCODING_CMP_SUBS_32_addsub_shift, //!< <a href="../target/aarch64/CMP_SUBS_addsub_shift.html#CMP_SUBS_32_addsub_shift">32-bit</a>
  AMED_AARCH64_ENCODING_CMP_SUBS_64_addsub_shift, //!< <a href="../target/aarch64/CMP_SUBS_addsub_shift.html#CMP_SUBS_64_addsub_shift">64-bit</a>
  AMED_AARCH64_ENCODING_CMPP_SUBPS_64S_dp_2src, //!< <a href="../target/aarch64/CMPP_SUBPS.html#CMPP_SUBPS_64S_dp_2src">Integer</a>
  AMED_AARCH64_ENCODING_CNEG_CSNEG_32_condsel, //!< <a href="../target/aarch64/CNEG_CSNEG.html#CNEG_CSNEG_32_condsel">32-bit</a>
  AMED_AARCH64_ENCODING_CNEG_CSNEG_64_condsel, //!< <a href="../target/aarch64/CNEG_CSNEG.html#CNEG_CSNEG_64_condsel">64-bit</a>
  AMED_AARCH64_ENCODING_CPP_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/CPP_SYS.html#CPP_SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_ENCODING_CSET_CSINC_32_condsel, //!< <a href="../target/aarch64/CSET_CSINC.html#CSET_CSINC_32_condsel">32-bit</a>
  AMED_AARCH64_ENCODING_CSET_CSINC_64_condsel, //!< <a href="../target/aarch64/CSET_CSINC.html#CSET_CSINC_64_condsel">64-bit</a>
  AMED_AARCH64_ENCODING_CSETM_CSINV_32_condsel, //!< <a href="../target/aarch64/CSETM_CSINV.html#CSETM_CSINV_32_condsel">32-bit</a>
  AMED_AARCH64_ENCODING_CSETM_CSINV_64_condsel, //!< <a href="../target/aarch64/CSETM_CSINV.html#CSETM_CSINV_64_condsel">64-bit</a>
  AMED_AARCH64_ENCODING_DC_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/DC_SYS.html#DC_SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_ENCODING_DFB_DSB_BO_barriers, //!< <a href="../target/aarch64/DFB_DSB.html#DFB_DSB_BO_barriers">System</a>
  AMED_AARCH64_ENCODING_DVP_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/DVP_SYS.html#DVP_SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_ENCODING_IC_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/IC_SYS.html#IC_SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_ENCODING_LSL_LSLV_32_dp_2src, //!< <a href="../target/aarch64/LSL_LSLV.html#LSL_LSLV_32_dp_2src">32-bit</a>
  AMED_AARCH64_ENCODING_LSL_LSLV_64_dp_2src, //!< <a href="../target/aarch64/LSL_LSLV.html#LSL_LSLV_64_dp_2src">64-bit</a>
  AMED_AARCH64_ENCODING_LSL_UBFM_32M_bitfield, //!< <a href="../target/aarch64/LSL_UBFM.html#LSL_UBFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_LSL_UBFM_64M_bitfield, //!< <a href="../target/aarch64/LSL_UBFM.html#LSL_UBFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_LSR_LSRV_32_dp_2src, //!< <a href="../target/aarch64/LSR_LSRV.html#LSR_LSRV_32_dp_2src">32-bit</a>
  AMED_AARCH64_ENCODING_LSR_LSRV_64_dp_2src, //!< <a href="../target/aarch64/LSR_LSRV.html#LSR_LSRV_64_dp_2src">64-bit</a>
  AMED_AARCH64_ENCODING_LSR_UBFM_32M_bitfield, //!< <a href="../target/aarch64/LSR_UBFM.html#LSR_UBFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_LSR_UBFM_64M_bitfield, //!< <a href="../target/aarch64/LSR_UBFM.html#LSR_UBFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_MNEG_MSUB_32A_dp_3src, //!< <a href="../target/aarch64/MNEG_MSUB.html#MNEG_MSUB_32A_dp_3src">32-bit</a>
  AMED_AARCH64_ENCODING_MNEG_MSUB_64A_dp_3src, //!< <a href="../target/aarch64/MNEG_MSUB.html#MNEG_MSUB_64A_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_MOV_ADD_32_addsub_imm, //!< <a href="../target/aarch64/MOV_ADD_addsub_imm.html#MOV_ADD_32_addsub_imm">32-bit</a>
  AMED_AARCH64_ENCODING_MOV_ADD_64_addsub_imm, //!< <a href="../target/aarch64/MOV_ADD_addsub_imm.html#MOV_ADD_64_addsub_imm">64-bit</a>
  AMED_AARCH64_ENCODING_MOV_MOVN_32_movewide, //!< <a href="../target/aarch64/MOV_MOVN.html#MOV_MOVN_32_movewide">32-bit</a>
  AMED_AARCH64_ENCODING_MOV_MOVN_64_movewide, //!< <a href="../target/aarch64/MOV_MOVN.html#MOV_MOVN_64_movewide">64-bit</a>
  AMED_AARCH64_ENCODING_MOV_MOVZ_32_movewide, //!< <a href="../target/aarch64/MOV_MOVZ.html#MOV_MOVZ_32_movewide">32-bit</a>
  AMED_AARCH64_ENCODING_MOV_MOVZ_64_movewide, //!< <a href="../target/aarch64/MOV_MOVZ.html#MOV_MOVZ_64_movewide">64-bit</a>
  AMED_AARCH64_ENCODING_MOV_ORR_32_log_imm, //!< <a href="../target/aarch64/MOV_ORR_log_imm.html#MOV_ORR_32_log_imm">32-bit</a>
  AMED_AARCH64_ENCODING_MOV_ORR_64_log_imm, //!< <a href="../target/aarch64/MOV_ORR_log_imm.html#MOV_ORR_64_log_imm">64-bit</a>
  AMED_AARCH64_ENCODING_MOV_ORR_32_log_shift, //!< <a href="../target/aarch64/MOV_ORR_log_shift.html#MOV_ORR_32_log_shift">32-bit</a>
  AMED_AARCH64_ENCODING_MOV_ORR_64_log_shift, //!< <a href="../target/aarch64/MOV_ORR_log_shift.html#MOV_ORR_64_log_shift">64-bit</a>
  AMED_AARCH64_ENCODING_MUL_MADD_32A_dp_3src, //!< <a href="../target/aarch64/MUL_MADD.html#MUL_MADD_32A_dp_3src">32-bit</a>
  AMED_AARCH64_ENCODING_MUL_MADD_64A_dp_3src, //!< <a href="../target/aarch64/MUL_MADD.html#MUL_MADD_64A_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_MVN_ORN_32_log_shift, //!< <a href="../target/aarch64/MVN_ORN_log_shift.html#MVN_ORN_32_log_shift">32-bit</a>
  AMED_AARCH64_ENCODING_MVN_ORN_64_log_shift, //!< <a href="../target/aarch64/MVN_ORN_log_shift.html#MVN_ORN_64_log_shift">64-bit</a>
  AMED_AARCH64_ENCODING_NEG_SUB_32_addsub_shift, //!< <a href="../target/aarch64/NEG_SUB_addsub_shift.html#NEG_SUB_32_addsub_shift">32-bit</a>
  AMED_AARCH64_ENCODING_NEG_SUB_64_addsub_shift, //!< <a href="../target/aarch64/NEG_SUB_addsub_shift.html#NEG_SUB_64_addsub_shift">64-bit</a>
  AMED_AARCH64_ENCODING_NEGS_SUBS_32_addsub_shift, //!< <a href="../target/aarch64/NEGS_SUBS_addsub_shift.html#NEGS_SUBS_32_addsub_shift">32-bit</a>
  AMED_AARCH64_ENCODING_NEGS_SUBS_64_addsub_shift, //!< <a href="../target/aarch64/NEGS_SUBS_addsub_shift.html#NEGS_SUBS_64_addsub_shift">64-bit</a>
  AMED_AARCH64_ENCODING_NGC_SBC_32_addsub_carry, //!< <a href="../target/aarch64/NGC_SBC.html#NGC_SBC_32_addsub_carry">32-bit</a>
  AMED_AARCH64_ENCODING_NGC_SBC_64_addsub_carry, //!< <a href="../target/aarch64/NGC_SBC.html#NGC_SBC_64_addsub_carry">64-bit</a>
  AMED_AARCH64_ENCODING_NGCS_SBCS_32_addsub_carry, //!< <a href="../target/aarch64/NGCS_SBCS.html#NGCS_SBCS_32_addsub_carry">32-bit</a>
  AMED_AARCH64_ENCODING_NGCS_SBCS_64_addsub_carry, //!< <a href="../target/aarch64/NGCS_SBCS.html#NGCS_SBCS_64_addsub_carry">64-bit</a>
  AMED_AARCH64_ENCODING_REV64_REV_64_dp_1src, //!< <a href="../target/aarch64/REV64_REV.html#REV64_REV_64_dp_1src">64-bit</a>
  AMED_AARCH64_ENCODING_ROR_EXTR_32_extract, //!< <a href="../target/aarch64/ROR_EXTR.html#ROR_EXTR_32_extract">32-bit</a>
  AMED_AARCH64_ENCODING_ROR_EXTR_64_extract, //!< <a href="../target/aarch64/ROR_EXTR.html#ROR_EXTR_64_extract">64-bit</a>
  AMED_AARCH64_ENCODING_ROR_RORV_32_dp_2src, //!< <a href="../target/aarch64/ROR_RORV.html#ROR_RORV_32_dp_2src">32-bit</a>
  AMED_AARCH64_ENCODING_ROR_RORV_64_dp_2src, //!< <a href="../target/aarch64/ROR_RORV.html#ROR_RORV_64_dp_2src">64-bit</a>
  AMED_AARCH64_ENCODING_SBFIZ_SBFM_32M_bitfield, //!< <a href="../target/aarch64/SBFIZ_SBFM.html#SBFIZ_SBFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_SBFIZ_SBFM_64M_bitfield, //!< <a href="../target/aarch64/SBFIZ_SBFM.html#SBFIZ_SBFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_SBFX_SBFM_32M_bitfield, //!< <a href="../target/aarch64/SBFX_SBFM.html#SBFX_SBFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_SBFX_SBFM_64M_bitfield, //!< <a href="../target/aarch64/SBFX_SBFM.html#SBFX_SBFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_SMNEGL_SMSUBL_64WA_dp_3src, //!< <a href="../target/aarch64/SMNEGL_SMSUBL.html#SMNEGL_SMSUBL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_SMULL_SMADDL_64WA_dp_3src, //!< <a href="../target/aarch64/SMULL_SMADDL.html#SMULL_SMADDL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_STADD_LDADD_32_memop, //!< <a href="../target/aarch64/STADD_LDADD.html#STADD_LDADD_32_memop">32-bit LDADD alias</a>
  AMED_AARCH64_ENCODING_STADDL_LDADDL_32_memop, //!< <a href="../target/aarch64/STADD_LDADD.html#STADDL_LDADDL_32_memop">32-bit LDADDL alias</a>
  AMED_AARCH64_ENCODING_STADD_LDADD_64_memop, //!< <a href="../target/aarch64/STADD_LDADD.html#STADD_LDADD_64_memop">64-bit LDADD alias</a>
  AMED_AARCH64_ENCODING_STADDL_LDADDL_64_memop, //!< <a href="../target/aarch64/STADD_LDADD.html#STADDL_LDADDL_64_memop">64-bit LDADDL alias</a>
  AMED_AARCH64_ENCODING_STADDB_LDADDB_32_memop, //!< <a href="../target/aarch64/STADDB_LDADDB.html#STADDB_LDADDB_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STADDLB_LDADDLB_32_memop, //!< <a href="../target/aarch64/STADDB_LDADDB.html#STADDLB_LDADDLB_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STADDH_LDADDH_32_memop, //!< <a href="../target/aarch64/STADDH_LDADDH.html#STADDH_LDADDH_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STADDLH_LDADDLH_32_memop, //!< <a href="../target/aarch64/STADDH_LDADDH.html#STADDLH_LDADDLH_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STCLR_LDCLR_32_memop, //!< <a href="../target/aarch64/STCLR_LDCLR.html#STCLR_LDCLR_32_memop">32-bit LDCLR alias</a>
  AMED_AARCH64_ENCODING_STCLRL_LDCLRL_32_memop, //!< <a href="../target/aarch64/STCLR_LDCLR.html#STCLRL_LDCLRL_32_memop">32-bit LDCLRL alias</a>
  AMED_AARCH64_ENCODING_STCLR_LDCLR_64_memop, //!< <a href="../target/aarch64/STCLR_LDCLR.html#STCLR_LDCLR_64_memop">64-bit LDCLR alias</a>
  AMED_AARCH64_ENCODING_STCLRL_LDCLRL_64_memop, //!< <a href="../target/aarch64/STCLR_LDCLR.html#STCLRL_LDCLRL_64_memop">64-bit LDCLRL alias</a>
  AMED_AARCH64_ENCODING_STCLRB_LDCLRB_32_memop, //!< <a href="../target/aarch64/STCLRB_LDCLRB.html#STCLRB_LDCLRB_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STCLRLB_LDCLRLB_32_memop, //!< <a href="../target/aarch64/STCLRB_LDCLRB.html#STCLRLB_LDCLRLB_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STCLRH_LDCLRH_32_memop, //!< <a href="../target/aarch64/STCLRH_LDCLRH.html#STCLRH_LDCLRH_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STCLRLH_LDCLRLH_32_memop, //!< <a href="../target/aarch64/STCLRH_LDCLRH.html#STCLRLH_LDCLRLH_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STEOR_LDEOR_32_memop, //!< <a href="../target/aarch64/STEOR_LDEOR.html#STEOR_LDEOR_32_memop">32-bit LDEOR alias</a>
  AMED_AARCH64_ENCODING_STEORL_LDEORL_32_memop, //!< <a href="../target/aarch64/STEOR_LDEOR.html#STEORL_LDEORL_32_memop">32-bit LDEORL alias</a>
  AMED_AARCH64_ENCODING_STEOR_LDEOR_64_memop, //!< <a href="../target/aarch64/STEOR_LDEOR.html#STEOR_LDEOR_64_memop">64-bit LDEOR alias</a>
  AMED_AARCH64_ENCODING_STEORL_LDEORL_64_memop, //!< <a href="../target/aarch64/STEOR_LDEOR.html#STEORL_LDEORL_64_memop">64-bit LDEORL alias</a>
  AMED_AARCH64_ENCODING_STEORB_LDEORB_32_memop, //!< <a href="../target/aarch64/STEORB_LDEORB.html#STEORB_LDEORB_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STEORLB_LDEORLB_32_memop, //!< <a href="../target/aarch64/STEORB_LDEORB.html#STEORLB_LDEORLB_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STEORH_LDEORH_32_memop, //!< <a href="../target/aarch64/STEORH_LDEORH.html#STEORH_LDEORH_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STEORLH_LDEORLH_32_memop, //!< <a href="../target/aarch64/STEORH_LDEORH.html#STEORLH_LDEORLH_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STSET_LDSET_32_memop, //!< <a href="../target/aarch64/STSET_LDSET.html#STSET_LDSET_32_memop">32-bit LDSET alias</a>
  AMED_AARCH64_ENCODING_STSETL_LDSETL_32_memop, //!< <a href="../target/aarch64/STSET_LDSET.html#STSETL_LDSETL_32_memop">32-bit LDSETL alias</a>
  AMED_AARCH64_ENCODING_STSET_LDSET_64_memop, //!< <a href="../target/aarch64/STSET_LDSET.html#STSET_LDSET_64_memop">64-bit LDSET alias</a>
  AMED_AARCH64_ENCODING_STSETL_LDSETL_64_memop, //!< <a href="../target/aarch64/STSET_LDSET.html#STSETL_LDSETL_64_memop">64-bit LDSETL alias</a>
  AMED_AARCH64_ENCODING_STSETB_LDSETB_32_memop, //!< <a href="../target/aarch64/STSETB_LDSETB.html#STSETB_LDSETB_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STSETLB_LDSETLB_32_memop, //!< <a href="../target/aarch64/STSETB_LDSETB.html#STSETLB_LDSETLB_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STSETH_LDSETH_32_memop, //!< <a href="../target/aarch64/STSETH_LDSETH.html#STSETH_LDSETH_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STSETLH_LDSETLH_32_memop, //!< <a href="../target/aarch64/STSETH_LDSETH.html#STSETLH_LDSETLH_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STSMAX_LDSMAX_32_memop, //!< <a href="../target/aarch64/STSMAX_LDSMAX.html#STSMAX_LDSMAX_32_memop">32-bit LDSMAX alias</a>
  AMED_AARCH64_ENCODING_STSMAXL_LDSMAXL_32_memop, //!< <a href="../target/aarch64/STSMAX_LDSMAX.html#STSMAXL_LDSMAXL_32_memop">32-bit LDSMAXL alias</a>
  AMED_AARCH64_ENCODING_STSMAX_LDSMAX_64_memop, //!< <a href="../target/aarch64/STSMAX_LDSMAX.html#STSMAX_LDSMAX_64_memop">64-bit LDSMAX alias</a>
  AMED_AARCH64_ENCODING_STSMAXL_LDSMAXL_64_memop, //!< <a href="../target/aarch64/STSMAX_LDSMAX.html#STSMAXL_LDSMAXL_64_memop">64-bit LDSMAXL alias</a>
  AMED_AARCH64_ENCODING_STSMAXB_LDSMAXB_32_memop, //!< <a href="../target/aarch64/STSMAXB_LDSMAXB.html#STSMAXB_LDSMAXB_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STSMAXLB_LDSMAXLB_32_memop, //!< <a href="../target/aarch64/STSMAXB_LDSMAXB.html#STSMAXLB_LDSMAXLB_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STSMAXH_LDSMAXH_32_memop, //!< <a href="../target/aarch64/STSMAXH_LDSMAXH.html#STSMAXH_LDSMAXH_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STSMAXLH_LDSMAXLH_32_memop, //!< <a href="../target/aarch64/STSMAXH_LDSMAXH.html#STSMAXLH_LDSMAXLH_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STSMIN_LDSMIN_32_memop, //!< <a href="../target/aarch64/STSMIN_LDSMIN.html#STSMIN_LDSMIN_32_memop">32-bit LDSMIN alias</a>
  AMED_AARCH64_ENCODING_STSMINL_LDSMINL_32_memop, //!< <a href="../target/aarch64/STSMIN_LDSMIN.html#STSMINL_LDSMINL_32_memop">32-bit LDSMINL alias</a>
  AMED_AARCH64_ENCODING_STSMIN_LDSMIN_64_memop, //!< <a href="../target/aarch64/STSMIN_LDSMIN.html#STSMIN_LDSMIN_64_memop">64-bit LDSMIN alias</a>
  AMED_AARCH64_ENCODING_STSMINL_LDSMINL_64_memop, //!< <a href="../target/aarch64/STSMIN_LDSMIN.html#STSMINL_LDSMINL_64_memop">64-bit LDSMINL alias</a>
  AMED_AARCH64_ENCODING_STSMINB_LDSMINB_32_memop, //!< <a href="../target/aarch64/STSMINB_LDSMINB.html#STSMINB_LDSMINB_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STSMINLB_LDSMINLB_32_memop, //!< <a href="../target/aarch64/STSMINB_LDSMINB.html#STSMINLB_LDSMINLB_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STSMINH_LDSMINH_32_memop, //!< <a href="../target/aarch64/STSMINH_LDSMINH.html#STSMINH_LDSMINH_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STSMINLH_LDSMINLH_32_memop, //!< <a href="../target/aarch64/STSMINH_LDSMINH.html#STSMINLH_LDSMINLH_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STUMAX_LDUMAX_32_memop, //!< <a href="../target/aarch64/STUMAX_LDUMAX.html#STUMAX_LDUMAX_32_memop">32-bit LDUMAX alias</a>
  AMED_AARCH64_ENCODING_STUMAXL_LDUMAXL_32_memop, //!< <a href="../target/aarch64/STUMAX_LDUMAX.html#STUMAXL_LDUMAXL_32_memop">32-bit LDUMAXL alias</a>
  AMED_AARCH64_ENCODING_STUMAX_LDUMAX_64_memop, //!< <a href="../target/aarch64/STUMAX_LDUMAX.html#STUMAX_LDUMAX_64_memop">64-bit LDUMAX alias</a>
  AMED_AARCH64_ENCODING_STUMAXL_LDUMAXL_64_memop, //!< <a href="../target/aarch64/STUMAX_LDUMAX.html#STUMAXL_LDUMAXL_64_memop">64-bit LDUMAXL alias</a>
  AMED_AARCH64_ENCODING_STUMAXB_LDUMAXB_32_memop, //!< <a href="../target/aarch64/STUMAXB_LDUMAXB.html#STUMAXB_LDUMAXB_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STUMAXLB_LDUMAXLB_32_memop, //!< <a href="../target/aarch64/STUMAXB_LDUMAXB.html#STUMAXLB_LDUMAXLB_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STUMAXH_LDUMAXH_32_memop, //!< <a href="../target/aarch64/STUMAXH_LDUMAXH.html#STUMAXH_LDUMAXH_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STUMAXLH_LDUMAXLH_32_memop, //!< <a href="../target/aarch64/STUMAXH_LDUMAXH.html#STUMAXLH_LDUMAXLH_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STUMIN_LDUMIN_32_memop, //!< <a href="../target/aarch64/STUMIN_LDUMIN.html#STUMIN_LDUMIN_32_memop">32-bit LDUMIN alias</a>
  AMED_AARCH64_ENCODING_STUMINL_LDUMINL_32_memop, //!< <a href="../target/aarch64/STUMIN_LDUMIN.html#STUMINL_LDUMINL_32_memop">32-bit LDUMINL alias</a>
  AMED_AARCH64_ENCODING_STUMIN_LDUMIN_64_memop, //!< <a href="../target/aarch64/STUMIN_LDUMIN.html#STUMIN_LDUMIN_64_memop">64-bit LDUMIN alias</a>
  AMED_AARCH64_ENCODING_STUMINL_LDUMINL_64_memop, //!< <a href="../target/aarch64/STUMIN_LDUMIN.html#STUMINL_LDUMINL_64_memop">64-bit LDUMINL alias</a>
  AMED_AARCH64_ENCODING_STUMINB_LDUMINB_32_memop, //!< <a href="../target/aarch64/STUMINB_LDUMINB.html#STUMINB_LDUMINB_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STUMINLB_LDUMINLB_32_memop, //!< <a href="../target/aarch64/STUMINB_LDUMINB.html#STUMINLB_LDUMINLB_32_memop">Release</a>
  AMED_AARCH64_ENCODING_STUMINH_LDUMINH_32_memop, //!< <a href="../target/aarch64/STUMINH_LDUMINH.html#STUMINH_LDUMINH_32_memop">No memory ordering</a>
  AMED_AARCH64_ENCODING_STUMINLH_LDUMINLH_32_memop, //!< <a href="../target/aarch64/STUMINH_LDUMINH.html#STUMINLH_LDUMINLH_32_memop">Release</a>
  AMED_AARCH64_ENCODING_SXTB_SBFM_32M_bitfield, //!< <a href="../target/aarch64/SXTB_SBFM.html#SXTB_SBFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_SXTB_SBFM_64M_bitfield, //!< <a href="../target/aarch64/SXTB_SBFM.html#SXTB_SBFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_SXTH_SBFM_32M_bitfield, //!< <a href="../target/aarch64/SXTH_SBFM.html#SXTH_SBFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_SXTH_SBFM_64M_bitfield, //!< <a href="../target/aarch64/SXTH_SBFM.html#SXTH_SBFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_SXTW_SBFM_64M_bitfield, //!< <a href="../target/aarch64/SXTW_SBFM.html#SXTW_SBFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_TLBI_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/TLBI_SYS.html#TLBI_SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_ENCODING_TST_ANDS_32S_log_imm, //!< <a href="../target/aarch64/TST_ANDS_log_imm.html#TST_ANDS_32S_log_imm">32-bit</a>
  AMED_AARCH64_ENCODING_TST_ANDS_64S_log_imm, //!< <a href="../target/aarch64/TST_ANDS_log_imm.html#TST_ANDS_64S_log_imm">64-bit</a>
  AMED_AARCH64_ENCODING_TST_ANDS_32_log_shift, //!< <a href="../target/aarch64/TST_ANDS_log_shift.html#TST_ANDS_32_log_shift">32-bit</a>
  AMED_AARCH64_ENCODING_TST_ANDS_64_log_shift, //!< <a href="../target/aarch64/TST_ANDS_log_shift.html#TST_ANDS_64_log_shift">64-bit</a>
  AMED_AARCH64_ENCODING_UBFIZ_UBFM_32M_bitfield, //!< <a href="../target/aarch64/UBFIZ_UBFM.html#UBFIZ_UBFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_UBFIZ_UBFM_64M_bitfield, //!< <a href="../target/aarch64/UBFIZ_UBFM.html#UBFIZ_UBFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_UBFX_UBFM_32M_bitfield, //!< <a href="../target/aarch64/UBFX_UBFM.html#UBFX_UBFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_UBFX_UBFM_64M_bitfield, //!< <a href="../target/aarch64/UBFX_UBFM.html#UBFX_UBFM_64M_bitfield">64-bit</a>
  AMED_AARCH64_ENCODING_UMNEGL_UMSUBL_64WA_dp_3src, //!< <a href="../target/aarch64/UMNEGL_UMSUBL.html#UMNEGL_UMSUBL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_UMULL_UMADDL_64WA_dp_3src, //!< <a href="../target/aarch64/UMULL_UMADDL.html#UMULL_UMADDL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_ENCODING_UXTB_UBFM_32M_bitfield, //!< <a href="../target/aarch64/UXTB_UBFM.html#UXTB_UBFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_UXTH_UBFM_32M_bitfield, //!< <a href="../target/aarch64/UXTH_UBFM.html#UXTH_UBFM_32M_bitfield">32-bit</a>
  AMED_AARCH64_ENCODING_ABS_asisdmisc_R, //!< <a href="../target/aarch64/ABS_advsimd.html#ABS_asisdmisc_R">Scalar</a>
  AMED_AARCH64_ENCODING_ABS_asimdmisc_R, //!< <a href="../target/aarch64/ABS_advsimd.html#ABS_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_ADD_asisdsame_only, //!< <a href="../target/aarch64/ADD_advsimd.html#ADD_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_ADD_asimdsame_only, //!< <a href="../target/aarch64/ADD_advsimd.html#ADD_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_ADDHN_asimddiff_N, //!< <a href="../target/aarch64/ADDHN_advsimd.html#ADDHN_asimddiff_N">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_ADDP_asisdpair_only, //!< <a href="../target/aarch64/ADDP_advsimd_pair.html#ADDP_asisdpair_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_ADDP_asimdsame_only, //!< <a href="../target/aarch64/ADDP_advsimd_vec.html#ADDP_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_ADDV_asimdall_only, //!< <a href="../target/aarch64/ADDV_advsimd.html#ADDV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_AESD_B_cryptoaes, //!< <a href="../target/aarch64/AESD_advsimd.html#AESD_B_cryptoaes">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_AESE_B_cryptoaes, //!< <a href="../target/aarch64/AESE_advsimd.html#AESE_B_cryptoaes">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_AESIMC_B_cryptoaes, //!< <a href="../target/aarch64/AESIMC_advsimd.html#AESIMC_B_cryptoaes">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_AESMC_B_cryptoaes, //!< <a href="../target/aarch64/AESMC_advsimd.html#AESMC_B_cryptoaes">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_AND_asimdsame_only, //!< <a href="../target/aarch64/AND_advsimd.html#AND_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_BCAX_VVV16_crypto4, //!< <a href="../target/aarch64/BCAX_advsimd.html#BCAX_VVV16_crypto4">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_BFCVT_BS_floatdp1, //!< <a href="../target/aarch64/BFCVT_float.html#BFCVT_BS_floatdp1">Single-precision to BFloat16</a>
  AMED_AARCH64_ENCODING_BFCVTN_asimdmisc_4S, //!< <a href="../target/aarch64/BFCVTN_advsimd.html#BFCVTN_asimdmisc_4S">Vector single-precision and BFloat16</a>
  AMED_AARCH64_ENCODING_BFDOT_asimdelem_E, //!< <a href="../target/aarch64/BFDOT_advsimd_elt.html#BFDOT_asimdelem_E">Vector</a>
  AMED_AARCH64_ENCODING_BFDOT_asimdsame2_D, //!< <a href="../target/aarch64/BFDOT_advsimd_vec.html#BFDOT_asimdsame2_D">Vector</a>
  AMED_AARCH64_ENCODING_BFMLAL_asimdelem_F, //!< <a href="../target/aarch64/BFMLAL_advsimd_elt.html#BFMLAL_asimdelem_F">Vector</a>
  AMED_AARCH64_ENCODING_BFMLAL_asimdsame2_F_, //!< <a href="../target/aarch64/BFMLAL_advsimd_vec.html#BFMLAL_asimdsame2_F_">Vector</a>
  AMED_AARCH64_ENCODING_BFMMLA_asimdsame2_E, //!< <a href="../target/aarch64/BFMMLA_advsimd.html#BFMMLA_asimdsame2_E">Vector</a>
  AMED_AARCH64_ENCODING_BIC_asimdimm_L_hl, //!< <a href="../target/aarch64/BIC_advsimd_imm.html#BIC_asimdimm_L_hl">16-bit</a>
  AMED_AARCH64_ENCODING_BIC_asimdimm_L_sl, //!< <a href="../target/aarch64/BIC_advsimd_imm.html#BIC_asimdimm_L_sl">32-bit</a>
  AMED_AARCH64_ENCODING_BIC_asimdsame_only, //!< <a href="../target/aarch64/BIC_advsimd_reg.html#BIC_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_BIF_asimdsame_only, //!< <a href="../target/aarch64/BIF_advsimd.html#BIF_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_BIT_asimdsame_only, //!< <a href="../target/aarch64/BIT_advsimd.html#BIT_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_BSL_asimdsame_only, //!< <a href="../target/aarch64/BSL_advsimd.html#BSL_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_CLS_asimdmisc_R, //!< <a href="../target/aarch64/CLS_advsimd.html#CLS_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_CLZ_asimdmisc_R, //!< <a href="../target/aarch64/CLZ_advsimd.html#CLZ_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_CMEQ_asisdsame_only, //!< <a href="../target/aarch64/CMEQ_advsimd_reg.html#CMEQ_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_CMEQ_asimdsame_only, //!< <a href="../target/aarch64/CMEQ_advsimd_reg.html#CMEQ_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_CMEQ_asisdmisc_Z, //!< <a href="../target/aarch64/CMEQ_advsimd_zero.html#CMEQ_asisdmisc_Z">Scalar</a>
  AMED_AARCH64_ENCODING_CMEQ_asimdmisc_Z, //!< <a href="../target/aarch64/CMEQ_advsimd_zero.html#CMEQ_asimdmisc_Z">Vector</a>
  AMED_AARCH64_ENCODING_CMGE_asisdsame_only, //!< <a href="../target/aarch64/CMGE_advsimd_reg.html#CMGE_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_CMGE_asimdsame_only, //!< <a href="../target/aarch64/CMGE_advsimd_reg.html#CMGE_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_CMGE_asisdmisc_Z, //!< <a href="../target/aarch64/CMGE_advsimd_zero.html#CMGE_asisdmisc_Z">Scalar</a>
  AMED_AARCH64_ENCODING_CMGE_asimdmisc_Z, //!< <a href="../target/aarch64/CMGE_advsimd_zero.html#CMGE_asimdmisc_Z">Vector</a>
  AMED_AARCH64_ENCODING_CMGT_asisdsame_only, //!< <a href="../target/aarch64/CMGT_advsimd_reg.html#CMGT_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_CMGT_asimdsame_only, //!< <a href="../target/aarch64/CMGT_advsimd_reg.html#CMGT_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_CMGT_asisdmisc_Z, //!< <a href="../target/aarch64/CMGT_advsimd_zero.html#CMGT_asisdmisc_Z">Scalar</a>
  AMED_AARCH64_ENCODING_CMGT_asimdmisc_Z, //!< <a href="../target/aarch64/CMGT_advsimd_zero.html#CMGT_asimdmisc_Z">Vector</a>
  AMED_AARCH64_ENCODING_CMHI_asisdsame_only, //!< <a href="../target/aarch64/CMHI_advsimd.html#CMHI_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_CMHI_asimdsame_only, //!< <a href="../target/aarch64/CMHI_advsimd.html#CMHI_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_CMHS_asisdsame_only, //!< <a href="../target/aarch64/CMHS_advsimd.html#CMHS_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_CMHS_asimdsame_only, //!< <a href="../target/aarch64/CMHS_advsimd.html#CMHS_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_CMLE_asisdmisc_Z, //!< <a href="../target/aarch64/CMLE_advsimd.html#CMLE_asisdmisc_Z">Scalar</a>
  AMED_AARCH64_ENCODING_CMLE_asimdmisc_Z, //!< <a href="../target/aarch64/CMLE_advsimd.html#CMLE_asimdmisc_Z">Vector</a>
  AMED_AARCH64_ENCODING_CMLT_asisdmisc_Z, //!< <a href="../target/aarch64/CMLT_advsimd.html#CMLT_asisdmisc_Z">Scalar</a>
  AMED_AARCH64_ENCODING_CMLT_asimdmisc_Z, //!< <a href="../target/aarch64/CMLT_advsimd.html#CMLT_asimdmisc_Z">Vector</a>
  AMED_AARCH64_ENCODING_CMTST_asisdsame_only, //!< <a href="../target/aarch64/CMTST_advsimd.html#CMTST_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_CMTST_asimdsame_only, //!< <a href="../target/aarch64/CMTST_advsimd.html#CMTST_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_CNT_asimdmisc_R, //!< <a href="../target/aarch64/CNT_advsimd.html#CNT_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_DUP_asisdone_only, //!< <a href="../target/aarch64/DUP_advsimd_elt.html#DUP_asisdone_only">Scalar</a>
  AMED_AARCH64_ENCODING_DUP_asimdins_DV_v, //!< <a href="../target/aarch64/DUP_advsimd_elt.html#DUP_asimdins_DV_v">Vector</a>
  AMED_AARCH64_ENCODING_DUP_asimdins_DR_r, //!< <a href="../target/aarch64/DUP_advsimd_gen.html#DUP_asimdins_DR_r">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_EOR3_VVV16_crypto4, //!< <a href="../target/aarch64/EOR3_advsimd.html#EOR3_VVV16_crypto4">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_EOR_asimdsame_only, //!< <a href="../target/aarch64/EOR_advsimd.html#EOR_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_EXT_asimdext_only, //!< <a href="../target/aarch64/EXT_advsimd.html#EXT_asimdext_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_FABD_asisdsamefp16_only, //!< <a href="../target/aarch64/FABD_advsimd.html#FABD_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FABD_asisdsame_only, //!< <a href="../target/aarch64/FABD_advsimd.html#FABD_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FABD_asimdsamefp16_only, //!< <a href="../target/aarch64/FABD_advsimd.html#FABD_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_ENCODING_FABD_asimdsame_only, //!< <a href="../target/aarch64/FABD_advsimd.html#FABD_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FABS_asimdmiscfp16_R, //!< <a href="../target/aarch64/FABS_advsimd.html#FABS_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_ENCODING_FABS_asimdmisc_R, //!< <a href="../target/aarch64/FABS_advsimd.html#FABS_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FABS_H_floatdp1, //!< <a href="../target/aarch64/FABS_float.html#FABS_H_floatdp1">Half-precision</a>
  AMED_AARCH64_ENCODING_FABS_S_floatdp1, //!< <a href="../target/aarch64/FABS_float.html#FABS_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FABS_D_floatdp1, //!< <a href="../target/aarch64/FABS_float.html#FABS_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FACGE_asisdsamefp16_only, //!< <a href="../target/aarch64/FACGE_advsimd.html#FACGE_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FACGE_asisdsame_only, //!< <a href="../target/aarch64/FACGE_advsimd.html#FACGE_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FACGE_asimdsamefp16_only, //!< <a href="../target/aarch64/FACGE_advsimd.html#FACGE_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_ENCODING_FACGE_asimdsame_only, //!< <a href="../target/aarch64/FACGE_advsimd.html#FACGE_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FACGT_asisdsamefp16_only, //!< <a href="../target/aarch64/FACGT_advsimd.html#FACGT_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FACGT_asisdsame_only, //!< <a href="../target/aarch64/FACGT_advsimd.html#FACGT_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FACGT_asimdsamefp16_only, //!< <a href="../target/aarch64/FACGT_advsimd.html#FACGT_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_ENCODING_FACGT_asimdsame_only, //!< <a href="../target/aarch64/FACGT_advsimd.html#FACGT_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FADD_asimdsamefp16_only, //!< <a href="../target/aarch64/FADD_advsimd.html#FADD_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FADD_asimdsame_only, //!< <a href="../target/aarch64/FADD_advsimd.html#FADD_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FADD_H_floatdp2, //!< <a href="../target/aarch64/FADD_float.html#FADD_H_floatdp2">Half-precision</a>
  AMED_AARCH64_ENCODING_FADD_S_floatdp2, //!< <a href="../target/aarch64/FADD_float.html#FADD_S_floatdp2">Single-precision</a>
  AMED_AARCH64_ENCODING_FADD_D_floatdp2, //!< <a href="../target/aarch64/FADD_float.html#FADD_D_floatdp2">Double-precision</a>
  AMED_AARCH64_ENCODING_FADDP_asisdpair_only_H, //!< <a href="../target/aarch64/FADDP_advsimd_pair.html#FADDP_asisdpair_only_H">Half-precision</a>
  AMED_AARCH64_ENCODING_FADDP_asisdpair_only_SD, //!< <a href="../target/aarch64/FADDP_advsimd_pair.html#FADDP_asisdpair_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FADDP_asimdsamefp16_only, //!< <a href="../target/aarch64/FADDP_advsimd_vec.html#FADDP_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FADDP_asimdsame_only, //!< <a href="../target/aarch64/FADDP_advsimd_vec.html#FADDP_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCADD_asimdsame2_C, //!< <a href="../target/aarch64/FCADD_advsimd_vec.html#FCADD_asimdsame2_C">Vector</a>
  AMED_AARCH64_ENCODING_FCCMP_H_floatccmp, //!< <a href="../target/aarch64/FCCMP_float.html#FCCMP_H_floatccmp">Half-precision</a>
  AMED_AARCH64_ENCODING_FCCMP_S_floatccmp, //!< <a href="../target/aarch64/FCCMP_float.html#FCCMP_S_floatccmp">Single-precision</a>
  AMED_AARCH64_ENCODING_FCCMP_D_floatccmp, //!< <a href="../target/aarch64/FCCMP_float.html#FCCMP_D_floatccmp">Double-precision</a>
  AMED_AARCH64_ENCODING_FCCMPE_H_floatccmp, //!< <a href="../target/aarch64/FCCMPE_float.html#FCCMPE_H_floatccmp">Half-precision</a>
  AMED_AARCH64_ENCODING_FCCMPE_S_floatccmp, //!< <a href="../target/aarch64/FCCMPE_float.html#FCCMPE_S_floatccmp">Single-precision</a>
  AMED_AARCH64_ENCODING_FCCMPE_D_floatccmp, //!< <a href="../target/aarch64/FCCMPE_float.html#FCCMPE_D_floatccmp">Double-precision</a>
  AMED_AARCH64_ENCODING_FCMEQ_asisdsamefp16_only, //!< <a href="../target/aarch64/FCMEQ_advsimd_reg.html#FCMEQ_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCMEQ_asisdsame_only, //!< <a href="../target/aarch64/FCMEQ_advsimd_reg.html#FCMEQ_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMEQ_asimdsamefp16_only, //!< <a href="../target/aarch64/FCMEQ_advsimd_reg.html#FCMEQ_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCMEQ_asimdsame_only, //!< <a href="../target/aarch64/FCMEQ_advsimd_reg.html#FCMEQ_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMEQ_asisdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMEQ_advsimd_zero.html#FCMEQ_asisdmiscfp16_FZ">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCMEQ_asisdmisc_FZ, //!< <a href="../target/aarch64/FCMEQ_advsimd_zero.html#FCMEQ_asisdmisc_FZ">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMEQ_asimdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMEQ_advsimd_zero.html#FCMEQ_asimdmiscfp16_FZ">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCMEQ_asimdmisc_FZ, //!< <a href="../target/aarch64/FCMEQ_advsimd_zero.html#FCMEQ_asimdmisc_FZ">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMGE_asisdsamefp16_only, //!< <a href="../target/aarch64/FCMGE_advsimd_reg.html#FCMGE_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCMGE_asisdsame_only, //!< <a href="../target/aarch64/FCMGE_advsimd_reg.html#FCMGE_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMGE_asimdsamefp16_only, //!< <a href="../target/aarch64/FCMGE_advsimd_reg.html#FCMGE_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCMGE_asimdsame_only, //!< <a href="../target/aarch64/FCMGE_advsimd_reg.html#FCMGE_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMGE_asisdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMGE_advsimd_zero.html#FCMGE_asisdmiscfp16_FZ">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCMGE_asisdmisc_FZ, //!< <a href="../target/aarch64/FCMGE_advsimd_zero.html#FCMGE_asisdmisc_FZ">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMGE_asimdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMGE_advsimd_zero.html#FCMGE_asimdmiscfp16_FZ">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCMGE_asimdmisc_FZ, //!< <a href="../target/aarch64/FCMGE_advsimd_zero.html#FCMGE_asimdmisc_FZ">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMGT_asisdsamefp16_only, //!< <a href="../target/aarch64/FCMGT_advsimd_reg.html#FCMGT_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCMGT_asisdsame_only, //!< <a href="../target/aarch64/FCMGT_advsimd_reg.html#FCMGT_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMGT_asimdsamefp16_only, //!< <a href="../target/aarch64/FCMGT_advsimd_reg.html#FCMGT_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCMGT_asimdsame_only, //!< <a href="../target/aarch64/FCMGT_advsimd_reg.html#FCMGT_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMGT_asisdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMGT_advsimd_zero.html#FCMGT_asisdmiscfp16_FZ">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCMGT_asisdmisc_FZ, //!< <a href="../target/aarch64/FCMGT_advsimd_zero.html#FCMGT_asisdmisc_FZ">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMGT_asimdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMGT_advsimd_zero.html#FCMGT_asimdmiscfp16_FZ">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCMGT_asimdmisc_FZ, //!< <a href="../target/aarch64/FCMGT_advsimd_zero.html#FCMGT_asimdmisc_FZ">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMLA_asimdelem_C_H, //!< <a href="../target/aarch64/FCMLA_advsimd_elt.html#FCMLA_asimdelem_C_H">FCMLA_asimdelem_C_H</a>
  AMED_AARCH64_ENCODING_FCMLA_asimdelem_C_S, //!< <a href="../target/aarch64/FCMLA_advsimd_elt.html#FCMLA_asimdelem_C_S">FCMLA_asimdelem_C_S</a>
  AMED_AARCH64_ENCODING_FCMLA_asimdsame2_C, //!< <a href="../target/aarch64/FCMLA_advsimd_vec.html#FCMLA_asimdsame2_C">Vector</a>
  AMED_AARCH64_ENCODING_FCMLE_asisdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMLE_advsimd.html#FCMLE_asisdmiscfp16_FZ">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCMLE_asisdmisc_FZ, //!< <a href="../target/aarch64/FCMLE_advsimd.html#FCMLE_asisdmisc_FZ">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMLE_asimdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMLE_advsimd.html#FCMLE_asimdmiscfp16_FZ">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCMLE_asimdmisc_FZ, //!< <a href="../target/aarch64/FCMLE_advsimd.html#FCMLE_asimdmisc_FZ">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMLT_asisdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMLT_advsimd.html#FCMLT_asisdmiscfp16_FZ">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCMLT_asisdmisc_FZ, //!< <a href="../target/aarch64/FCMLT_advsimd.html#FCMLT_asisdmisc_FZ">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMLT_asimdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMLT_advsimd.html#FCMLT_asimdmiscfp16_FZ">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCMLT_asimdmisc_FZ, //!< <a href="../target/aarch64/FCMLT_advsimd.html#FCMLT_asimdmisc_FZ">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCMP_H_floatcmp, //!< <a href="../target/aarch64/FCMP_float.html#FCMP_H_floatcmp">Half-precision</a>
  AMED_AARCH64_ENCODING_FCMP_HZ_floatcmp, //!< <a href="../target/aarch64/FCMP_float.html#FCMP_HZ_floatcmp">Half-precision, zero</a>
  AMED_AARCH64_ENCODING_FCMP_S_floatcmp, //!< <a href="../target/aarch64/FCMP_float.html#FCMP_S_floatcmp">Single-precision</a>
  AMED_AARCH64_ENCODING_FCMP_SZ_floatcmp, //!< <a href="../target/aarch64/FCMP_float.html#FCMP_SZ_floatcmp">Single-precision, zero</a>
  AMED_AARCH64_ENCODING_FCMP_D_floatcmp, //!< <a href="../target/aarch64/FCMP_float.html#FCMP_D_floatcmp">Double-precision</a>
  AMED_AARCH64_ENCODING_FCMP_DZ_floatcmp, //!< <a href="../target/aarch64/FCMP_float.html#FCMP_DZ_floatcmp">Double-precision, zero</a>
  AMED_AARCH64_ENCODING_FCMPE_H_floatcmp, //!< <a href="../target/aarch64/FCMPE_float.html#FCMPE_H_floatcmp">Half-precision</a>
  AMED_AARCH64_ENCODING_FCMPE_HZ_floatcmp, //!< <a href="../target/aarch64/FCMPE_float.html#FCMPE_HZ_floatcmp">Half-precision, zero</a>
  AMED_AARCH64_ENCODING_FCMPE_S_floatcmp, //!< <a href="../target/aarch64/FCMPE_float.html#FCMPE_S_floatcmp">Single-precision</a>
  AMED_AARCH64_ENCODING_FCMPE_SZ_floatcmp, //!< <a href="../target/aarch64/FCMPE_float.html#FCMPE_SZ_floatcmp">Single-precision, zero</a>
  AMED_AARCH64_ENCODING_FCMPE_D_floatcmp, //!< <a href="../target/aarch64/FCMPE_float.html#FCMPE_D_floatcmp">Double-precision</a>
  AMED_AARCH64_ENCODING_FCMPE_DZ_floatcmp, //!< <a href="../target/aarch64/FCMPE_float.html#FCMPE_DZ_floatcmp">Double-precision, zero</a>
  AMED_AARCH64_ENCODING_FCSEL_H_floatsel, //!< <a href="../target/aarch64/FCSEL_float.html#FCSEL_H_floatsel">Half-precision</a>
  AMED_AARCH64_ENCODING_FCSEL_S_floatsel, //!< <a href="../target/aarch64/FCSEL_float.html#FCSEL_S_floatsel">Single-precision</a>
  AMED_AARCH64_ENCODING_FCSEL_D_floatsel, //!< <a href="../target/aarch64/FCSEL_float.html#FCSEL_D_floatsel">Double-precision</a>
  AMED_AARCH64_ENCODING_FCVT_SH_floatdp1, //!< <a href="../target/aarch64/FCVT_float.html#FCVT_SH_floatdp1">Half-precision to single-precision</a>
  AMED_AARCH64_ENCODING_FCVT_DH_floatdp1, //!< <a href="../target/aarch64/FCVT_float.html#FCVT_DH_floatdp1">Half-precision to double-precision</a>
  AMED_AARCH64_ENCODING_FCVT_HS_floatdp1, //!< <a href="../target/aarch64/FCVT_float.html#FCVT_HS_floatdp1">Single-precision to half-precision</a>
  AMED_AARCH64_ENCODING_FCVT_DS_floatdp1, //!< <a href="../target/aarch64/FCVT_float.html#FCVT_DS_floatdp1">Single-precision to double-precision</a>
  AMED_AARCH64_ENCODING_FCVT_HD_floatdp1, //!< <a href="../target/aarch64/FCVT_float.html#FCVT_HD_floatdp1">Double-precision to half-precision</a>
  AMED_AARCH64_ENCODING_FCVT_SD_floatdp1, //!< <a href="../target/aarch64/FCVT_float.html#FCVT_SD_floatdp1">Double-precision to single-precision</a>
  AMED_AARCH64_ENCODING_FCVTAS_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTAS_advsimd.html#FCVTAS_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCVTAS_asisdmisc_R, //!< <a href="../target/aarch64/FCVTAS_advsimd.html#FCVTAS_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTAS_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTAS_advsimd.html#FCVTAS_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCVTAS_asimdmisc_R, //!< <a href="../target/aarch64/FCVTAS_advsimd.html#FCVTAS_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTAS_32H_float2int, //!< <a href="../target/aarch64/FCVTAS_float.html#FCVTAS_32H_float2int">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTAS_64H_float2int, //!< <a href="../target/aarch64/FCVTAS_float.html#FCVTAS_64H_float2int">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTAS_32S_float2int, //!< <a href="../target/aarch64/FCVTAS_float.html#FCVTAS_32S_float2int">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTAS_64S_float2int, //!< <a href="../target/aarch64/FCVTAS_float.html#FCVTAS_64S_float2int">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTAS_32D_float2int, //!< <a href="../target/aarch64/FCVTAS_float.html#FCVTAS_32D_float2int">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTAS_64D_float2int, //!< <a href="../target/aarch64/FCVTAS_float.html#FCVTAS_64D_float2int">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTAU_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTAU_advsimd.html#FCVTAU_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCVTAU_asisdmisc_R, //!< <a href="../target/aarch64/FCVTAU_advsimd.html#FCVTAU_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTAU_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTAU_advsimd.html#FCVTAU_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCVTAU_asimdmisc_R, //!< <a href="../target/aarch64/FCVTAU_advsimd.html#FCVTAU_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTAU_32H_float2int, //!< <a href="../target/aarch64/FCVTAU_float.html#FCVTAU_32H_float2int">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTAU_64H_float2int, //!< <a href="../target/aarch64/FCVTAU_float.html#FCVTAU_64H_float2int">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTAU_32S_float2int, //!< <a href="../target/aarch64/FCVTAU_float.html#FCVTAU_32S_float2int">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTAU_64S_float2int, //!< <a href="../target/aarch64/FCVTAU_float.html#FCVTAU_64S_float2int">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTAU_32D_float2int, //!< <a href="../target/aarch64/FCVTAU_float.html#FCVTAU_32D_float2int">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTAU_64D_float2int, //!< <a href="../target/aarch64/FCVTAU_float.html#FCVTAU_64D_float2int">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTL_asimdmisc_L, //!< <a href="../target/aarch64/FCVTL_advsimd.html#FCVTL_asimdmisc_L">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTMS_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTMS_advsimd.html#FCVTMS_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCVTMS_asisdmisc_R, //!< <a href="../target/aarch64/FCVTMS_advsimd.html#FCVTMS_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTMS_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTMS_advsimd.html#FCVTMS_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCVTMS_asimdmisc_R, //!< <a href="../target/aarch64/FCVTMS_advsimd.html#FCVTMS_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTMS_32H_float2int, //!< <a href="../target/aarch64/FCVTMS_float.html#FCVTMS_32H_float2int">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTMS_64H_float2int, //!< <a href="../target/aarch64/FCVTMS_float.html#FCVTMS_64H_float2int">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTMS_32S_float2int, //!< <a href="../target/aarch64/FCVTMS_float.html#FCVTMS_32S_float2int">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTMS_64S_float2int, //!< <a href="../target/aarch64/FCVTMS_float.html#FCVTMS_64S_float2int">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTMS_32D_float2int, //!< <a href="../target/aarch64/FCVTMS_float.html#FCVTMS_32D_float2int">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTMS_64D_float2int, //!< <a href="../target/aarch64/FCVTMS_float.html#FCVTMS_64D_float2int">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTMU_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTMU_advsimd.html#FCVTMU_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCVTMU_asisdmisc_R, //!< <a href="../target/aarch64/FCVTMU_advsimd.html#FCVTMU_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTMU_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTMU_advsimd.html#FCVTMU_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCVTMU_asimdmisc_R, //!< <a href="../target/aarch64/FCVTMU_advsimd.html#FCVTMU_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTMU_32H_float2int, //!< <a href="../target/aarch64/FCVTMU_float.html#FCVTMU_32H_float2int">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTMU_64H_float2int, //!< <a href="../target/aarch64/FCVTMU_float.html#FCVTMU_64H_float2int">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTMU_32S_float2int, //!< <a href="../target/aarch64/FCVTMU_float.html#FCVTMU_32S_float2int">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTMU_64S_float2int, //!< <a href="../target/aarch64/FCVTMU_float.html#FCVTMU_64S_float2int">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTMU_32D_float2int, //!< <a href="../target/aarch64/FCVTMU_float.html#FCVTMU_32D_float2int">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTMU_64D_float2int, //!< <a href="../target/aarch64/FCVTMU_float.html#FCVTMU_64D_float2int">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTN_asimdmisc_N, //!< <a href="../target/aarch64/FCVTN_advsimd.html#FCVTN_asimdmisc_N">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTNS_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTNS_advsimd.html#FCVTNS_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCVTNS_asisdmisc_R, //!< <a href="../target/aarch64/FCVTNS_advsimd.html#FCVTNS_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTNS_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTNS_advsimd.html#FCVTNS_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCVTNS_asimdmisc_R, //!< <a href="../target/aarch64/FCVTNS_advsimd.html#FCVTNS_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTNS_32H_float2int, //!< <a href="../target/aarch64/FCVTNS_float.html#FCVTNS_32H_float2int">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTNS_64H_float2int, //!< <a href="../target/aarch64/FCVTNS_float.html#FCVTNS_64H_float2int">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTNS_32S_float2int, //!< <a href="../target/aarch64/FCVTNS_float.html#FCVTNS_32S_float2int">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTNS_64S_float2int, //!< <a href="../target/aarch64/FCVTNS_float.html#FCVTNS_64S_float2int">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTNS_32D_float2int, //!< <a href="../target/aarch64/FCVTNS_float.html#FCVTNS_32D_float2int">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTNS_64D_float2int, //!< <a href="../target/aarch64/FCVTNS_float.html#FCVTNS_64D_float2int">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTNU_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTNU_advsimd.html#FCVTNU_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCVTNU_asisdmisc_R, //!< <a href="../target/aarch64/FCVTNU_advsimd.html#FCVTNU_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTNU_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTNU_advsimd.html#FCVTNU_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCVTNU_asimdmisc_R, //!< <a href="../target/aarch64/FCVTNU_advsimd.html#FCVTNU_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTNU_32H_float2int, //!< <a href="../target/aarch64/FCVTNU_float.html#FCVTNU_32H_float2int">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTNU_64H_float2int, //!< <a href="../target/aarch64/FCVTNU_float.html#FCVTNU_64H_float2int">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTNU_32S_float2int, //!< <a href="../target/aarch64/FCVTNU_float.html#FCVTNU_32S_float2int">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTNU_64S_float2int, //!< <a href="../target/aarch64/FCVTNU_float.html#FCVTNU_64S_float2int">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTNU_32D_float2int, //!< <a href="../target/aarch64/FCVTNU_float.html#FCVTNU_32D_float2int">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTNU_64D_float2int, //!< <a href="../target/aarch64/FCVTNU_float.html#FCVTNU_64D_float2int">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTPS_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTPS_advsimd.html#FCVTPS_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCVTPS_asisdmisc_R, //!< <a href="../target/aarch64/FCVTPS_advsimd.html#FCVTPS_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTPS_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTPS_advsimd.html#FCVTPS_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCVTPS_asimdmisc_R, //!< <a href="../target/aarch64/FCVTPS_advsimd.html#FCVTPS_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTPS_32H_float2int, //!< <a href="../target/aarch64/FCVTPS_float.html#FCVTPS_32H_float2int">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTPS_64H_float2int, //!< <a href="../target/aarch64/FCVTPS_float.html#FCVTPS_64H_float2int">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTPS_32S_float2int, //!< <a href="../target/aarch64/FCVTPS_float.html#FCVTPS_32S_float2int">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTPS_64S_float2int, //!< <a href="../target/aarch64/FCVTPS_float.html#FCVTPS_64S_float2int">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTPS_32D_float2int, //!< <a href="../target/aarch64/FCVTPS_float.html#FCVTPS_32D_float2int">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTPS_64D_float2int, //!< <a href="../target/aarch64/FCVTPS_float.html#FCVTPS_64D_float2int">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTPU_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTPU_advsimd.html#FCVTPU_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCVTPU_asisdmisc_R, //!< <a href="../target/aarch64/FCVTPU_advsimd.html#FCVTPU_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTPU_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTPU_advsimd.html#FCVTPU_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCVTPU_asimdmisc_R, //!< <a href="../target/aarch64/FCVTPU_advsimd.html#FCVTPU_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTPU_32H_float2int, //!< <a href="../target/aarch64/FCVTPU_float.html#FCVTPU_32H_float2int">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTPU_64H_float2int, //!< <a href="../target/aarch64/FCVTPU_float.html#FCVTPU_64H_float2int">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTPU_32S_float2int, //!< <a href="../target/aarch64/FCVTPU_float.html#FCVTPU_32S_float2int">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTPU_64S_float2int, //!< <a href="../target/aarch64/FCVTPU_float.html#FCVTPU_64S_float2int">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTPU_32D_float2int, //!< <a href="../target/aarch64/FCVTPU_float.html#FCVTPU_32D_float2int">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTPU_64D_float2int, //!< <a href="../target/aarch64/FCVTPU_float.html#FCVTPU_64D_float2int">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTXN_asisdmisc_N, //!< <a href="../target/aarch64/FCVTXN_advsimd.html#FCVTXN_asisdmisc_N">Scalar</a>
  AMED_AARCH64_ENCODING_FCVTXN_asimdmisc_N, //!< <a href="../target/aarch64/FCVTXN_advsimd.html#FCVTXN_asimdmisc_N">Vector</a>
  AMED_AARCH64_ENCODING_FCVTZS_asisdshf_C, //!< <a href="../target/aarch64/FCVTZS_advsimd_fix.html#FCVTZS_asisdshf_C">Scalar</a>
  AMED_AARCH64_ENCODING_FCVTZS_asimdshf_C, //!< <a href="../target/aarch64/FCVTZS_advsimd_fix.html#FCVTZS_asimdshf_C">Vector</a>
  AMED_AARCH64_ENCODING_FCVTZS_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTZS_advsimd_int.html#FCVTZS_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCVTZS_asisdmisc_R, //!< <a href="../target/aarch64/FCVTZS_advsimd_int.html#FCVTZS_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTZS_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTZS_advsimd_int.html#FCVTZS_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCVTZS_asimdmisc_R, //!< <a href="../target/aarch64/FCVTZS_advsimd_int.html#FCVTZS_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTZS_32H_float2fix, //!< <a href="../target/aarch64/FCVTZS_float_fix.html#FCVTZS_32H_float2fix">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTZS_64H_float2fix, //!< <a href="../target/aarch64/FCVTZS_float_fix.html#FCVTZS_64H_float2fix">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTZS_32S_float2fix, //!< <a href="../target/aarch64/FCVTZS_float_fix.html#FCVTZS_32S_float2fix">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTZS_64S_float2fix, //!< <a href="../target/aarch64/FCVTZS_float_fix.html#FCVTZS_64S_float2fix">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTZS_32D_float2fix, //!< <a href="../target/aarch64/FCVTZS_float_fix.html#FCVTZS_32D_float2fix">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTZS_64D_float2fix, //!< <a href="../target/aarch64/FCVTZS_float_fix.html#FCVTZS_64D_float2fix">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTZS_32H_float2int, //!< <a href="../target/aarch64/FCVTZS_float_int.html#FCVTZS_32H_float2int">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTZS_64H_float2int, //!< <a href="../target/aarch64/FCVTZS_float_int.html#FCVTZS_64H_float2int">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTZS_32S_float2int, //!< <a href="../target/aarch64/FCVTZS_float_int.html#FCVTZS_32S_float2int">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTZS_64S_float2int, //!< <a href="../target/aarch64/FCVTZS_float_int.html#FCVTZS_64S_float2int">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTZS_32D_float2int, //!< <a href="../target/aarch64/FCVTZS_float_int.html#FCVTZS_32D_float2int">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTZS_64D_float2int, //!< <a href="../target/aarch64/FCVTZS_float_int.html#FCVTZS_64D_float2int">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTZU_asisdshf_C, //!< <a href="../target/aarch64/FCVTZU_advsimd_fix.html#FCVTZU_asisdshf_C">Scalar</a>
  AMED_AARCH64_ENCODING_FCVTZU_asimdshf_C, //!< <a href="../target/aarch64/FCVTZU_advsimd_fix.html#FCVTZU_asimdshf_C">Vector</a>
  AMED_AARCH64_ENCODING_FCVTZU_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTZU_advsimd_int.html#FCVTZU_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FCVTZU_asisdmisc_R, //!< <a href="../target/aarch64/FCVTZU_advsimd_int.html#FCVTZU_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTZU_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTZU_advsimd_int.html#FCVTZU_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_FCVTZU_asimdmisc_R, //!< <a href="../target/aarch64/FCVTZU_advsimd_int.html#FCVTZU_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FCVTZU_32H_float2fix, //!< <a href="../target/aarch64/FCVTZU_float_fix.html#FCVTZU_32H_float2fix">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTZU_64H_float2fix, //!< <a href="../target/aarch64/FCVTZU_float_fix.html#FCVTZU_64H_float2fix">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTZU_32S_float2fix, //!< <a href="../target/aarch64/FCVTZU_float_fix.html#FCVTZU_32S_float2fix">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTZU_64S_float2fix, //!< <a href="../target/aarch64/FCVTZU_float_fix.html#FCVTZU_64S_float2fix">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTZU_32D_float2fix, //!< <a href="../target/aarch64/FCVTZU_float_fix.html#FCVTZU_32D_float2fix">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTZU_64D_float2fix, //!< <a href="../target/aarch64/FCVTZU_float_fix.html#FCVTZU_64D_float2fix">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTZU_32H_float2int, //!< <a href="../target/aarch64/FCVTZU_float_int.html#FCVTZU_32H_float2int">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTZU_64H_float2int, //!< <a href="../target/aarch64/FCVTZU_float_int.html#FCVTZU_64H_float2int">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTZU_32S_float2int, //!< <a href="../target/aarch64/FCVTZU_float_int.html#FCVTZU_32S_float2int">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTZU_64S_float2int, //!< <a href="../target/aarch64/FCVTZU_float_int.html#FCVTZU_64S_float2int">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FCVTZU_32D_float2int, //!< <a href="../target/aarch64/FCVTZU_float_int.html#FCVTZU_32D_float2int">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FCVTZU_64D_float2int, //!< <a href="../target/aarch64/FCVTZU_float_int.html#FCVTZU_64D_float2int">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FDIV_asimdsamefp16_only, //!< <a href="../target/aarch64/FDIV_advsimd.html#FDIV_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FDIV_asimdsame_only, //!< <a href="../target/aarch64/FDIV_advsimd.html#FDIV_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FDIV_H_floatdp2, //!< <a href="../target/aarch64/FDIV_float.html#FDIV_H_floatdp2">Half-precision</a>
  AMED_AARCH64_ENCODING_FDIV_S_floatdp2, //!< <a href="../target/aarch64/FDIV_float.html#FDIV_S_floatdp2">Single-precision</a>
  AMED_AARCH64_ENCODING_FDIV_D_floatdp2, //!< <a href="../target/aarch64/FDIV_float.html#FDIV_D_floatdp2">Double-precision</a>
  AMED_AARCH64_ENCODING_FJCVTZS_32D_float2int, //!< <a href="../target/aarch64/FJCVTZS.html#FJCVTZS_32D_float2int">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FMADD_H_floatdp3, //!< <a href="../target/aarch64/FMADD_float.html#FMADD_H_floatdp3">Half-precision</a>
  AMED_AARCH64_ENCODING_FMADD_S_floatdp3, //!< <a href="../target/aarch64/FMADD_float.html#FMADD_S_floatdp3">Single-precision</a>
  AMED_AARCH64_ENCODING_FMADD_D_floatdp3, //!< <a href="../target/aarch64/FMADD_float.html#FMADD_D_floatdp3">Double-precision</a>
  AMED_AARCH64_ENCODING_FMAX_asimdsamefp16_only, //!< <a href="../target/aarch64/FMAX_advsimd.html#FMAX_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FMAX_asimdsame_only, //!< <a href="../target/aarch64/FMAX_advsimd.html#FMAX_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMAX_H_floatdp2, //!< <a href="../target/aarch64/FMAX_float.html#FMAX_H_floatdp2">Half-precision</a>
  AMED_AARCH64_ENCODING_FMAX_S_floatdp2, //!< <a href="../target/aarch64/FMAX_float.html#FMAX_S_floatdp2">Single-precision</a>
  AMED_AARCH64_ENCODING_FMAX_D_floatdp2, //!< <a href="../target/aarch64/FMAX_float.html#FMAX_D_floatdp2">Double-precision</a>
  AMED_AARCH64_ENCODING_FMAXNM_asimdsamefp16_only, //!< <a href="../target/aarch64/FMAXNM_advsimd.html#FMAXNM_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FMAXNM_asimdsame_only, //!< <a href="../target/aarch64/FMAXNM_advsimd.html#FMAXNM_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMAXNM_H_floatdp2, //!< <a href="../target/aarch64/FMAXNM_float.html#FMAXNM_H_floatdp2">Half-precision</a>
  AMED_AARCH64_ENCODING_FMAXNM_S_floatdp2, //!< <a href="../target/aarch64/FMAXNM_float.html#FMAXNM_S_floatdp2">Single-precision</a>
  AMED_AARCH64_ENCODING_FMAXNM_D_floatdp2, //!< <a href="../target/aarch64/FMAXNM_float.html#FMAXNM_D_floatdp2">Double-precision</a>
  AMED_AARCH64_ENCODING_FMAXNMP_asisdpair_only_H, //!< <a href="../target/aarch64/FMAXNMP_advsimd_pair.html#FMAXNMP_asisdpair_only_H">Half-precision</a>
  AMED_AARCH64_ENCODING_FMAXNMP_asisdpair_only_SD, //!< <a href="../target/aarch64/FMAXNMP_advsimd_pair.html#FMAXNMP_asisdpair_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMAXNMP_asimdsamefp16_only, //!< <a href="../target/aarch64/FMAXNMP_advsimd_vec.html#FMAXNMP_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FMAXNMP_asimdsame_only, //!< <a href="../target/aarch64/FMAXNMP_advsimd_vec.html#FMAXNMP_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMAXNMV_asimdall_only_H, //!< <a href="../target/aarch64/FMAXNMV_advsimd.html#FMAXNMV_asimdall_only_H">Half-precision</a>
  AMED_AARCH64_ENCODING_FMAXNMV_asimdall_only_SD, //!< <a href="../target/aarch64/FMAXNMV_advsimd.html#FMAXNMV_asimdall_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMAXP_asisdpair_only_H, //!< <a href="../target/aarch64/FMAXP_advsimd_pair.html#FMAXP_asisdpair_only_H">Half-precision</a>
  AMED_AARCH64_ENCODING_FMAXP_asisdpair_only_SD, //!< <a href="../target/aarch64/FMAXP_advsimd_pair.html#FMAXP_asisdpair_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMAXP_asimdsamefp16_only, //!< <a href="../target/aarch64/FMAXP_advsimd_vec.html#FMAXP_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FMAXP_asimdsame_only, //!< <a href="../target/aarch64/FMAXP_advsimd_vec.html#FMAXP_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMAXV_asimdall_only_H, //!< <a href="../target/aarch64/FMAXV_advsimd.html#FMAXV_asimdall_only_H">Half-precision</a>
  AMED_AARCH64_ENCODING_FMAXV_asimdall_only_SD, //!< <a href="../target/aarch64/FMAXV_advsimd.html#FMAXV_asimdall_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMIN_asimdsamefp16_only, //!< <a href="../target/aarch64/FMIN_advsimd.html#FMIN_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FMIN_asimdsame_only, //!< <a href="../target/aarch64/FMIN_advsimd.html#FMIN_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMIN_H_floatdp2, //!< <a href="../target/aarch64/FMIN_float.html#FMIN_H_floatdp2">Half-precision</a>
  AMED_AARCH64_ENCODING_FMIN_S_floatdp2, //!< <a href="../target/aarch64/FMIN_float.html#FMIN_S_floatdp2">Single-precision</a>
  AMED_AARCH64_ENCODING_FMIN_D_floatdp2, //!< <a href="../target/aarch64/FMIN_float.html#FMIN_D_floatdp2">Double-precision</a>
  AMED_AARCH64_ENCODING_FMINNM_asimdsamefp16_only, //!< <a href="../target/aarch64/FMINNM_advsimd.html#FMINNM_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FMINNM_asimdsame_only, //!< <a href="../target/aarch64/FMINNM_advsimd.html#FMINNM_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMINNM_H_floatdp2, //!< <a href="../target/aarch64/FMINNM_float.html#FMINNM_H_floatdp2">Half-precision</a>
  AMED_AARCH64_ENCODING_FMINNM_S_floatdp2, //!< <a href="../target/aarch64/FMINNM_float.html#FMINNM_S_floatdp2">Single-precision</a>
  AMED_AARCH64_ENCODING_FMINNM_D_floatdp2, //!< <a href="../target/aarch64/FMINNM_float.html#FMINNM_D_floatdp2">Double-precision</a>
  AMED_AARCH64_ENCODING_FMINNMP_asisdpair_only_H, //!< <a href="../target/aarch64/FMINNMP_advsimd_pair.html#FMINNMP_asisdpair_only_H">Half-precision</a>
  AMED_AARCH64_ENCODING_FMINNMP_asisdpair_only_SD, //!< <a href="../target/aarch64/FMINNMP_advsimd_pair.html#FMINNMP_asisdpair_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMINNMP_asimdsamefp16_only, //!< <a href="../target/aarch64/FMINNMP_advsimd_vec.html#FMINNMP_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FMINNMP_asimdsame_only, //!< <a href="../target/aarch64/FMINNMP_advsimd_vec.html#FMINNMP_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMINNMV_asimdall_only_H, //!< <a href="../target/aarch64/FMINNMV_advsimd.html#FMINNMV_asimdall_only_H">Half-precision</a>
  AMED_AARCH64_ENCODING_FMINNMV_asimdall_only_SD, //!< <a href="../target/aarch64/FMINNMV_advsimd.html#FMINNMV_asimdall_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMINP_asisdpair_only_H, //!< <a href="../target/aarch64/FMINP_advsimd_pair.html#FMINP_asisdpair_only_H">Half-precision</a>
  AMED_AARCH64_ENCODING_FMINP_asisdpair_only_SD, //!< <a href="../target/aarch64/FMINP_advsimd_pair.html#FMINP_asisdpair_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMINP_asimdsamefp16_only, //!< <a href="../target/aarch64/FMINP_advsimd_vec.html#FMINP_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FMINP_asimdsame_only, //!< <a href="../target/aarch64/FMINP_advsimd_vec.html#FMINP_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMINV_asimdall_only_H, //!< <a href="../target/aarch64/FMINV_advsimd.html#FMINV_asimdall_only_H">Half-precision</a>
  AMED_AARCH64_ENCODING_FMINV_asimdall_only_SD, //!< <a href="../target/aarch64/FMINV_advsimd.html#FMINV_asimdall_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMLA_asisdelem_RH_H, //!< <a href="../target/aarch64/FMLA_advsimd_elt.html#FMLA_asisdelem_RH_H">Scalar, half-precision</a>
  AMED_AARCH64_ENCODING_FMLA_asisdelem_R_SD, //!< <a href="../target/aarch64/FMLA_advsimd_elt.html#FMLA_asisdelem_R_SD">Scalar, single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMLA_asimdelem_RH_H, //!< <a href="../target/aarch64/FMLA_advsimd_elt.html#FMLA_asimdelem_RH_H">Vector, half-precision</a>
  AMED_AARCH64_ENCODING_FMLA_asimdelem_R_SD, //!< <a href="../target/aarch64/FMLA_advsimd_elt.html#FMLA_asimdelem_R_SD">Vector, single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMLA_asimdsamefp16_only, //!< <a href="../target/aarch64/FMLA_advsimd_vec.html#FMLA_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FMLA_asimdsame_only, //!< <a href="../target/aarch64/FMLA_advsimd_vec.html#FMLA_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMLAL_asimdelem_LH, //!< <a href="../target/aarch64/FMLAL_advsimd_elt.html#FMLAL_asimdelem_LH">FMLAL</a>
  AMED_AARCH64_ENCODING_FMLAL2_asimdelem_LH, //!< <a href="../target/aarch64/FMLAL_advsimd_elt.html#FMLAL2_asimdelem_LH">FMLAL2</a>
  AMED_AARCH64_ENCODING_FMLAL_asimdsame_F, //!< <a href="../target/aarch64/FMLAL_advsimd_vec.html#FMLAL_asimdsame_F">FMLAL</a>
  AMED_AARCH64_ENCODING_FMLAL2_asimdsame_F, //!< <a href="../target/aarch64/FMLAL_advsimd_vec.html#FMLAL2_asimdsame_F">FMLAL2</a>
  AMED_AARCH64_ENCODING_FMLS_asisdelem_RH_H, //!< <a href="../target/aarch64/FMLS_advsimd_elt.html#FMLS_asisdelem_RH_H">Scalar, half-precision</a>
  AMED_AARCH64_ENCODING_FMLS_asisdelem_R_SD, //!< <a href="../target/aarch64/FMLS_advsimd_elt.html#FMLS_asisdelem_R_SD">Scalar, single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMLS_asimdelem_RH_H, //!< <a href="../target/aarch64/FMLS_advsimd_elt.html#FMLS_asimdelem_RH_H">Vector, half-precision</a>
  AMED_AARCH64_ENCODING_FMLS_asimdelem_R_SD, //!< <a href="../target/aarch64/FMLS_advsimd_elt.html#FMLS_asimdelem_R_SD">Vector, single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMLS_asimdsamefp16_only, //!< <a href="../target/aarch64/FMLS_advsimd_vec.html#FMLS_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FMLS_asimdsame_only, //!< <a href="../target/aarch64/FMLS_advsimd_vec.html#FMLS_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMLSL_asimdelem_LH, //!< <a href="../target/aarch64/FMLSL_advsimd_elt.html#FMLSL_asimdelem_LH">FMLSL</a>
  AMED_AARCH64_ENCODING_FMLSL2_asimdelem_LH, //!< <a href="../target/aarch64/FMLSL_advsimd_elt.html#FMLSL2_asimdelem_LH">FMLSL2</a>
  AMED_AARCH64_ENCODING_FMLSL_asimdsame_F, //!< <a href="../target/aarch64/FMLSL_advsimd_vec.html#FMLSL_asimdsame_F">FMLSL</a>
  AMED_AARCH64_ENCODING_FMLSL2_asimdsame_F, //!< <a href="../target/aarch64/FMLSL_advsimd_vec.html#FMLSL2_asimdsame_F">FMLSL2</a>
  AMED_AARCH64_ENCODING_FMOV_asimdimm_H_h, //!< <a href="../target/aarch64/FMOV_advsimd.html#FMOV_asimdimm_H_h">Half-precision</a>
  AMED_AARCH64_ENCODING_FMOV_asimdimm_S_s, //!< <a href="../target/aarch64/FMOV_advsimd.html#FMOV_asimdimm_S_s">Single-precision</a>
  AMED_AARCH64_ENCODING_FMOV_asimdimm_D2_d, //!< <a href="../target/aarch64/FMOV_advsimd.html#FMOV_asimdimm_D2_d">Double-precision</a>
  AMED_AARCH64_ENCODING_FMOV_H_floatdp1, //!< <a href="../target/aarch64/FMOV_float.html#FMOV_H_floatdp1">Half-precision</a>
  AMED_AARCH64_ENCODING_FMOV_S_floatdp1, //!< <a href="../target/aarch64/FMOV_float.html#FMOV_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FMOV_D_floatdp1, //!< <a href="../target/aarch64/FMOV_float.html#FMOV_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FMOV_32H_float2int, //!< <a href="../target/aarch64/FMOV_float_gen.html#FMOV_32H_float2int">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FMOV_64H_float2int, //!< <a href="../target/aarch64/FMOV_float_gen.html#FMOV_64H_float2int">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FMOV_H32_float2int, //!< <a href="../target/aarch64/FMOV_float_gen.html#FMOV_H32_float2int">32-bit to half-precision</a>
  AMED_AARCH64_ENCODING_FMOV_S32_float2int, //!< <a href="../target/aarch64/FMOV_float_gen.html#FMOV_S32_float2int">32-bit to single-precision</a>
  AMED_AARCH64_ENCODING_FMOV_32S_float2int, //!< <a href="../target/aarch64/FMOV_float_gen.html#FMOV_32S_float2int">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_FMOV_H64_float2int, //!< <a href="../target/aarch64/FMOV_float_gen.html#FMOV_H64_float2int">64-bit to half-precision</a>
  AMED_AARCH64_ENCODING_FMOV_D64_float2int, //!< <a href="../target/aarch64/FMOV_float_gen.html#FMOV_D64_float2int">64-bit to double-precision</a>
  AMED_AARCH64_ENCODING_FMOV_V64I_float2int, //!< <a href="../target/aarch64/FMOV_float_gen.html#FMOV_V64I_float2int">64-bit to top half of 128-bit</a>
  AMED_AARCH64_ENCODING_FMOV_64D_float2int, //!< <a href="../target/aarch64/FMOV_float_gen.html#FMOV_64D_float2int">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_FMOV_64VX_float2int, //!< <a href="../target/aarch64/FMOV_float_gen.html#FMOV_64VX_float2int">Top half of 128-bit to 64-bit</a>
  AMED_AARCH64_ENCODING_FMOV_H_floatimm, //!< <a href="../target/aarch64/FMOV_float_imm.html#FMOV_H_floatimm">Half-precision</a>
  AMED_AARCH64_ENCODING_FMOV_S_floatimm, //!< <a href="../target/aarch64/FMOV_float_imm.html#FMOV_S_floatimm">Single-precision</a>
  AMED_AARCH64_ENCODING_FMOV_D_floatimm, //!< <a href="../target/aarch64/FMOV_float_imm.html#FMOV_D_floatimm">Double-precision</a>
  AMED_AARCH64_ENCODING_FMSUB_H_floatdp3, //!< <a href="../target/aarch64/FMSUB_float.html#FMSUB_H_floatdp3">Half-precision</a>
  AMED_AARCH64_ENCODING_FMSUB_S_floatdp3, //!< <a href="../target/aarch64/FMSUB_float.html#FMSUB_S_floatdp3">Single-precision</a>
  AMED_AARCH64_ENCODING_FMSUB_D_floatdp3, //!< <a href="../target/aarch64/FMSUB_float.html#FMSUB_D_floatdp3">Double-precision</a>
  AMED_AARCH64_ENCODING_FMUL_asisdelem_RH_H, //!< <a href="../target/aarch64/FMUL_advsimd_elt.html#FMUL_asisdelem_RH_H">Scalar, half-precision</a>
  AMED_AARCH64_ENCODING_FMUL_asisdelem_R_SD, //!< <a href="../target/aarch64/FMUL_advsimd_elt.html#FMUL_asisdelem_R_SD">Scalar, single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMUL_asimdelem_RH_H, //!< <a href="../target/aarch64/FMUL_advsimd_elt.html#FMUL_asimdelem_RH_H">Vector, half-precision</a>
  AMED_AARCH64_ENCODING_FMUL_asimdelem_R_SD, //!< <a href="../target/aarch64/FMUL_advsimd_elt.html#FMUL_asimdelem_R_SD">Vector, single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMUL_asimdsamefp16_only, //!< <a href="../target/aarch64/FMUL_advsimd_vec.html#FMUL_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FMUL_asimdsame_only, //!< <a href="../target/aarch64/FMUL_advsimd_vec.html#FMUL_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMUL_H_floatdp2, //!< <a href="../target/aarch64/FMUL_float.html#FMUL_H_floatdp2">Half-precision</a>
  AMED_AARCH64_ENCODING_FMUL_S_floatdp2, //!< <a href="../target/aarch64/FMUL_float.html#FMUL_S_floatdp2">Single-precision</a>
  AMED_AARCH64_ENCODING_FMUL_D_floatdp2, //!< <a href="../target/aarch64/FMUL_float.html#FMUL_D_floatdp2">Double-precision</a>
  AMED_AARCH64_ENCODING_FMULX_asisdelem_RH_H, //!< <a href="../target/aarch64/FMULX_advsimd_elt.html#FMULX_asisdelem_RH_H">Scalar, half-precision</a>
  AMED_AARCH64_ENCODING_FMULX_asisdelem_R_SD, //!< <a href="../target/aarch64/FMULX_advsimd_elt.html#FMULX_asisdelem_R_SD">Scalar, single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMULX_asimdelem_RH_H, //!< <a href="../target/aarch64/FMULX_advsimd_elt.html#FMULX_asimdelem_RH_H">Vector, half-precision</a>
  AMED_AARCH64_ENCODING_FMULX_asimdelem_R_SD, //!< <a href="../target/aarch64/FMULX_advsimd_elt.html#FMULX_asimdelem_R_SD">Vector, single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMULX_asisdsamefp16_only, //!< <a href="../target/aarch64/FMULX_advsimd_vec.html#FMULX_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FMULX_asisdsame_only, //!< <a href="../target/aarch64/FMULX_advsimd_vec.html#FMULX_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FMULX_asimdsamefp16_only, //!< <a href="../target/aarch64/FMULX_advsimd_vec.html#FMULX_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_ENCODING_FMULX_asimdsame_only, //!< <a href="../target/aarch64/FMULX_advsimd_vec.html#FMULX_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FNEG_asimdmiscfp16_R, //!< <a href="../target/aarch64/FNEG_advsimd.html#FNEG_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_ENCODING_FNEG_asimdmisc_R, //!< <a href="../target/aarch64/FNEG_advsimd.html#FNEG_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FNEG_H_floatdp1, //!< <a href="../target/aarch64/FNEG_float.html#FNEG_H_floatdp1">Half-precision</a>
  AMED_AARCH64_ENCODING_FNEG_S_floatdp1, //!< <a href="../target/aarch64/FNEG_float.html#FNEG_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FNEG_D_floatdp1, //!< <a href="../target/aarch64/FNEG_float.html#FNEG_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FNMADD_H_floatdp3, //!< <a href="../target/aarch64/FNMADD_float.html#FNMADD_H_floatdp3">Half-precision</a>
  AMED_AARCH64_ENCODING_FNMADD_S_floatdp3, //!< <a href="../target/aarch64/FNMADD_float.html#FNMADD_S_floatdp3">Single-precision</a>
  AMED_AARCH64_ENCODING_FNMADD_D_floatdp3, //!< <a href="../target/aarch64/FNMADD_float.html#FNMADD_D_floatdp3">Double-precision</a>
  AMED_AARCH64_ENCODING_FNMSUB_H_floatdp3, //!< <a href="../target/aarch64/FNMSUB_float.html#FNMSUB_H_floatdp3">Half-precision</a>
  AMED_AARCH64_ENCODING_FNMSUB_S_floatdp3, //!< <a href="../target/aarch64/FNMSUB_float.html#FNMSUB_S_floatdp3">Single-precision</a>
  AMED_AARCH64_ENCODING_FNMSUB_D_floatdp3, //!< <a href="../target/aarch64/FNMSUB_float.html#FNMSUB_D_floatdp3">Double-precision</a>
  AMED_AARCH64_ENCODING_FNMUL_H_floatdp2, //!< <a href="../target/aarch64/FNMUL_float.html#FNMUL_H_floatdp2">Half-precision</a>
  AMED_AARCH64_ENCODING_FNMUL_S_floatdp2, //!< <a href="../target/aarch64/FNMUL_float.html#FNMUL_S_floatdp2">Single-precision</a>
  AMED_AARCH64_ENCODING_FNMUL_D_floatdp2, //!< <a href="../target/aarch64/FNMUL_float.html#FNMUL_D_floatdp2">Double-precision</a>
  AMED_AARCH64_ENCODING_FRECPE_asisdmiscfp16_R, //!< <a href="../target/aarch64/FRECPE_advsimd.html#FRECPE_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FRECPE_asisdmisc_R, //!< <a href="../target/aarch64/FRECPE_advsimd.html#FRECPE_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRECPE_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRECPE_advsimd.html#FRECPE_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_FRECPE_asimdmisc_R, //!< <a href="../target/aarch64/FRECPE_advsimd.html#FRECPE_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRECPS_asisdsamefp16_only, //!< <a href="../target/aarch64/FRECPS_advsimd.html#FRECPS_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FRECPS_asisdsame_only, //!< <a href="../target/aarch64/FRECPS_advsimd.html#FRECPS_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRECPS_asimdsamefp16_only, //!< <a href="../target/aarch64/FRECPS_advsimd.html#FRECPS_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_ENCODING_FRECPS_asimdsame_only, //!< <a href="../target/aarch64/FRECPS_advsimd.html#FRECPS_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRECPX_asisdmiscfp16_R, //!< <a href="../target/aarch64/FRECPX_advsimd.html#FRECPX_asisdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_ENCODING_FRECPX_asisdmisc_R, //!< <a href="../target/aarch64/FRECPX_advsimd.html#FRECPX_asisdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRINT32X_asimdmisc_R, //!< <a href="../target/aarch64/FRINT32X_advsimd.html#FRINT32X_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRINT32X_S_floatdp1, //!< <a href="../target/aarch64/FRINT32X_float.html#FRINT32X_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FRINT32X_D_floatdp1, //!< <a href="../target/aarch64/FRINT32X_float.html#FRINT32X_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FRINT32Z_asimdmisc_R, //!< <a href="../target/aarch64/FRINT32Z_advsimd.html#FRINT32Z_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRINT32Z_S_floatdp1, //!< <a href="../target/aarch64/FRINT32Z_float.html#FRINT32Z_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FRINT32Z_D_floatdp1, //!< <a href="../target/aarch64/FRINT32Z_float.html#FRINT32Z_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FRINT64X_asimdmisc_R, //!< <a href="../target/aarch64/FRINT64X_advsimd.html#FRINT64X_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRINT64X_S_floatdp1, //!< <a href="../target/aarch64/FRINT64X_float.html#FRINT64X_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FRINT64X_D_floatdp1, //!< <a href="../target/aarch64/FRINT64X_float.html#FRINT64X_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FRINT64Z_asimdmisc_R, //!< <a href="../target/aarch64/FRINT64Z_advsimd.html#FRINT64Z_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRINT64Z_S_floatdp1, //!< <a href="../target/aarch64/FRINT64Z_float.html#FRINT64Z_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FRINT64Z_D_floatdp1, //!< <a href="../target/aarch64/FRINT64Z_float.html#FRINT64Z_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FRINTA_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTA_advsimd.html#FRINTA_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTA_asimdmisc_R, //!< <a href="../target/aarch64/FRINTA_advsimd.html#FRINTA_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRINTA_H_floatdp1, //!< <a href="../target/aarch64/FRINTA_float.html#FRINTA_H_floatdp1">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTA_S_floatdp1, //!< <a href="../target/aarch64/FRINTA_float.html#FRINTA_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FRINTA_D_floatdp1, //!< <a href="../target/aarch64/FRINTA_float.html#FRINTA_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FRINTI_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTI_advsimd.html#FRINTI_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTI_asimdmisc_R, //!< <a href="../target/aarch64/FRINTI_advsimd.html#FRINTI_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRINTI_H_floatdp1, //!< <a href="../target/aarch64/FRINTI_float.html#FRINTI_H_floatdp1">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTI_S_floatdp1, //!< <a href="../target/aarch64/FRINTI_float.html#FRINTI_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FRINTI_D_floatdp1, //!< <a href="../target/aarch64/FRINTI_float.html#FRINTI_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FRINTM_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTM_advsimd.html#FRINTM_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTM_asimdmisc_R, //!< <a href="../target/aarch64/FRINTM_advsimd.html#FRINTM_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRINTM_H_floatdp1, //!< <a href="../target/aarch64/FRINTM_float.html#FRINTM_H_floatdp1">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTM_S_floatdp1, //!< <a href="../target/aarch64/FRINTM_float.html#FRINTM_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FRINTM_D_floatdp1, //!< <a href="../target/aarch64/FRINTM_float.html#FRINTM_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FRINTN_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTN_advsimd.html#FRINTN_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTN_asimdmisc_R, //!< <a href="../target/aarch64/FRINTN_advsimd.html#FRINTN_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRINTN_H_floatdp1, //!< <a href="../target/aarch64/FRINTN_float.html#FRINTN_H_floatdp1">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTN_S_floatdp1, //!< <a href="../target/aarch64/FRINTN_float.html#FRINTN_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FRINTN_D_floatdp1, //!< <a href="../target/aarch64/FRINTN_float.html#FRINTN_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FRINTP_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTP_advsimd.html#FRINTP_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTP_asimdmisc_R, //!< <a href="../target/aarch64/FRINTP_advsimd.html#FRINTP_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRINTP_H_floatdp1, //!< <a href="../target/aarch64/FRINTP_float.html#FRINTP_H_floatdp1">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTP_S_floatdp1, //!< <a href="../target/aarch64/FRINTP_float.html#FRINTP_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FRINTP_D_floatdp1, //!< <a href="../target/aarch64/FRINTP_float.html#FRINTP_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FRINTX_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTX_advsimd.html#FRINTX_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTX_asimdmisc_R, //!< <a href="../target/aarch64/FRINTX_advsimd.html#FRINTX_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRINTX_H_floatdp1, //!< <a href="../target/aarch64/FRINTX_float.html#FRINTX_H_floatdp1">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTX_S_floatdp1, //!< <a href="../target/aarch64/FRINTX_float.html#FRINTX_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FRINTX_D_floatdp1, //!< <a href="../target/aarch64/FRINTX_float.html#FRINTX_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FRINTZ_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTZ_advsimd.html#FRINTZ_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTZ_asimdmisc_R, //!< <a href="../target/aarch64/FRINTZ_advsimd.html#FRINTZ_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRINTZ_H_floatdp1, //!< <a href="../target/aarch64/FRINTZ_float.html#FRINTZ_H_floatdp1">Half-precision</a>
  AMED_AARCH64_ENCODING_FRINTZ_S_floatdp1, //!< <a href="../target/aarch64/FRINTZ_float.html#FRINTZ_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FRINTZ_D_floatdp1, //!< <a href="../target/aarch64/FRINTZ_float.html#FRINTZ_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FRSQRTE_asisdmiscfp16_R, //!< <a href="../target/aarch64/FRSQRTE_advsimd.html#FRSQRTE_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FRSQRTE_asisdmisc_R, //!< <a href="../target/aarch64/FRSQRTE_advsimd.html#FRSQRTE_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRSQRTE_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRSQRTE_advsimd.html#FRSQRTE_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_FRSQRTE_asimdmisc_R, //!< <a href="../target/aarch64/FRSQRTE_advsimd.html#FRSQRTE_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRSQRTS_asisdsamefp16_only, //!< <a href="../target/aarch64/FRSQRTS_advsimd.html#FRSQRTS_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_ENCODING_FRSQRTS_asisdsame_only, //!< <a href="../target/aarch64/FRSQRTS_advsimd.html#FRSQRTS_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FRSQRTS_asimdsamefp16_only, //!< <a href="../target/aarch64/FRSQRTS_advsimd.html#FRSQRTS_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_ENCODING_FRSQRTS_asimdsame_only, //!< <a href="../target/aarch64/FRSQRTS_advsimd.html#FRSQRTS_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FSQRT_asimdmiscfp16_R, //!< <a href="../target/aarch64/FSQRT_advsimd.html#FSQRT_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_ENCODING_FSQRT_asimdmisc_R, //!< <a href="../target/aarch64/FSQRT_advsimd.html#FSQRT_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FSQRT_H_floatdp1, //!< <a href="../target/aarch64/FSQRT_float.html#FSQRT_H_floatdp1">Half-precision</a>
  AMED_AARCH64_ENCODING_FSQRT_S_floatdp1, //!< <a href="../target/aarch64/FSQRT_float.html#FSQRT_S_floatdp1">Single-precision</a>
  AMED_AARCH64_ENCODING_FSQRT_D_floatdp1, //!< <a href="../target/aarch64/FSQRT_float.html#FSQRT_D_floatdp1">Double-precision</a>
  AMED_AARCH64_ENCODING_FSUB_asimdsamefp16_only, //!< <a href="../target/aarch64/FSUB_advsimd.html#FSUB_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_ENCODING_FSUB_asimdsame_only, //!< <a href="../target/aarch64/FSUB_advsimd.html#FSUB_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_FSUB_H_floatdp2, //!< <a href="../target/aarch64/FSUB_float.html#FSUB_H_floatdp2">Half-precision</a>
  AMED_AARCH64_ENCODING_FSUB_S_floatdp2, //!< <a href="../target/aarch64/FSUB_float.html#FSUB_S_floatdp2">Single-precision</a>
  AMED_AARCH64_ENCODING_FSUB_D_floatdp2, //!< <a href="../target/aarch64/FSUB_float.html#FSUB_D_floatdp2">Double-precision</a>
  AMED_AARCH64_ENCODING_INS_asimdins_IV_v, //!< <a href="../target/aarch64/INS_advsimd_elt.html#INS_asimdins_IV_v">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_INS_asimdins_IR_r, //!< <a href="../target/aarch64/INS_advsimd_gen.html#INS_asimdins_IR_r">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_LD1_asisdlse_R1_1v, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#LD1_asisdlse_R1_1v">One register</a>
  AMED_AARCH64_ENCODING_LD1_asisdlse_R2_2v, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#LD1_asisdlse_R2_2v">Two registers</a>
  AMED_AARCH64_ENCODING_LD1_asisdlse_R3_3v, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#LD1_asisdlse_R3_3v">Three registers</a>
  AMED_AARCH64_ENCODING_LD1_asisdlse_R4_4v, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#LD1_asisdlse_R4_4v">Four registers</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsep_I1_i1, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#LD1_asisdlsep_I1_i1">One register, immediate offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsep_R1_r1, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#LD1_asisdlsep_R1_r1">One register, register offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsep_I2_i2, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#LD1_asisdlsep_I2_i2">Two registers, immediate offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsep_R2_r2, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#LD1_asisdlsep_R2_r2">Two registers, register offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsep_I3_i3, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#LD1_asisdlsep_I3_i3">Three registers, immediate offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsep_R3_r3, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#LD1_asisdlsep_R3_r3">Three registers, register offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsep_I4_i4, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#LD1_asisdlsep_I4_i4">Four registers, immediate offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsep_R4_r4, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#LD1_asisdlsep_R4_r4">Four registers, register offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlso_B1_1b, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#LD1_asisdlso_B1_1b">8-bit</a>
  AMED_AARCH64_ENCODING_LD1_asisdlso_H1_1h, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#LD1_asisdlso_H1_1h">16-bit</a>
  AMED_AARCH64_ENCODING_LD1_asisdlso_S1_1s, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#LD1_asisdlso_S1_1s">32-bit</a>
  AMED_AARCH64_ENCODING_LD1_asisdlso_D1_1d, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#LD1_asisdlso_D1_1d">64-bit</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsop_B1_i1b, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#LD1_asisdlsop_B1_i1b">8-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsop_BX1_r1b, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#LD1_asisdlsop_BX1_r1b">8-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsop_H1_i1h, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#LD1_asisdlsop_H1_i1h">16-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsop_HX1_r1h, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#LD1_asisdlsop_HX1_r1h">16-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsop_S1_i1s, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#LD1_asisdlsop_S1_i1s">32-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsop_SX1_r1s, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#LD1_asisdlsop_SX1_r1s">32-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsop_D1_i1d, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#LD1_asisdlsop_D1_i1d">64-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD1_asisdlsop_DX1_r1d, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#LD1_asisdlsop_DX1_r1d">64-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD1R_asisdlso_R1, //!< <a href="../target/aarch64/LD1R_advsimd.html#LD1R_asisdlso_R1">No offset</a>
  AMED_AARCH64_ENCODING_LD1R_asisdlsop_R1_i, //!< <a href="../target/aarch64/LD1R_advsimd.html#LD1R_asisdlsop_R1_i">Immediate offset</a>
  AMED_AARCH64_ENCODING_LD1R_asisdlsop_RX1_r, //!< <a href="../target/aarch64/LD1R_advsimd.html#LD1R_asisdlsop_RX1_r">Register offset</a>
  AMED_AARCH64_ENCODING_LD2_asisdlse_R2, //!< <a href="../target/aarch64/LD2_advsimd_mult.html#LD2_asisdlse_R2">No offset</a>
  AMED_AARCH64_ENCODING_LD2_asisdlsep_I2_i, //!< <a href="../target/aarch64/LD2_advsimd_mult.html#LD2_asisdlsep_I2_i">Immediate offset</a>
  AMED_AARCH64_ENCODING_LD2_asisdlsep_R2_r, //!< <a href="../target/aarch64/LD2_advsimd_mult.html#LD2_asisdlsep_R2_r">Register offset</a>
  AMED_AARCH64_ENCODING_LD2_asisdlso_B2_2b, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#LD2_asisdlso_B2_2b">8-bit</a>
  AMED_AARCH64_ENCODING_LD2_asisdlso_H2_2h, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#LD2_asisdlso_H2_2h">16-bit</a>
  AMED_AARCH64_ENCODING_LD2_asisdlso_S2_2s, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#LD2_asisdlso_S2_2s">32-bit</a>
  AMED_AARCH64_ENCODING_LD2_asisdlso_D2_2d, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#LD2_asisdlso_D2_2d">64-bit</a>
  AMED_AARCH64_ENCODING_LD2_asisdlsop_B2_i2b, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#LD2_asisdlsop_B2_i2b">8-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD2_asisdlsop_BX2_r2b, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#LD2_asisdlsop_BX2_r2b">8-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD2_asisdlsop_H2_i2h, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#LD2_asisdlsop_H2_i2h">16-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD2_asisdlsop_HX2_r2h, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#LD2_asisdlsop_HX2_r2h">16-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD2_asisdlsop_S2_i2s, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#LD2_asisdlsop_S2_i2s">32-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD2_asisdlsop_SX2_r2s, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#LD2_asisdlsop_SX2_r2s">32-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD2_asisdlsop_D2_i2d, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#LD2_asisdlsop_D2_i2d">64-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD2_asisdlsop_DX2_r2d, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#LD2_asisdlsop_DX2_r2d">64-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD2R_asisdlso_R2, //!< <a href="../target/aarch64/LD2R_advsimd.html#LD2R_asisdlso_R2">No offset</a>
  AMED_AARCH64_ENCODING_LD2R_asisdlsop_R2_i, //!< <a href="../target/aarch64/LD2R_advsimd.html#LD2R_asisdlsop_R2_i">Immediate offset</a>
  AMED_AARCH64_ENCODING_LD2R_asisdlsop_RX2_r, //!< <a href="../target/aarch64/LD2R_advsimd.html#LD2R_asisdlsop_RX2_r">Register offset</a>
  AMED_AARCH64_ENCODING_LD3_asisdlse_R3, //!< <a href="../target/aarch64/LD3_advsimd_mult.html#LD3_asisdlse_R3">No offset</a>
  AMED_AARCH64_ENCODING_LD3_asisdlsep_I3_i, //!< <a href="../target/aarch64/LD3_advsimd_mult.html#LD3_asisdlsep_I3_i">Immediate offset</a>
  AMED_AARCH64_ENCODING_LD3_asisdlsep_R3_r, //!< <a href="../target/aarch64/LD3_advsimd_mult.html#LD3_asisdlsep_R3_r">Register offset</a>
  AMED_AARCH64_ENCODING_LD3_asisdlso_B3_3b, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#LD3_asisdlso_B3_3b">8-bit</a>
  AMED_AARCH64_ENCODING_LD3_asisdlso_H3_3h, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#LD3_asisdlso_H3_3h">16-bit</a>
  AMED_AARCH64_ENCODING_LD3_asisdlso_S3_3s, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#LD3_asisdlso_S3_3s">32-bit</a>
  AMED_AARCH64_ENCODING_LD3_asisdlso_D3_3d, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#LD3_asisdlso_D3_3d">64-bit</a>
  AMED_AARCH64_ENCODING_LD3_asisdlsop_B3_i3b, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#LD3_asisdlsop_B3_i3b">8-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD3_asisdlsop_BX3_r3b, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#LD3_asisdlsop_BX3_r3b">8-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD3_asisdlsop_H3_i3h, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#LD3_asisdlsop_H3_i3h">16-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD3_asisdlsop_HX3_r3h, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#LD3_asisdlsop_HX3_r3h">16-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD3_asisdlsop_S3_i3s, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#LD3_asisdlsop_S3_i3s">32-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD3_asisdlsop_SX3_r3s, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#LD3_asisdlsop_SX3_r3s">32-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD3_asisdlsop_D3_i3d, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#LD3_asisdlsop_D3_i3d">64-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD3_asisdlsop_DX3_r3d, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#LD3_asisdlsop_DX3_r3d">64-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD3R_asisdlso_R3, //!< <a href="../target/aarch64/LD3R_advsimd.html#LD3R_asisdlso_R3">No offset</a>
  AMED_AARCH64_ENCODING_LD3R_asisdlsop_R3_i, //!< <a href="../target/aarch64/LD3R_advsimd.html#LD3R_asisdlsop_R3_i">Immediate offset</a>
  AMED_AARCH64_ENCODING_LD3R_asisdlsop_RX3_r, //!< <a href="../target/aarch64/LD3R_advsimd.html#LD3R_asisdlsop_RX3_r">Register offset</a>
  AMED_AARCH64_ENCODING_LD4_asisdlse_R4, //!< <a href="../target/aarch64/LD4_advsimd_mult.html#LD4_asisdlse_R4">No offset</a>
  AMED_AARCH64_ENCODING_LD4_asisdlsep_I4_i, //!< <a href="../target/aarch64/LD4_advsimd_mult.html#LD4_asisdlsep_I4_i">Immediate offset</a>
  AMED_AARCH64_ENCODING_LD4_asisdlsep_R4_r, //!< <a href="../target/aarch64/LD4_advsimd_mult.html#LD4_asisdlsep_R4_r">Register offset</a>
  AMED_AARCH64_ENCODING_LD4_asisdlso_B4_4b, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#LD4_asisdlso_B4_4b">8-bit</a>
  AMED_AARCH64_ENCODING_LD4_asisdlso_H4_4h, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#LD4_asisdlso_H4_4h">16-bit</a>
  AMED_AARCH64_ENCODING_LD4_asisdlso_S4_4s, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#LD4_asisdlso_S4_4s">32-bit</a>
  AMED_AARCH64_ENCODING_LD4_asisdlso_D4_4d, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#LD4_asisdlso_D4_4d">64-bit</a>
  AMED_AARCH64_ENCODING_LD4_asisdlsop_B4_i4b, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#LD4_asisdlsop_B4_i4b">8-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD4_asisdlsop_BX4_r4b, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#LD4_asisdlsop_BX4_r4b">8-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD4_asisdlsop_H4_i4h, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#LD4_asisdlsop_H4_i4h">16-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD4_asisdlsop_HX4_r4h, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#LD4_asisdlsop_HX4_r4h">16-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD4_asisdlsop_S4_i4s, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#LD4_asisdlsop_S4_i4s">32-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD4_asisdlsop_SX4_r4s, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#LD4_asisdlsop_SX4_r4s">32-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD4_asisdlsop_D4_i4d, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#LD4_asisdlsop_D4_i4d">64-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_LD4_asisdlsop_DX4_r4d, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#LD4_asisdlsop_DX4_r4d">64-bit, register offset</a>
  AMED_AARCH64_ENCODING_LD4R_asisdlso_R4, //!< <a href="../target/aarch64/LD4R_advsimd.html#LD4R_asisdlso_R4">No offset</a>
  AMED_AARCH64_ENCODING_LD4R_asisdlsop_R4_i, //!< <a href="../target/aarch64/LD4R_advsimd.html#LD4R_asisdlsop_R4_i">Immediate offset</a>
  AMED_AARCH64_ENCODING_LD4R_asisdlsop_RX4_r, //!< <a href="../target/aarch64/LD4R_advsimd.html#LD4R_asisdlsop_RX4_r">Register offset</a>
  AMED_AARCH64_ENCODING_LDNP_S_ldstnapair_offs, //!< <a href="../target/aarch64/LDNP_fpsimd.html#LDNP_S_ldstnapair_offs">32-bit</a>
  AMED_AARCH64_ENCODING_LDNP_D_ldstnapair_offs, //!< <a href="../target/aarch64/LDNP_fpsimd.html#LDNP_D_ldstnapair_offs">64-bit</a>
  AMED_AARCH64_ENCODING_LDNP_Q_ldstnapair_offs, //!< <a href="../target/aarch64/LDNP_fpsimd.html#LDNP_Q_ldstnapair_offs">128-bit</a>
  AMED_AARCH64_ENCODING_LDP_S_ldstpair_post, //!< <a href="../target/aarch64/LDP_fpsimd.html#LDP_S_ldstpair_post">32-bit</a>
  AMED_AARCH64_ENCODING_LDP_D_ldstpair_post, //!< <a href="../target/aarch64/LDP_fpsimd.html#LDP_D_ldstpair_post">64-bit</a>
  AMED_AARCH64_ENCODING_LDP_Q_ldstpair_post, //!< <a href="../target/aarch64/LDP_fpsimd.html#LDP_Q_ldstpair_post">128-bit</a>
  AMED_AARCH64_ENCODING_LDP_S_ldstpair_pre, //!< <a href="../target/aarch64/LDP_fpsimd.html#LDP_S_ldstpair_pre">32-bit</a>
  AMED_AARCH64_ENCODING_LDP_D_ldstpair_pre, //!< <a href="../target/aarch64/LDP_fpsimd.html#LDP_D_ldstpair_pre">64-bit</a>
  AMED_AARCH64_ENCODING_LDP_Q_ldstpair_pre, //!< <a href="../target/aarch64/LDP_fpsimd.html#LDP_Q_ldstpair_pre">128-bit</a>
  AMED_AARCH64_ENCODING_LDP_S_ldstpair_off, //!< <a href="../target/aarch64/LDP_fpsimd.html#LDP_S_ldstpair_off">32-bit</a>
  AMED_AARCH64_ENCODING_LDP_D_ldstpair_off, //!< <a href="../target/aarch64/LDP_fpsimd.html#LDP_D_ldstpair_off">64-bit</a>
  AMED_AARCH64_ENCODING_LDP_Q_ldstpair_off, //!< <a href="../target/aarch64/LDP_fpsimd.html#LDP_Q_ldstpair_off">128-bit</a>
  AMED_AARCH64_ENCODING_LDR_B_ldst_immpost, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_B_ldst_immpost">8-bit</a>
  AMED_AARCH64_ENCODING_LDR_H_ldst_immpost, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_H_ldst_immpost">16-bit</a>
  AMED_AARCH64_ENCODING_LDR_S_ldst_immpost, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_S_ldst_immpost">32-bit</a>
  AMED_AARCH64_ENCODING_LDR_D_ldst_immpost, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_D_ldst_immpost">64-bit</a>
  AMED_AARCH64_ENCODING_LDR_Q_ldst_immpost, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_Q_ldst_immpost">128-bit</a>
  AMED_AARCH64_ENCODING_LDR_B_ldst_immpre, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_B_ldst_immpre">8-bit</a>
  AMED_AARCH64_ENCODING_LDR_H_ldst_immpre, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_H_ldst_immpre">16-bit</a>
  AMED_AARCH64_ENCODING_LDR_S_ldst_immpre, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_S_ldst_immpre">32-bit</a>
  AMED_AARCH64_ENCODING_LDR_D_ldst_immpre, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_D_ldst_immpre">64-bit</a>
  AMED_AARCH64_ENCODING_LDR_Q_ldst_immpre, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_Q_ldst_immpre">128-bit</a>
  AMED_AARCH64_ENCODING_LDR_B_ldst_pos, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_B_ldst_pos">8-bit</a>
  AMED_AARCH64_ENCODING_LDR_H_ldst_pos, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_H_ldst_pos">16-bit</a>
  AMED_AARCH64_ENCODING_LDR_S_ldst_pos, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_S_ldst_pos">32-bit</a>
  AMED_AARCH64_ENCODING_LDR_D_ldst_pos, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_D_ldst_pos">64-bit</a>
  AMED_AARCH64_ENCODING_LDR_Q_ldst_pos, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#LDR_Q_ldst_pos">128-bit</a>
  AMED_AARCH64_ENCODING_LDR_S_loadlit, //!< <a href="../target/aarch64/LDR_lit_fpsimd.html#LDR_S_loadlit">32-bit</a>
  AMED_AARCH64_ENCODING_LDR_D_loadlit, //!< <a href="../target/aarch64/LDR_lit_fpsimd.html#LDR_D_loadlit">64-bit</a>
  AMED_AARCH64_ENCODING_LDR_Q_loadlit, //!< <a href="../target/aarch64/LDR_lit_fpsimd.html#LDR_Q_loadlit">128-bit</a>
  AMED_AARCH64_ENCODING_LDR_B_ldst_regoff, //!< <a href="../target/aarch64/LDR_reg_fpsimd.html#LDR_B_ldst_regoff">8-fsreg,LDR-8-fsreg</a>
  AMED_AARCH64_ENCODING_LDR_BL_ldst_regoff, //!< <a href="../target/aarch64/LDR_reg_fpsimd.html#LDR_BL_ldst_regoff">8-fsreg,LDR-8-fsreg</a>
  AMED_AARCH64_ENCODING_LDR_H_ldst_regoff, //!< <a href="../target/aarch64/LDR_reg_fpsimd.html#LDR_H_ldst_regoff">16-fsreg,LDR-16-fsreg</a>
  AMED_AARCH64_ENCODING_LDR_S_ldst_regoff, //!< <a href="../target/aarch64/LDR_reg_fpsimd.html#LDR_S_ldst_regoff">32-fsreg,LDR-32-fsreg</a>
  AMED_AARCH64_ENCODING_LDR_D_ldst_regoff, //!< <a href="../target/aarch64/LDR_reg_fpsimd.html#LDR_D_ldst_regoff">64-fsreg,LDR-64-fsreg</a>
  AMED_AARCH64_ENCODING_LDR_Q_ldst_regoff, //!< <a href="../target/aarch64/LDR_reg_fpsimd.html#LDR_Q_ldst_regoff">128-fsreg,LDR-128-fsreg</a>
  AMED_AARCH64_ENCODING_LDUR_B_ldst_unscaled, //!< <a href="../target/aarch64/LDUR_fpsimd.html#LDUR_B_ldst_unscaled">8-bit</a>
  AMED_AARCH64_ENCODING_LDUR_H_ldst_unscaled, //!< <a href="../target/aarch64/LDUR_fpsimd.html#LDUR_H_ldst_unscaled">16-bit</a>
  AMED_AARCH64_ENCODING_LDUR_S_ldst_unscaled, //!< <a href="../target/aarch64/LDUR_fpsimd.html#LDUR_S_ldst_unscaled">32-bit</a>
  AMED_AARCH64_ENCODING_LDUR_D_ldst_unscaled, //!< <a href="../target/aarch64/LDUR_fpsimd.html#LDUR_D_ldst_unscaled">64-bit</a>
  AMED_AARCH64_ENCODING_LDUR_Q_ldst_unscaled, //!< <a href="../target/aarch64/LDUR_fpsimd.html#LDUR_Q_ldst_unscaled">128-bit</a>
  AMED_AARCH64_ENCODING_MLA_asimdelem_R, //!< <a href="../target/aarch64/MLA_advsimd_elt.html#MLA_asimdelem_R">Vector</a>
  AMED_AARCH64_ENCODING_MLA_asimdsame_only, //!< <a href="../target/aarch64/MLA_advsimd_vec.html#MLA_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_MLS_asimdelem_R, //!< <a href="../target/aarch64/MLS_advsimd_elt.html#MLS_asimdelem_R">Vector</a>
  AMED_AARCH64_ENCODING_MLS_asimdsame_only, //!< <a href="../target/aarch64/MLS_advsimd_vec.html#MLS_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_MOVI_asimdimm_N_b, //!< <a href="../target/aarch64/MOVI_advsimd.html#MOVI_asimdimm_N_b">8-bit</a>
  AMED_AARCH64_ENCODING_MOVI_asimdimm_L_hl, //!< <a href="../target/aarch64/MOVI_advsimd.html#MOVI_asimdimm_L_hl">16-bit shifted immediate</a>
  AMED_AARCH64_ENCODING_MOVI_asimdimm_L_sl, //!< <a href="../target/aarch64/MOVI_advsimd.html#MOVI_asimdimm_L_sl">32-bit shifted immediate</a>
  AMED_AARCH64_ENCODING_MOVI_asimdimm_M_sm, //!< <a href="../target/aarch64/MOVI_advsimd.html#MOVI_asimdimm_M_sm">32-bit shifting ones</a>
  AMED_AARCH64_ENCODING_MOVI_asimdimm_D_ds, //!< <a href="../target/aarch64/MOVI_advsimd.html#MOVI_asimdimm_D_ds">64-bit scalar</a>
  AMED_AARCH64_ENCODING_MOVI_asimdimm_D2_d, //!< <a href="../target/aarch64/MOVI_advsimd.html#MOVI_asimdimm_D2_d">64-bit vector</a>
  AMED_AARCH64_ENCODING_MUL_asimdelem_R, //!< <a href="../target/aarch64/MUL_advsimd_elt.html#MUL_asimdelem_R">Vector</a>
  AMED_AARCH64_ENCODING_MUL_asimdsame_only, //!< <a href="../target/aarch64/MUL_advsimd_vec.html#MUL_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_MVNI_asimdimm_L_hl, //!< <a href="../target/aarch64/MVNI_advsimd.html#MVNI_asimdimm_L_hl">16-bit shifted immediate</a>
  AMED_AARCH64_ENCODING_MVNI_asimdimm_L_sl, //!< <a href="../target/aarch64/MVNI_advsimd.html#MVNI_asimdimm_L_sl">32-bit shifted immediate</a>
  AMED_AARCH64_ENCODING_MVNI_asimdimm_M_sm, //!< <a href="../target/aarch64/MVNI_advsimd.html#MVNI_asimdimm_M_sm">32-bit shifting ones</a>
  AMED_AARCH64_ENCODING_NEG_asisdmisc_R, //!< <a href="../target/aarch64/NEG_advsimd.html#NEG_asisdmisc_R">Scalar</a>
  AMED_AARCH64_ENCODING_NEG_asimdmisc_R, //!< <a href="../target/aarch64/NEG_advsimd.html#NEG_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_NOT_asimdmisc_R, //!< <a href="../target/aarch64/NOT_advsimd.html#NOT_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_ORN_asimdsame_only, //!< <a href="../target/aarch64/ORN_advsimd.html#ORN_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_ORR_asimdimm_L_hl, //!< <a href="../target/aarch64/ORR_advsimd_imm.html#ORR_asimdimm_L_hl">16-bit</a>
  AMED_AARCH64_ENCODING_ORR_asimdimm_L_sl, //!< <a href="../target/aarch64/ORR_advsimd_imm.html#ORR_asimdimm_L_sl">32-bit</a>
  AMED_AARCH64_ENCODING_ORR_asimdsame_only, //!< <a href="../target/aarch64/ORR_advsimd_reg.html#ORR_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_PMUL_asimdsame_only, //!< <a href="../target/aarch64/PMUL_advsimd.html#PMUL_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_PMULL_asimddiff_L, //!< <a href="../target/aarch64/PMULL_advsimd.html#PMULL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_RADDHN_asimddiff_N, //!< <a href="../target/aarch64/RADDHN_advsimd.html#RADDHN_asimddiff_N">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_RAX1_VVV2_cryptosha512_3, //!< <a href="../target/aarch64/RAX1_advsimd.html#RAX1_VVV2_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_RBIT_asimdmisc_R, //!< <a href="../target/aarch64/RBIT_advsimd.html#RBIT_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_REV16_asimdmisc_R, //!< <a href="../target/aarch64/REV16_advsimd.html#REV16_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_REV32_asimdmisc_R, //!< <a href="../target/aarch64/REV32_advsimd.html#REV32_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_REV64_asimdmisc_R, //!< <a href="../target/aarch64/REV64_advsimd.html#REV64_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_RSHRN_asimdshf_N, //!< <a href="../target/aarch64/RSHRN_advsimd.html#RSHRN_asimdshf_N">Vector</a>
  AMED_AARCH64_ENCODING_RSUBHN_asimddiff_N, //!< <a href="../target/aarch64/RSUBHN_advsimd.html#RSUBHN_asimddiff_N">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_SABA_asimdsame_only, //!< <a href="../target/aarch64/SABA_advsimd.html#SABA_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_SABAL_asimddiff_L, //!< <a href="../target/aarch64/SABAL_advsimd.html#SABAL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_SABD_asimdsame_only, //!< <a href="../target/aarch64/SABD_advsimd.html#SABD_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_SABDL_asimddiff_L, //!< <a href="../target/aarch64/SABDL_advsimd.html#SABDL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_SADALP_asimdmisc_P, //!< <a href="../target/aarch64/SADALP_advsimd.html#SADALP_asimdmisc_P">Vector</a>
  AMED_AARCH64_ENCODING_SADDL_asimddiff_L, //!< <a href="../target/aarch64/SADDL_advsimd.html#SADDL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_SADDLP_asimdmisc_P, //!< <a href="../target/aarch64/SADDLP_advsimd.html#SADDLP_asimdmisc_P">Vector</a>
  AMED_AARCH64_ENCODING_SADDLV_asimdall_only, //!< <a href="../target/aarch64/SADDLV_advsimd.html#SADDLV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SADDW_asimddiff_W, //!< <a href="../target/aarch64/SADDW_advsimd.html#SADDW_asimddiff_W">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_SCVTF_asisdshf_C, //!< <a href="../target/aarch64/SCVTF_advsimd_fix.html#SCVTF_asisdshf_C">Scalar</a>
  AMED_AARCH64_ENCODING_SCVTF_asimdshf_C, //!< <a href="../target/aarch64/SCVTF_advsimd_fix.html#SCVTF_asimdshf_C">Vector</a>
  AMED_AARCH64_ENCODING_SCVTF_asisdmiscfp16_R, //!< <a href="../target/aarch64/SCVTF_advsimd_int.html#SCVTF_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_SCVTF_asisdmisc_R, //!< <a href="../target/aarch64/SCVTF_advsimd_int.html#SCVTF_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_SCVTF_asimdmiscfp16_R, //!< <a href="../target/aarch64/SCVTF_advsimd_int.html#SCVTF_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_SCVTF_asimdmisc_R, //!< <a href="../target/aarch64/SCVTF_advsimd_int.html#SCVTF_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_SCVTF_H32_float2fix, //!< <a href="../target/aarch64/SCVTF_float_fix.html#SCVTF_H32_float2fix">32-bit to half-precision</a>
  AMED_AARCH64_ENCODING_SCVTF_S32_float2fix, //!< <a href="../target/aarch64/SCVTF_float_fix.html#SCVTF_S32_float2fix">32-bit to single-precision</a>
  AMED_AARCH64_ENCODING_SCVTF_D32_float2fix, //!< <a href="../target/aarch64/SCVTF_float_fix.html#SCVTF_D32_float2fix">32-bit to double-precision</a>
  AMED_AARCH64_ENCODING_SCVTF_H64_float2fix, //!< <a href="../target/aarch64/SCVTF_float_fix.html#SCVTF_H64_float2fix">64-bit to half-precision</a>
  AMED_AARCH64_ENCODING_SCVTF_S64_float2fix, //!< <a href="../target/aarch64/SCVTF_float_fix.html#SCVTF_S64_float2fix">64-bit to single-precision</a>
  AMED_AARCH64_ENCODING_SCVTF_D64_float2fix, //!< <a href="../target/aarch64/SCVTF_float_fix.html#SCVTF_D64_float2fix">64-bit to double-precision</a>
  AMED_AARCH64_ENCODING_SCVTF_H32_float2int, //!< <a href="../target/aarch64/SCVTF_float_int.html#SCVTF_H32_float2int">32-bit to half-precision</a>
  AMED_AARCH64_ENCODING_SCVTF_S32_float2int, //!< <a href="../target/aarch64/SCVTF_float_int.html#SCVTF_S32_float2int">32-bit to single-precision</a>
  AMED_AARCH64_ENCODING_SCVTF_D32_float2int, //!< <a href="../target/aarch64/SCVTF_float_int.html#SCVTF_D32_float2int">32-bit to double-precision</a>
  AMED_AARCH64_ENCODING_SCVTF_H64_float2int, //!< <a href="../target/aarch64/SCVTF_float_int.html#SCVTF_H64_float2int">64-bit to half-precision</a>
  AMED_AARCH64_ENCODING_SCVTF_S64_float2int, //!< <a href="../target/aarch64/SCVTF_float_int.html#SCVTF_S64_float2int">64-bit to single-precision</a>
  AMED_AARCH64_ENCODING_SCVTF_D64_float2int, //!< <a href="../target/aarch64/SCVTF_float_int.html#SCVTF_D64_float2int">64-bit to double-precision</a>
  AMED_AARCH64_ENCODING_SDOT_asimdelem_D, //!< <a href="../target/aarch64/SDOT_advsimd_elt.html#SDOT_asimdelem_D">Vector</a>
  AMED_AARCH64_ENCODING_SDOT_asimdsame2_D, //!< <a href="../target/aarch64/SDOT_advsimd_vec.html#SDOT_asimdsame2_D">Vector</a>
  AMED_AARCH64_ENCODING_SHA1C_QSV_cryptosha3, //!< <a href="../target/aarch64/SHA1C_advsimd.html#SHA1C_QSV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHA1H_SS_cryptosha2, //!< <a href="../target/aarch64/SHA1H_advsimd.html#SHA1H_SS_cryptosha2">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHA1M_QSV_cryptosha3, //!< <a href="../target/aarch64/SHA1M_advsimd.html#SHA1M_QSV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHA1P_QSV_cryptosha3, //!< <a href="../target/aarch64/SHA1P_advsimd.html#SHA1P_QSV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHA1SU0_VVV_cryptosha3, //!< <a href="../target/aarch64/SHA1SU0_advsimd.html#SHA1SU0_VVV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHA1SU1_VV_cryptosha2, //!< <a href="../target/aarch64/SHA1SU1_advsimd.html#SHA1SU1_VV_cryptosha2">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHA256H2_QQV_cryptosha3, //!< <a href="../target/aarch64/SHA256H2_advsimd.html#SHA256H2_QQV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHA256H_QQV_cryptosha3, //!< <a href="../target/aarch64/SHA256H_advsimd.html#SHA256H_QQV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHA256SU0_VV_cryptosha2, //!< <a href="../target/aarch64/SHA256SU0_advsimd.html#SHA256SU0_VV_cryptosha2">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHA256SU1_VVV_cryptosha3, //!< <a href="../target/aarch64/SHA256SU1_advsimd.html#SHA256SU1_VVV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHA512H2_QQV_cryptosha512_3, //!< <a href="../target/aarch64/SHA512H2_advsimd.html#SHA512H2_QQV_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHA512H_QQV_cryptosha512_3, //!< <a href="../target/aarch64/SHA512H_advsimd.html#SHA512H_QQV_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHA512SU0_VV2_cryptosha512_2, //!< <a href="../target/aarch64/SHA512SU0_advsimd.html#SHA512SU0_VV2_cryptosha512_2">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHA512SU1_VVV2_cryptosha512_3, //!< <a href="../target/aarch64/SHA512SU1_advsimd.html#SHA512SU1_VVV2_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SHADD_asimdsame_only, //!< <a href="../target/aarch64/SHADD_advsimd.html#SHADD_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_SHL_asisdshf_R, //!< <a href="../target/aarch64/SHL_advsimd.html#SHL_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_SHL_asimdshf_R, //!< <a href="../target/aarch64/SHL_advsimd.html#SHL_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_SHLL_asimdmisc_S, //!< <a href="../target/aarch64/SHLL_advsimd.html#SHLL_asimdmisc_S">Vector</a>
  AMED_AARCH64_ENCODING_SHRN_asimdshf_N, //!< <a href="../target/aarch64/SHRN_advsimd.html#SHRN_asimdshf_N">Vector</a>
  AMED_AARCH64_ENCODING_SHSUB_asimdsame_only, //!< <a href="../target/aarch64/SHSUB_advsimd.html#SHSUB_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_SLI_asisdshf_R, //!< <a href="../target/aarch64/SLI_advsimd.html#SLI_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_SLI_asimdshf_R, //!< <a href="../target/aarch64/SLI_advsimd.html#SLI_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_SM3PARTW1_VVV4_cryptosha512_3, //!< <a href="../target/aarch64/SM3PARTW1_advsimd.html#SM3PARTW1_VVV4_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SM3PARTW2_VVV4_cryptosha512_3, //!< <a href="../target/aarch64/SM3PARTW2_advsimd.html#SM3PARTW2_VVV4_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SM3SS1_VVV4_crypto4, //!< <a href="../target/aarch64/SM3SS1_advsimd.html#SM3SS1_VVV4_crypto4">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SM3TT1A_VVV4_crypto3_imm2, //!< <a href="../target/aarch64/SM3TT1A_advsimd.html#SM3TT1A_VVV4_crypto3_imm2">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SM3TT1B_VVV4_crypto3_imm2, //!< <a href="../target/aarch64/SM3TT1B_advsimd.html#SM3TT1B_VVV4_crypto3_imm2">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SM3TT2A_VVV4_crypto3_imm2, //!< <a href="../target/aarch64/SM3TT2A_advsimd.html#SM3TT2A_VVV4_crypto3_imm2">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SM3TT2B_VVV_crypto3_imm2, //!< <a href="../target/aarch64/SM3TT2B_advsimd.html#SM3TT2B_VVV_crypto3_imm2">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SM4E_VV4_cryptosha512_2, //!< <a href="../target/aarch64/SM4E_advsimd.html#SM4E_VV4_cryptosha512_2">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SM4EKEY_VVV4_cryptosha512_3, //!< <a href="../target/aarch64/SM4EKEY_advsimd.html#SM4EKEY_VVV4_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SMAX_asimdsame_only, //!< <a href="../target/aarch64/SMAX_advsimd.html#SMAX_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_SMAXP_asimdsame_only, //!< <a href="../target/aarch64/SMAXP_advsimd.html#SMAXP_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_SMAXV_asimdall_only, //!< <a href="../target/aarch64/SMAXV_advsimd.html#SMAXV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SMIN_asimdsame_only, //!< <a href="../target/aarch64/SMIN_advsimd.html#SMIN_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_SMINP_asimdsame_only, //!< <a href="../target/aarch64/SMINP_advsimd.html#SMINP_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_SMINV_asimdall_only, //!< <a href="../target/aarch64/SMINV_advsimd.html#SMINV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_SMLAL_asimdelem_L, //!< <a href="../target/aarch64/SMLAL_advsimd_elt.html#SMLAL_asimdelem_L">Vector</a>
  AMED_AARCH64_ENCODING_SMLAL_asimddiff_L, //!< <a href="../target/aarch64/SMLAL_advsimd_vec.html#SMLAL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_SMLSL_asimdelem_L, //!< <a href="../target/aarch64/SMLSL_advsimd_elt.html#SMLSL_asimdelem_L">Vector</a>
  AMED_AARCH64_ENCODING_SMLSL_asimddiff_L, //!< <a href="../target/aarch64/SMLSL_advsimd_vec.html#SMLSL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_SMMLA_asimdsame2_G, //!< <a href="../target/aarch64/SMMLA_advsimd_vec.html#SMMLA_asimdsame2_G">Vector</a>
  AMED_AARCH64_ENCODING_SMOV_asimdins_W_w, //!< <a href="../target/aarch64/SMOV_advsimd.html#SMOV_asimdins_W_w">32-bit</a>
  AMED_AARCH64_ENCODING_SMOV_asimdins_X_x, //!< <a href="../target/aarch64/SMOV_advsimd.html#SMOV_asimdins_X_x">64-reg,SMOV-64-reg</a>
  AMED_AARCH64_ENCODING_SMULL_asimdelem_L, //!< <a href="../target/aarch64/SMULL_advsimd_elt.html#SMULL_asimdelem_L">Vector</a>
  AMED_AARCH64_ENCODING_SMULL_asimddiff_L, //!< <a href="../target/aarch64/SMULL_advsimd_vec.html#SMULL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_SQABS_asisdmisc_R, //!< <a href="../target/aarch64/SQABS_advsimd.html#SQABS_asisdmisc_R">Scalar</a>
  AMED_AARCH64_ENCODING_SQABS_asimdmisc_R, //!< <a href="../target/aarch64/SQABS_advsimd.html#SQABS_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_SQADD_asisdsame_only, //!< <a href="../target/aarch64/SQADD_advsimd.html#SQADD_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_SQADD_asimdsame_only, //!< <a href="../target/aarch64/SQADD_advsimd.html#SQADD_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_SQDMLAL_asisdelem_L, //!< <a href="../target/aarch64/SQDMLAL_advsimd_elt.html#SQDMLAL_asisdelem_L">Scalar</a>
  AMED_AARCH64_ENCODING_SQDMLAL_asimdelem_L, //!< <a href="../target/aarch64/SQDMLAL_advsimd_elt.html#SQDMLAL_asimdelem_L">Vector</a>
  AMED_AARCH64_ENCODING_SQDMLAL_asisddiff_only, //!< <a href="../target/aarch64/SQDMLAL_advsimd_vec.html#SQDMLAL_asisddiff_only">Scalar</a>
  AMED_AARCH64_ENCODING_SQDMLAL_asimddiff_L, //!< <a href="../target/aarch64/SQDMLAL_advsimd_vec.html#SQDMLAL_asimddiff_L">Vector</a>
  AMED_AARCH64_ENCODING_SQDMLSL_asisdelem_L, //!< <a href="../target/aarch64/SQDMLSL_advsimd_elt.html#SQDMLSL_asisdelem_L">Scalar</a>
  AMED_AARCH64_ENCODING_SQDMLSL_asimdelem_L, //!< <a href="../target/aarch64/SQDMLSL_advsimd_elt.html#SQDMLSL_asimdelem_L">Vector</a>
  AMED_AARCH64_ENCODING_SQDMLSL_asisddiff_only, //!< <a href="../target/aarch64/SQDMLSL_advsimd_vec.html#SQDMLSL_asisddiff_only">Scalar</a>
  AMED_AARCH64_ENCODING_SQDMLSL_asimddiff_L, //!< <a href="../target/aarch64/SQDMLSL_advsimd_vec.html#SQDMLSL_asimddiff_L">Vector</a>
  AMED_AARCH64_ENCODING_SQDMULH_asisdelem_R, //!< <a href="../target/aarch64/SQDMULH_advsimd_elt.html#SQDMULH_asisdelem_R">Scalar</a>
  AMED_AARCH64_ENCODING_SQDMULH_asimdelem_R, //!< <a href="../target/aarch64/SQDMULH_advsimd_elt.html#SQDMULH_asimdelem_R">Vector</a>
  AMED_AARCH64_ENCODING_SQDMULH_asisdsame_only, //!< <a href="../target/aarch64/SQDMULH_advsimd_vec.html#SQDMULH_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_SQDMULH_asimdsame_only, //!< <a href="../target/aarch64/SQDMULH_advsimd_vec.html#SQDMULH_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_SQDMULL_asisdelem_L, //!< <a href="../target/aarch64/SQDMULL_advsimd_elt.html#SQDMULL_asisdelem_L">Scalar</a>
  AMED_AARCH64_ENCODING_SQDMULL_asimdelem_L, //!< <a href="../target/aarch64/SQDMULL_advsimd_elt.html#SQDMULL_asimdelem_L">Vector</a>
  AMED_AARCH64_ENCODING_SQDMULL_asisddiff_only, //!< <a href="../target/aarch64/SQDMULL_advsimd_vec.html#SQDMULL_asisddiff_only">Scalar</a>
  AMED_AARCH64_ENCODING_SQDMULL_asimddiff_L, //!< <a href="../target/aarch64/SQDMULL_advsimd_vec.html#SQDMULL_asimddiff_L">Vector</a>
  AMED_AARCH64_ENCODING_SQNEG_asisdmisc_R, //!< <a href="../target/aarch64/SQNEG_advsimd.html#SQNEG_asisdmisc_R">Scalar</a>
  AMED_AARCH64_ENCODING_SQNEG_asimdmisc_R, //!< <a href="../target/aarch64/SQNEG_advsimd.html#SQNEG_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_SQRDMLAH_asisdelem_R, //!< <a href="../target/aarch64/SQRDMLAH_advsimd_elt.html#SQRDMLAH_asisdelem_R">Scalar</a>
  AMED_AARCH64_ENCODING_SQRDMLAH_asimdelem_R, //!< <a href="../target/aarch64/SQRDMLAH_advsimd_elt.html#SQRDMLAH_asimdelem_R">Vector</a>
  AMED_AARCH64_ENCODING_SQRDMLAH_asisdsame2_only, //!< <a href="../target/aarch64/SQRDMLAH_advsimd_vec.html#SQRDMLAH_asisdsame2_only">Scalar</a>
  AMED_AARCH64_ENCODING_SQRDMLAH_asimdsame2_only, //!< <a href="../target/aarch64/SQRDMLAH_advsimd_vec.html#SQRDMLAH_asimdsame2_only">Vector</a>
  AMED_AARCH64_ENCODING_SQRDMLSH_asisdelem_R, //!< <a href="../target/aarch64/SQRDMLSH_advsimd_elt.html#SQRDMLSH_asisdelem_R">Scalar</a>
  AMED_AARCH64_ENCODING_SQRDMLSH_asimdelem_R, //!< <a href="../target/aarch64/SQRDMLSH_advsimd_elt.html#SQRDMLSH_asimdelem_R">Vector</a>
  AMED_AARCH64_ENCODING_SQRDMLSH_asisdsame2_only, //!< <a href="../target/aarch64/SQRDMLSH_advsimd_vec.html#SQRDMLSH_asisdsame2_only">Scalar</a>
  AMED_AARCH64_ENCODING_SQRDMLSH_asimdsame2_only, //!< <a href="../target/aarch64/SQRDMLSH_advsimd_vec.html#SQRDMLSH_asimdsame2_only">Vector</a>
  AMED_AARCH64_ENCODING_SQRDMULH_asisdelem_R, //!< <a href="../target/aarch64/SQRDMULH_advsimd_elt.html#SQRDMULH_asisdelem_R">Scalar</a>
  AMED_AARCH64_ENCODING_SQRDMULH_asimdelem_R, //!< <a href="../target/aarch64/SQRDMULH_advsimd_elt.html#SQRDMULH_asimdelem_R">Vector</a>
  AMED_AARCH64_ENCODING_SQRDMULH_asisdsame_only, //!< <a href="../target/aarch64/SQRDMULH_advsimd_vec.html#SQRDMULH_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_SQRDMULH_asimdsame_only, //!< <a href="../target/aarch64/SQRDMULH_advsimd_vec.html#SQRDMULH_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_SQRSHL_asisdsame_only, //!< <a href="../target/aarch64/SQRSHL_advsimd.html#SQRSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_SQRSHL_asimdsame_only, //!< <a href="../target/aarch64/SQRSHL_advsimd.html#SQRSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_SQRSHRN_asisdshf_N, //!< <a href="../target/aarch64/SQRSHRN_advsimd.html#SQRSHRN_asisdshf_N">Scalar</a>
  AMED_AARCH64_ENCODING_SQRSHRN_asimdshf_N, //!< <a href="../target/aarch64/SQRSHRN_advsimd.html#SQRSHRN_asimdshf_N">Vector</a>
  AMED_AARCH64_ENCODING_SQRSHRUN_asisdshf_N, //!< <a href="../target/aarch64/SQRSHRUN_advsimd.html#SQRSHRUN_asisdshf_N">Scalar</a>
  AMED_AARCH64_ENCODING_SQRSHRUN_asimdshf_N, //!< <a href="../target/aarch64/SQRSHRUN_advsimd.html#SQRSHRUN_asimdshf_N">Vector</a>
  AMED_AARCH64_ENCODING_SQSHL_asisdshf_R, //!< <a href="../target/aarch64/SQSHL_advsimd_imm.html#SQSHL_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_SQSHL_asimdshf_R, //!< <a href="../target/aarch64/SQSHL_advsimd_imm.html#SQSHL_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_SQSHL_asisdsame_only, //!< <a href="../target/aarch64/SQSHL_advsimd_reg.html#SQSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_SQSHL_asimdsame_only, //!< <a href="../target/aarch64/SQSHL_advsimd_reg.html#SQSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_SQSHLU_asisdshf_R, //!< <a href="../target/aarch64/SQSHLU_advsimd.html#SQSHLU_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_SQSHLU_asimdshf_R, //!< <a href="../target/aarch64/SQSHLU_advsimd.html#SQSHLU_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_SQSHRN_asisdshf_N, //!< <a href="../target/aarch64/SQSHRN_advsimd.html#SQSHRN_asisdshf_N">Scalar</a>
  AMED_AARCH64_ENCODING_SQSHRN_asimdshf_N, //!< <a href="../target/aarch64/SQSHRN_advsimd.html#SQSHRN_asimdshf_N">Vector</a>
  AMED_AARCH64_ENCODING_SQSHRUN_asisdshf_N, //!< <a href="../target/aarch64/SQSHRUN_advsimd.html#SQSHRUN_asisdshf_N">Scalar</a>
  AMED_AARCH64_ENCODING_SQSHRUN_asimdshf_N, //!< <a href="../target/aarch64/SQSHRUN_advsimd.html#SQSHRUN_asimdshf_N">Vector</a>
  AMED_AARCH64_ENCODING_SQSUB_asisdsame_only, //!< <a href="../target/aarch64/SQSUB_advsimd.html#SQSUB_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_SQSUB_asimdsame_only, //!< <a href="../target/aarch64/SQSUB_advsimd.html#SQSUB_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_SQXTN_asisdmisc_N, //!< <a href="../target/aarch64/SQXTN_advsimd.html#SQXTN_asisdmisc_N">Scalar</a>
  AMED_AARCH64_ENCODING_SQXTN_asimdmisc_N, //!< <a href="../target/aarch64/SQXTN_advsimd.html#SQXTN_asimdmisc_N">Vector</a>
  AMED_AARCH64_ENCODING_SQXTUN_asisdmisc_N, //!< <a href="../target/aarch64/SQXTUN_advsimd.html#SQXTUN_asisdmisc_N">Scalar</a>
  AMED_AARCH64_ENCODING_SQXTUN_asimdmisc_N, //!< <a href="../target/aarch64/SQXTUN_advsimd.html#SQXTUN_asimdmisc_N">Vector</a>
  AMED_AARCH64_ENCODING_SRHADD_asimdsame_only, //!< <a href="../target/aarch64/SRHADD_advsimd.html#SRHADD_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_SRI_asisdshf_R, //!< <a href="../target/aarch64/SRI_advsimd.html#SRI_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_SRI_asimdshf_R, //!< <a href="../target/aarch64/SRI_advsimd.html#SRI_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_SRSHL_asisdsame_only, //!< <a href="../target/aarch64/SRSHL_advsimd.html#SRSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_SRSHL_asimdsame_only, //!< <a href="../target/aarch64/SRSHL_advsimd.html#SRSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_SRSHR_asisdshf_R, //!< <a href="../target/aarch64/SRSHR_advsimd.html#SRSHR_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_SRSHR_asimdshf_R, //!< <a href="../target/aarch64/SRSHR_advsimd.html#SRSHR_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_SRSRA_asisdshf_R, //!< <a href="../target/aarch64/SRSRA_advsimd.html#SRSRA_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_SRSRA_asimdshf_R, //!< <a href="../target/aarch64/SRSRA_advsimd.html#SRSRA_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_SSHL_asisdsame_only, //!< <a href="../target/aarch64/SSHL_advsimd.html#SSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_SSHL_asimdsame_only, //!< <a href="../target/aarch64/SSHL_advsimd.html#SSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_SSHLL_asimdshf_L, //!< <a href="../target/aarch64/SSHLL_advsimd.html#SSHLL_asimdshf_L">Vector</a>
  AMED_AARCH64_ENCODING_SSHR_asisdshf_R, //!< <a href="../target/aarch64/SSHR_advsimd.html#SSHR_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_SSHR_asimdshf_R, //!< <a href="../target/aarch64/SSHR_advsimd.html#SSHR_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_SSRA_asisdshf_R, //!< <a href="../target/aarch64/SSRA_advsimd.html#SSRA_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_SSRA_asimdshf_R, //!< <a href="../target/aarch64/SSRA_advsimd.html#SSRA_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_SSUBL_asimddiff_L, //!< <a href="../target/aarch64/SSUBL_advsimd.html#SSUBL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_SSUBW_asimddiff_W, //!< <a href="../target/aarch64/SSUBW_advsimd.html#SSUBW_asimddiff_W">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_ST1_asisdlse_R1_1v, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#ST1_asisdlse_R1_1v">One register</a>
  AMED_AARCH64_ENCODING_ST1_asisdlse_R2_2v, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#ST1_asisdlse_R2_2v">Two registers</a>
  AMED_AARCH64_ENCODING_ST1_asisdlse_R3_3v, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#ST1_asisdlse_R3_3v">Three registers</a>
  AMED_AARCH64_ENCODING_ST1_asisdlse_R4_4v, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#ST1_asisdlse_R4_4v">Four registers</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsep_I1_i1, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#ST1_asisdlsep_I1_i1">One register, immediate offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsep_R1_r1, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#ST1_asisdlsep_R1_r1">One register, register offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsep_I2_i2, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#ST1_asisdlsep_I2_i2">Two registers, immediate offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsep_R2_r2, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#ST1_asisdlsep_R2_r2">Two registers, register offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsep_I3_i3, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#ST1_asisdlsep_I3_i3">Three registers, immediate offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsep_R3_r3, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#ST1_asisdlsep_R3_r3">Three registers, register offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsep_I4_i4, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#ST1_asisdlsep_I4_i4">Four registers, immediate offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsep_R4_r4, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#ST1_asisdlsep_R4_r4">Four registers, register offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlso_B1_1b, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#ST1_asisdlso_B1_1b">8-bit</a>
  AMED_AARCH64_ENCODING_ST1_asisdlso_H1_1h, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#ST1_asisdlso_H1_1h">16-bit</a>
  AMED_AARCH64_ENCODING_ST1_asisdlso_S1_1s, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#ST1_asisdlso_S1_1s">32-bit</a>
  AMED_AARCH64_ENCODING_ST1_asisdlso_D1_1d, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#ST1_asisdlso_D1_1d">64-bit</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsop_B1_i1b, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#ST1_asisdlsop_B1_i1b">8-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsop_BX1_r1b, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#ST1_asisdlsop_BX1_r1b">8-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsop_H1_i1h, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#ST1_asisdlsop_H1_i1h">16-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsop_HX1_r1h, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#ST1_asisdlsop_HX1_r1h">16-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsop_S1_i1s, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#ST1_asisdlsop_S1_i1s">32-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsop_SX1_r1s, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#ST1_asisdlsop_SX1_r1s">32-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsop_D1_i1d, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#ST1_asisdlsop_D1_i1d">64-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST1_asisdlsop_DX1_r1d, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#ST1_asisdlsop_DX1_r1d">64-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST2_asisdlse_R2, //!< <a href="../target/aarch64/ST2_advsimd_mult.html#ST2_asisdlse_R2">No offset</a>
  AMED_AARCH64_ENCODING_ST2_asisdlsep_I2_i, //!< <a href="../target/aarch64/ST2_advsimd_mult.html#ST2_asisdlsep_I2_i">Immediate offset</a>
  AMED_AARCH64_ENCODING_ST2_asisdlsep_R2_r, //!< <a href="../target/aarch64/ST2_advsimd_mult.html#ST2_asisdlsep_R2_r">Register offset</a>
  AMED_AARCH64_ENCODING_ST2_asisdlso_B2_2b, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#ST2_asisdlso_B2_2b">8-bit</a>
  AMED_AARCH64_ENCODING_ST2_asisdlso_H2_2h, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#ST2_asisdlso_H2_2h">16-bit</a>
  AMED_AARCH64_ENCODING_ST2_asisdlso_S2_2s, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#ST2_asisdlso_S2_2s">32-bit</a>
  AMED_AARCH64_ENCODING_ST2_asisdlso_D2_2d, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#ST2_asisdlso_D2_2d">64-bit</a>
  AMED_AARCH64_ENCODING_ST2_asisdlsop_B2_i2b, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#ST2_asisdlsop_B2_i2b">8-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST2_asisdlsop_BX2_r2b, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#ST2_asisdlsop_BX2_r2b">8-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST2_asisdlsop_H2_i2h, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#ST2_asisdlsop_H2_i2h">16-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST2_asisdlsop_HX2_r2h, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#ST2_asisdlsop_HX2_r2h">16-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST2_asisdlsop_S2_i2s, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#ST2_asisdlsop_S2_i2s">32-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST2_asisdlsop_SX2_r2s, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#ST2_asisdlsop_SX2_r2s">32-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST2_asisdlsop_D2_i2d, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#ST2_asisdlsop_D2_i2d">64-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST2_asisdlsop_DX2_r2d, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#ST2_asisdlsop_DX2_r2d">64-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST3_asisdlse_R3, //!< <a href="../target/aarch64/ST3_advsimd_mult.html#ST3_asisdlse_R3">No offset</a>
  AMED_AARCH64_ENCODING_ST3_asisdlsep_I3_i, //!< <a href="../target/aarch64/ST3_advsimd_mult.html#ST3_asisdlsep_I3_i">Immediate offset</a>
  AMED_AARCH64_ENCODING_ST3_asisdlsep_R3_r, //!< <a href="../target/aarch64/ST3_advsimd_mult.html#ST3_asisdlsep_R3_r">Register offset</a>
  AMED_AARCH64_ENCODING_ST3_asisdlso_B3_3b, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#ST3_asisdlso_B3_3b">8-bit</a>
  AMED_AARCH64_ENCODING_ST3_asisdlso_H3_3h, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#ST3_asisdlso_H3_3h">16-bit</a>
  AMED_AARCH64_ENCODING_ST3_asisdlso_S3_3s, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#ST3_asisdlso_S3_3s">32-bit</a>
  AMED_AARCH64_ENCODING_ST3_asisdlso_D3_3d, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#ST3_asisdlso_D3_3d">64-bit</a>
  AMED_AARCH64_ENCODING_ST3_asisdlsop_B3_i3b, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#ST3_asisdlsop_B3_i3b">8-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST3_asisdlsop_BX3_r3b, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#ST3_asisdlsop_BX3_r3b">8-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST3_asisdlsop_H3_i3h, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#ST3_asisdlsop_H3_i3h">16-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST3_asisdlsop_HX3_r3h, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#ST3_asisdlsop_HX3_r3h">16-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST3_asisdlsop_S3_i3s, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#ST3_asisdlsop_S3_i3s">32-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST3_asisdlsop_SX3_r3s, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#ST3_asisdlsop_SX3_r3s">32-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST3_asisdlsop_D3_i3d, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#ST3_asisdlsop_D3_i3d">64-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST3_asisdlsop_DX3_r3d, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#ST3_asisdlsop_DX3_r3d">64-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST4_asisdlse_R4, //!< <a href="../target/aarch64/ST4_advsimd_mult.html#ST4_asisdlse_R4">No offset</a>
  AMED_AARCH64_ENCODING_ST4_asisdlsep_I4_i, //!< <a href="../target/aarch64/ST4_advsimd_mult.html#ST4_asisdlsep_I4_i">Immediate offset</a>
  AMED_AARCH64_ENCODING_ST4_asisdlsep_R4_r, //!< <a href="../target/aarch64/ST4_advsimd_mult.html#ST4_asisdlsep_R4_r">Register offset</a>
  AMED_AARCH64_ENCODING_ST4_asisdlso_B4_4b, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#ST4_asisdlso_B4_4b">8-bit</a>
  AMED_AARCH64_ENCODING_ST4_asisdlso_H4_4h, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#ST4_asisdlso_H4_4h">16-bit</a>
  AMED_AARCH64_ENCODING_ST4_asisdlso_S4_4s, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#ST4_asisdlso_S4_4s">32-bit</a>
  AMED_AARCH64_ENCODING_ST4_asisdlso_D4_4d, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#ST4_asisdlso_D4_4d">64-bit</a>
  AMED_AARCH64_ENCODING_ST4_asisdlsop_B4_i4b, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#ST4_asisdlsop_B4_i4b">8-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST4_asisdlsop_BX4_r4b, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#ST4_asisdlsop_BX4_r4b">8-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST4_asisdlsop_H4_i4h, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#ST4_asisdlsop_H4_i4h">16-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST4_asisdlsop_HX4_r4h, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#ST4_asisdlsop_HX4_r4h">16-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST4_asisdlsop_S4_i4s, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#ST4_asisdlsop_S4_i4s">32-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST4_asisdlsop_SX4_r4s, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#ST4_asisdlsop_SX4_r4s">32-bit, register offset</a>
  AMED_AARCH64_ENCODING_ST4_asisdlsop_D4_i4d, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#ST4_asisdlsop_D4_i4d">64-bit, immediate offset</a>
  AMED_AARCH64_ENCODING_ST4_asisdlsop_DX4_r4d, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#ST4_asisdlsop_DX4_r4d">64-bit, register offset</a>
  AMED_AARCH64_ENCODING_STNP_S_ldstnapair_offs, //!< <a href="../target/aarch64/STNP_fpsimd.html#STNP_S_ldstnapair_offs">32-bit</a>
  AMED_AARCH64_ENCODING_STNP_D_ldstnapair_offs, //!< <a href="../target/aarch64/STNP_fpsimd.html#STNP_D_ldstnapair_offs">64-bit</a>
  AMED_AARCH64_ENCODING_STNP_Q_ldstnapair_offs, //!< <a href="../target/aarch64/STNP_fpsimd.html#STNP_Q_ldstnapair_offs">128-bit</a>
  AMED_AARCH64_ENCODING_STP_S_ldstpair_post, //!< <a href="../target/aarch64/STP_fpsimd.html#STP_S_ldstpair_post">32-bit</a>
  AMED_AARCH64_ENCODING_STP_D_ldstpair_post, //!< <a href="../target/aarch64/STP_fpsimd.html#STP_D_ldstpair_post">64-bit</a>
  AMED_AARCH64_ENCODING_STP_Q_ldstpair_post, //!< <a href="../target/aarch64/STP_fpsimd.html#STP_Q_ldstpair_post">128-bit</a>
  AMED_AARCH64_ENCODING_STP_S_ldstpair_pre, //!< <a href="../target/aarch64/STP_fpsimd.html#STP_S_ldstpair_pre">32-bit</a>
  AMED_AARCH64_ENCODING_STP_D_ldstpair_pre, //!< <a href="../target/aarch64/STP_fpsimd.html#STP_D_ldstpair_pre">64-bit</a>
  AMED_AARCH64_ENCODING_STP_Q_ldstpair_pre, //!< <a href="../target/aarch64/STP_fpsimd.html#STP_Q_ldstpair_pre">128-bit</a>
  AMED_AARCH64_ENCODING_STP_S_ldstpair_off, //!< <a href="../target/aarch64/STP_fpsimd.html#STP_S_ldstpair_off">32-bit</a>
  AMED_AARCH64_ENCODING_STP_D_ldstpair_off, //!< <a href="../target/aarch64/STP_fpsimd.html#STP_D_ldstpair_off">64-bit</a>
  AMED_AARCH64_ENCODING_STP_Q_ldstpair_off, //!< <a href="../target/aarch64/STP_fpsimd.html#STP_Q_ldstpair_off">128-bit</a>
  AMED_AARCH64_ENCODING_STR_B_ldst_immpost, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_B_ldst_immpost">8-bit</a>
  AMED_AARCH64_ENCODING_STR_H_ldst_immpost, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_H_ldst_immpost">16-bit</a>
  AMED_AARCH64_ENCODING_STR_S_ldst_immpost, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_S_ldst_immpost">32-bit</a>
  AMED_AARCH64_ENCODING_STR_D_ldst_immpost, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_D_ldst_immpost">64-bit</a>
  AMED_AARCH64_ENCODING_STR_Q_ldst_immpost, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_Q_ldst_immpost">128-bit</a>
  AMED_AARCH64_ENCODING_STR_B_ldst_immpre, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_B_ldst_immpre">8-bit</a>
  AMED_AARCH64_ENCODING_STR_H_ldst_immpre, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_H_ldst_immpre">16-bit</a>
  AMED_AARCH64_ENCODING_STR_S_ldst_immpre, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_S_ldst_immpre">32-bit</a>
  AMED_AARCH64_ENCODING_STR_D_ldst_immpre, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_D_ldst_immpre">64-bit</a>
  AMED_AARCH64_ENCODING_STR_Q_ldst_immpre, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_Q_ldst_immpre">128-bit</a>
  AMED_AARCH64_ENCODING_STR_B_ldst_pos, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_B_ldst_pos">8-bit</a>
  AMED_AARCH64_ENCODING_STR_H_ldst_pos, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_H_ldst_pos">16-bit</a>
  AMED_AARCH64_ENCODING_STR_S_ldst_pos, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_S_ldst_pos">32-bit</a>
  AMED_AARCH64_ENCODING_STR_D_ldst_pos, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_D_ldst_pos">64-bit</a>
  AMED_AARCH64_ENCODING_STR_Q_ldst_pos, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#STR_Q_ldst_pos">128-bit</a>
  AMED_AARCH64_ENCODING_STR_B_ldst_regoff, //!< <a href="../target/aarch64/STR_reg_fpsimd.html#STR_B_ldst_regoff">8-fsreg,STR-8-fsreg</a>
  AMED_AARCH64_ENCODING_STR_BL_ldst_regoff, //!< <a href="../target/aarch64/STR_reg_fpsimd.html#STR_BL_ldst_regoff">8-fsreg,STR-8-fsreg</a>
  AMED_AARCH64_ENCODING_STR_H_ldst_regoff, //!< <a href="../target/aarch64/STR_reg_fpsimd.html#STR_H_ldst_regoff">16-fsreg,STR-16-fsreg</a>
  AMED_AARCH64_ENCODING_STR_S_ldst_regoff, //!< <a href="../target/aarch64/STR_reg_fpsimd.html#STR_S_ldst_regoff">32-fsreg,STR-32-fsreg</a>
  AMED_AARCH64_ENCODING_STR_D_ldst_regoff, //!< <a href="../target/aarch64/STR_reg_fpsimd.html#STR_D_ldst_regoff">64-fsreg,STR-64-fsreg</a>
  AMED_AARCH64_ENCODING_STR_Q_ldst_regoff, //!< <a href="../target/aarch64/STR_reg_fpsimd.html#STR_Q_ldst_regoff">128-fsreg,STR-128-fsreg</a>
  AMED_AARCH64_ENCODING_STUR_B_ldst_unscaled, //!< <a href="../target/aarch64/STUR_fpsimd.html#STUR_B_ldst_unscaled">8-bit</a>
  AMED_AARCH64_ENCODING_STUR_H_ldst_unscaled, //!< <a href="../target/aarch64/STUR_fpsimd.html#STUR_H_ldst_unscaled">16-bit</a>
  AMED_AARCH64_ENCODING_STUR_S_ldst_unscaled, //!< <a href="../target/aarch64/STUR_fpsimd.html#STUR_S_ldst_unscaled">32-bit</a>
  AMED_AARCH64_ENCODING_STUR_D_ldst_unscaled, //!< <a href="../target/aarch64/STUR_fpsimd.html#STUR_D_ldst_unscaled">64-bit</a>
  AMED_AARCH64_ENCODING_STUR_Q_ldst_unscaled, //!< <a href="../target/aarch64/STUR_fpsimd.html#STUR_Q_ldst_unscaled">128-bit</a>
  AMED_AARCH64_ENCODING_SUB_asisdsame_only, //!< <a href="../target/aarch64/SUB_advsimd.html#SUB_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_SUB_asimdsame_only, //!< <a href="../target/aarch64/SUB_advsimd.html#SUB_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_SUBHN_asimddiff_N, //!< <a href="../target/aarch64/SUBHN_advsimd.html#SUBHN_asimddiff_N">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_SUDOT_asimdelem_D, //!< <a href="../target/aarch64/SUDOT_advsimd_elt.html#SUDOT_asimdelem_D">Vector</a>
  AMED_AARCH64_ENCODING_SUQADD_asisdmisc_R, //!< <a href="../target/aarch64/SUQADD_advsimd.html#SUQADD_asisdmisc_R">Scalar</a>
  AMED_AARCH64_ENCODING_SUQADD_asimdmisc_R, //!< <a href="../target/aarch64/SUQADD_advsimd.html#SUQADD_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_TBL_asimdtbl_L2_2, //!< <a href="../target/aarch64/TBL_advsimd.html#TBL_asimdtbl_L2_2">Two register table</a>
  AMED_AARCH64_ENCODING_TBL_asimdtbl_L3_3, //!< <a href="../target/aarch64/TBL_advsimd.html#TBL_asimdtbl_L3_3">Three register table</a>
  AMED_AARCH64_ENCODING_TBL_asimdtbl_L4_4, //!< <a href="../target/aarch64/TBL_advsimd.html#TBL_asimdtbl_L4_4">Four register table</a>
  AMED_AARCH64_ENCODING_TBL_asimdtbl_L1_1, //!< <a href="../target/aarch64/TBL_advsimd.html#TBL_asimdtbl_L1_1">Single register table</a>
  AMED_AARCH64_ENCODING_TBX_asimdtbl_L2_2, //!< <a href="../target/aarch64/TBX_advsimd.html#TBX_asimdtbl_L2_2">Two register table</a>
  AMED_AARCH64_ENCODING_TBX_asimdtbl_L3_3, //!< <a href="../target/aarch64/TBX_advsimd.html#TBX_asimdtbl_L3_3">Three register table</a>
  AMED_AARCH64_ENCODING_TBX_asimdtbl_L4_4, //!< <a href="../target/aarch64/TBX_advsimd.html#TBX_asimdtbl_L4_4">Four register table</a>
  AMED_AARCH64_ENCODING_TBX_asimdtbl_L1_1, //!< <a href="../target/aarch64/TBX_advsimd.html#TBX_asimdtbl_L1_1">Single register table</a>
  AMED_AARCH64_ENCODING_TRN1_asimdperm_only, //!< <a href="../target/aarch64/TRN1_advsimd.html#TRN1_asimdperm_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_TRN2_asimdperm_only, //!< <a href="../target/aarch64/TRN2_advsimd.html#TRN2_asimdperm_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_UABA_asimdsame_only, //!< <a href="../target/aarch64/UABA_advsimd.html#UABA_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_UABAL_asimddiff_L, //!< <a href="../target/aarch64/UABAL_advsimd.html#UABAL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_UABD_asimdsame_only, //!< <a href="../target/aarch64/UABD_advsimd.html#UABD_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_UABDL_asimddiff_L, //!< <a href="../target/aarch64/UABDL_advsimd.html#UABDL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_UADALP_asimdmisc_P, //!< <a href="../target/aarch64/UADALP_advsimd.html#UADALP_asimdmisc_P">Vector</a>
  AMED_AARCH64_ENCODING_UADDL_asimddiff_L, //!< <a href="../target/aarch64/UADDL_advsimd.html#UADDL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_UADDLP_asimdmisc_P, //!< <a href="../target/aarch64/UADDLP_advsimd.html#UADDLP_asimdmisc_P">Vector</a>
  AMED_AARCH64_ENCODING_UADDLV_asimdall_only, //!< <a href="../target/aarch64/UADDLV_advsimd.html#UADDLV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_UADDW_asimddiff_W, //!< <a href="../target/aarch64/UADDW_advsimd.html#UADDW_asimddiff_W">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_UCVTF_asisdshf_C, //!< <a href="../target/aarch64/UCVTF_advsimd_fix.html#UCVTF_asisdshf_C">Scalar</a>
  AMED_AARCH64_ENCODING_UCVTF_asimdshf_C, //!< <a href="../target/aarch64/UCVTF_advsimd_fix.html#UCVTF_asimdshf_C">Vector</a>
  AMED_AARCH64_ENCODING_UCVTF_asisdmiscfp16_R, //!< <a href="../target/aarch64/UCVTF_advsimd_int.html#UCVTF_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_ENCODING_UCVTF_asisdmisc_R, //!< <a href="../target/aarch64/UCVTF_advsimd_int.html#UCVTF_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_UCVTF_asimdmiscfp16_R, //!< <a href="../target/aarch64/UCVTF_advsimd_int.html#UCVTF_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_ENCODING_UCVTF_asimdmisc_R, //!< <a href="../target/aarch64/UCVTF_advsimd_int.html#UCVTF_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_ENCODING_UCVTF_H32_float2fix, //!< <a href="../target/aarch64/UCVTF_float_fix.html#UCVTF_H32_float2fix">32-bit to half-precision</a>
  AMED_AARCH64_ENCODING_UCVTF_S32_float2fix, //!< <a href="../target/aarch64/UCVTF_float_fix.html#UCVTF_S32_float2fix">32-bit to single-precision</a>
  AMED_AARCH64_ENCODING_UCVTF_D32_float2fix, //!< <a href="../target/aarch64/UCVTF_float_fix.html#UCVTF_D32_float2fix">32-bit to double-precision</a>
  AMED_AARCH64_ENCODING_UCVTF_H64_float2fix, //!< <a href="../target/aarch64/UCVTF_float_fix.html#UCVTF_H64_float2fix">64-bit to half-precision</a>
  AMED_AARCH64_ENCODING_UCVTF_S64_float2fix, //!< <a href="../target/aarch64/UCVTF_float_fix.html#UCVTF_S64_float2fix">64-bit to single-precision</a>
  AMED_AARCH64_ENCODING_UCVTF_D64_float2fix, //!< <a href="../target/aarch64/UCVTF_float_fix.html#UCVTF_D64_float2fix">64-bit to double-precision</a>
  AMED_AARCH64_ENCODING_UCVTF_H32_float2int, //!< <a href="../target/aarch64/UCVTF_float_int.html#UCVTF_H32_float2int">32-bit to half-precision</a>
  AMED_AARCH64_ENCODING_UCVTF_S32_float2int, //!< <a href="../target/aarch64/UCVTF_float_int.html#UCVTF_S32_float2int">32-bit to single-precision</a>
  AMED_AARCH64_ENCODING_UCVTF_D32_float2int, //!< <a href="../target/aarch64/UCVTF_float_int.html#UCVTF_D32_float2int">32-bit to double-precision</a>
  AMED_AARCH64_ENCODING_UCVTF_H64_float2int, //!< <a href="../target/aarch64/UCVTF_float_int.html#UCVTF_H64_float2int">64-bit to half-precision</a>
  AMED_AARCH64_ENCODING_UCVTF_S64_float2int, //!< <a href="../target/aarch64/UCVTF_float_int.html#UCVTF_S64_float2int">64-bit to single-precision</a>
  AMED_AARCH64_ENCODING_UCVTF_D64_float2int, //!< <a href="../target/aarch64/UCVTF_float_int.html#UCVTF_D64_float2int">64-bit to double-precision</a>
  AMED_AARCH64_ENCODING_UDOT_asimdelem_D, //!< <a href="../target/aarch64/UDOT_advsimd_elt.html#UDOT_asimdelem_D">Vector</a>
  AMED_AARCH64_ENCODING_UDOT_asimdsame2_D, //!< <a href="../target/aarch64/UDOT_advsimd_vec.html#UDOT_asimdsame2_D">Vector</a>
  AMED_AARCH64_ENCODING_UHADD_asimdsame_only, //!< <a href="../target/aarch64/UHADD_advsimd.html#UHADD_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_UHSUB_asimdsame_only, //!< <a href="../target/aarch64/UHSUB_advsimd.html#UHSUB_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_UMAX_asimdsame_only, //!< <a href="../target/aarch64/UMAX_advsimd.html#UMAX_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_UMAXP_asimdsame_only, //!< <a href="../target/aarch64/UMAXP_advsimd.html#UMAXP_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_UMAXV_asimdall_only, //!< <a href="../target/aarch64/UMAXV_advsimd.html#UMAXV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_UMIN_asimdsame_only, //!< <a href="../target/aarch64/UMIN_advsimd.html#UMIN_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_UMINP_asimdsame_only, //!< <a href="../target/aarch64/UMINP_advsimd.html#UMINP_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_UMINV_asimdall_only, //!< <a href="../target/aarch64/UMINV_advsimd.html#UMINV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_UMLAL_asimdelem_L, //!< <a href="../target/aarch64/UMLAL_advsimd_elt.html#UMLAL_asimdelem_L">Vector</a>
  AMED_AARCH64_ENCODING_UMLAL_asimddiff_L, //!< <a href="../target/aarch64/UMLAL_advsimd_vec.html#UMLAL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_UMLSL_asimdelem_L, //!< <a href="../target/aarch64/UMLSL_advsimd_elt.html#UMLSL_asimdelem_L">Vector</a>
  AMED_AARCH64_ENCODING_UMLSL_asimddiff_L, //!< <a href="../target/aarch64/UMLSL_advsimd_vec.html#UMLSL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_UMMLA_asimdsame2_G, //!< <a href="../target/aarch64/UMMLA_advsimd_vec.html#UMMLA_asimdsame2_G">Vector</a>
  AMED_AARCH64_ENCODING_UMOV_asimdins_W_w, //!< <a href="../target/aarch64/UMOV_advsimd.html#UMOV_asimdins_W_w">32-bit</a>
  AMED_AARCH64_ENCODING_UMOV_asimdins_X_x, //!< <a href="../target/aarch64/UMOV_advsimd.html#UMOV_asimdins_X_x">64-reg,UMOV-64-reg</a>
  AMED_AARCH64_ENCODING_UMULL_asimdelem_L, //!< <a href="../target/aarch64/UMULL_advsimd_elt.html#UMULL_asimdelem_L">Vector</a>
  AMED_AARCH64_ENCODING_UMULL_asimddiff_L, //!< <a href="../target/aarch64/UMULL_advsimd_vec.html#UMULL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_UQADD_asisdsame_only, //!< <a href="../target/aarch64/UQADD_advsimd.html#UQADD_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_UQADD_asimdsame_only, //!< <a href="../target/aarch64/UQADD_advsimd.html#UQADD_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_UQRSHL_asisdsame_only, //!< <a href="../target/aarch64/UQRSHL_advsimd.html#UQRSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_UQRSHL_asimdsame_only, //!< <a href="../target/aarch64/UQRSHL_advsimd.html#UQRSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_UQRSHRN_asisdshf_N, //!< <a href="../target/aarch64/UQRSHRN_advsimd.html#UQRSHRN_asisdshf_N">Scalar</a>
  AMED_AARCH64_ENCODING_UQRSHRN_asimdshf_N, //!< <a href="../target/aarch64/UQRSHRN_advsimd.html#UQRSHRN_asimdshf_N">Vector</a>
  AMED_AARCH64_ENCODING_UQSHL_asisdshf_R, //!< <a href="../target/aarch64/UQSHL_advsimd_imm.html#UQSHL_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_UQSHL_asimdshf_R, //!< <a href="../target/aarch64/UQSHL_advsimd_imm.html#UQSHL_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_UQSHL_asisdsame_only, //!< <a href="../target/aarch64/UQSHL_advsimd_reg.html#UQSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_UQSHL_asimdsame_only, //!< <a href="../target/aarch64/UQSHL_advsimd_reg.html#UQSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_UQSHRN_asisdshf_N, //!< <a href="../target/aarch64/UQSHRN_advsimd.html#UQSHRN_asisdshf_N">Scalar</a>
  AMED_AARCH64_ENCODING_UQSHRN_asimdshf_N, //!< <a href="../target/aarch64/UQSHRN_advsimd.html#UQSHRN_asimdshf_N">Vector</a>
  AMED_AARCH64_ENCODING_UQSUB_asisdsame_only, //!< <a href="../target/aarch64/UQSUB_advsimd.html#UQSUB_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_UQSUB_asimdsame_only, //!< <a href="../target/aarch64/UQSUB_advsimd.html#UQSUB_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_UQXTN_asisdmisc_N, //!< <a href="../target/aarch64/UQXTN_advsimd.html#UQXTN_asisdmisc_N">Scalar</a>
  AMED_AARCH64_ENCODING_UQXTN_asimdmisc_N, //!< <a href="../target/aarch64/UQXTN_advsimd.html#UQXTN_asimdmisc_N">Vector</a>
  AMED_AARCH64_ENCODING_URECPE_asimdmisc_R, //!< <a href="../target/aarch64/URECPE_advsimd.html#URECPE_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_URHADD_asimdsame_only, //!< <a href="../target/aarch64/URHADD_advsimd.html#URHADD_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_URSHL_asisdsame_only, //!< <a href="../target/aarch64/URSHL_advsimd.html#URSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_URSHL_asimdsame_only, //!< <a href="../target/aarch64/URSHL_advsimd.html#URSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_URSHR_asisdshf_R, //!< <a href="../target/aarch64/URSHR_advsimd.html#URSHR_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_URSHR_asimdshf_R, //!< <a href="../target/aarch64/URSHR_advsimd.html#URSHR_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_URSQRTE_asimdmisc_R, //!< <a href="../target/aarch64/URSQRTE_advsimd.html#URSQRTE_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_URSRA_asisdshf_R, //!< <a href="../target/aarch64/URSRA_advsimd.html#URSRA_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_URSRA_asimdshf_R, //!< <a href="../target/aarch64/URSRA_advsimd.html#URSRA_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_USDOT_asimdelem_D, //!< <a href="../target/aarch64/USDOT_advsimd_elt.html#USDOT_asimdelem_D">Vector</a>
  AMED_AARCH64_ENCODING_USDOT_asimdsame2_D, //!< <a href="../target/aarch64/USDOT_advsimd_vec.html#USDOT_asimdsame2_D">Vector</a>
  AMED_AARCH64_ENCODING_USHL_asisdsame_only, //!< <a href="../target/aarch64/USHL_advsimd.html#USHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_ENCODING_USHL_asimdsame_only, //!< <a href="../target/aarch64/USHL_advsimd.html#USHL_asimdsame_only">Vector</a>
  AMED_AARCH64_ENCODING_USHLL_asimdshf_L, //!< <a href="../target/aarch64/USHLL_advsimd.html#USHLL_asimdshf_L">Vector</a>
  AMED_AARCH64_ENCODING_USHR_asisdshf_R, //!< <a href="../target/aarch64/USHR_advsimd.html#USHR_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_USHR_asimdshf_R, //!< <a href="../target/aarch64/USHR_advsimd.html#USHR_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_USMMLA_asimdsame2_G, //!< <a href="../target/aarch64/USMMLA_advsimd_vec.html#USMMLA_asimdsame2_G">Vector</a>
  AMED_AARCH64_ENCODING_USQADD_asisdmisc_R, //!< <a href="../target/aarch64/USQADD_advsimd.html#USQADD_asisdmisc_R">Scalar</a>
  AMED_AARCH64_ENCODING_USQADD_asimdmisc_R, //!< <a href="../target/aarch64/USQADD_advsimd.html#USQADD_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_USRA_asisdshf_R, //!< <a href="../target/aarch64/USRA_advsimd.html#USRA_asisdshf_R">Scalar</a>
  AMED_AARCH64_ENCODING_USRA_asimdshf_R, //!< <a href="../target/aarch64/USRA_advsimd.html#USRA_asimdshf_R">Vector</a>
  AMED_AARCH64_ENCODING_USUBL_asimddiff_L, //!< <a href="../target/aarch64/USUBL_advsimd.html#USUBL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_USUBW_asimddiff_W, //!< <a href="../target/aarch64/USUBW_advsimd.html#USUBW_asimddiff_W">Three registers, not all the same type</a>
  AMED_AARCH64_ENCODING_UZP1_asimdperm_only, //!< <a href="../target/aarch64/UZP1_advsimd.html#UZP1_asimdperm_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_UZP2_asimdperm_only, //!< <a href="../target/aarch64/UZP2_advsimd.html#UZP2_asimdperm_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_XAR_VVV2_crypto3_imm6, //!< <a href="../target/aarch64/XAR_advsimd.html#XAR_VVV2_crypto3_imm6">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_XTN_asimdmisc_N, //!< <a href="../target/aarch64/XTN_advsimd.html#XTN_asimdmisc_N">Vector</a>
  AMED_AARCH64_ENCODING_ZIP1_asimdperm_only, //!< <a href="../target/aarch64/ZIP1_advsimd.html#ZIP1_asimdperm_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_ZIP2_asimdperm_only, //!< <a href="../target/aarch64/ZIP2_advsimd.html#ZIP2_asimdperm_only">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_MOV_DUP_asisdone_only, //!< <a href="../target/aarch64/MOV_DUP_advsimd_elt.html#MOV_DUP_asisdone_only">Scalar</a>
  AMED_AARCH64_ENCODING_MOV_INS_asimdins_IV_v, //!< <a href="../target/aarch64/MOV_INS_advsimd_elt.html#MOV_INS_asimdins_IV_v">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_MOV_INS_asimdins_IR_r, //!< <a href="../target/aarch64/MOV_INS_advsimd_gen.html#MOV_INS_asimdins_IR_r">Advanced SIMD</a>
  AMED_AARCH64_ENCODING_MOV_ORR_asimdsame_only, //!< <a href="../target/aarch64/MOV_ORR_advsimd_reg.html#MOV_ORR_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_ENCODING_MOV_UMOV_asimdins_W_w, //!< <a href="../target/aarch64/MOV_UMOV_advsimd.html#MOV_UMOV_asimdins_W_w">32-bit</a>
  AMED_AARCH64_ENCODING_MOV_UMOV_asimdins_X_x, //!< <a href="../target/aarch64/MOV_UMOV_advsimd.html#MOV_UMOV_asimdins_X_x">64-reg,UMOV-64-reg</a>
  AMED_AARCH64_ENCODING_MVN_NOT_asimdmisc_R, //!< <a href="../target/aarch64/MVN_NOT_advsimd.html#MVN_NOT_asimdmisc_R">Vector</a>
  AMED_AARCH64_ENCODING_SXTL_SSHLL_asimdshf_L, //!< <a href="../target/aarch64/SXTL_SSHLL_advsimd.html#SXTL_SSHLL_asimdshf_L">Vector</a>
  AMED_AARCH64_ENCODING_UXTL_USHLL_asimdshf_L, //!< <a href="../target/aarch64/UXTL_USHLL_advsimd.html#UXTL_USHLL_asimdshf_L">Vector</a>
  AMED_AARCH64_ENCODING_abs_z_p_z_, //!< <a href="../target/aarch64/abs_z_p_z.html#abs_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_adclb_z_zzz_, //!< <a href="../target/aarch64/adclb_z_zzz.html#adclb_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_adclt_z_zzz_, //!< <a href="../target/aarch64/adclt_z_zzz.html#adclt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_add_z_p_zz_, //!< <a href="../target/aarch64/add_z_p_zz.html#add_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_add_z_zi_, //!< <a href="../target/aarch64/add_z_zi.html#add_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_add_z_zz_, //!< <a href="../target/aarch64/add_z_zz.html#add_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_addhnb_z_zz_, //!< <a href="../target/aarch64/addhnb_z_zz.html#addhnb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_addhnt_z_zz_, //!< <a href="../target/aarch64/addhnt_z_zz.html#addhnt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_addp_z_p_zz_, //!< <a href="../target/aarch64/addp_z_p_zz.html#addp_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_addpl_r_ri_, //!< <a href="../target/aarch64/addpl_r_ri.html#addpl_r_ri_">SVE</a>
  AMED_AARCH64_ENCODING_addvl_r_ri_, //!< <a href="../target/aarch64/addvl_r_ri.html#addvl_r_ri_">SVE</a>
  AMED_AARCH64_ENCODING_adr_z_az_sd_same_scaled, //!< <a href="../target/aarch64/adr_z_az.html#adr_z_az_sd_same_scaled">Packed offsets</a>
  AMED_AARCH64_ENCODING_adr_z_az_d_s32_scaled, //!< <a href="../target/aarch64/adr_z_az.html#adr_z_az_d_s32_scaled">Unpacked 32-bit signed offsets</a>
  AMED_AARCH64_ENCODING_adr_z_az_d_u32_scaled, //!< <a href="../target/aarch64/adr_z_az.html#adr_z_az_d_u32_scaled">Unpacked 32-bit unsigned offsets</a>
  AMED_AARCH64_ENCODING_aesd_z_zz_, //!< <a href="../target/aarch64/aesd_z_zz.html#aesd_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_aese_z_zz_, //!< <a href="../target/aarch64/aese_z_zz.html#aese_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_aesimc_z_z_, //!< <a href="../target/aarch64/aesimc_z_z.html#aesimc_z_z_">SVE2</a>
  AMED_AARCH64_ENCODING_aesmc_z_z_, //!< <a href="../target/aarch64/aesmc_z_z.html#aesmc_z_z_">SVE2</a>
  AMED_AARCH64_ENCODING_and_p_p_pp_z, //!< <a href="../target/aarch64/and_p_p_pp.html#and_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_ands_p_p_pp_z, //!< <a href="../target/aarch64/and_p_p_pp.html#ands_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_and_z_p_zz_, //!< <a href="../target/aarch64/and_z_p_zz.html#and_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_and_z_zi_, //!< <a href="../target/aarch64/and_z_zi.html#and_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_and_z_zz_, //!< <a href="../target/aarch64/and_z_zz.html#and_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_andv_r_p_z_, //!< <a href="../target/aarch64/andv_r_p_z.html#andv_r_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_asr_z_p_zi_, //!< <a href="../target/aarch64/asr_z_p_zi.html#asr_z_p_zi_">SVE</a>
  AMED_AARCH64_ENCODING_asr_z_p_zw_, //!< <a href="../target/aarch64/asr_z_p_zw.html#asr_z_p_zw_">SVE</a>
  AMED_AARCH64_ENCODING_asr_z_p_zz_, //!< <a href="../target/aarch64/asr_z_p_zz.html#asr_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_asr_z_zi_, //!< <a href="../target/aarch64/asr_z_zi.html#asr_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_asr_z_zw_, //!< <a href="../target/aarch64/asr_z_zw.html#asr_z_zw_">SVE</a>
  AMED_AARCH64_ENCODING_asrd_z_p_zi_, //!< <a href="../target/aarch64/asrd_z_p_zi.html#asrd_z_p_zi_">SVE</a>
  AMED_AARCH64_ENCODING_asrr_z_p_zz_, //!< <a href="../target/aarch64/asrr_z_p_zz.html#asrr_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_bcax_z_zzz_, //!< <a href="../target/aarch64/bcax_z_zzz.html#bcax_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_bdep_z_zz_, //!< <a href="../target/aarch64/bdep_z_zz.html#bdep_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_bext_z_zz_, //!< <a href="../target/aarch64/bext_z_zz.html#bext_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_bfcvt_z_p_z_s2bf, //!< <a href="../target/aarch64/bfcvt_z_p_z.html#bfcvt_z_p_z_s2bf">SVE</a>
  AMED_AARCH64_ENCODING_bfcvtnt_z_p_z_s2bf, //!< <a href="../target/aarch64/bfcvtnt_z_p_z.html#bfcvtnt_z_p_z_s2bf">SVE</a>
  AMED_AARCH64_ENCODING_bfdot_z_zzz_, //!< <a href="../target/aarch64/bfdot_z_zzz.html#bfdot_z_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_bfdot_z_zzzi_, //!< <a href="../target/aarch64/bfdot_z_zzzi.html#bfdot_z_zzzi_">SVE</a>
  AMED_AARCH64_ENCODING_bfmlalb_z_zzz_, //!< <a href="../target/aarch64/bfmlalb_z_zzz.html#bfmlalb_z_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_bfmlalb_z_zzzi_, //!< <a href="../target/aarch64/bfmlalb_z_zzzi.html#bfmlalb_z_zzzi_">SVE</a>
  AMED_AARCH64_ENCODING_bfmlalt_z_zzz_, //!< <a href="../target/aarch64/bfmlalt_z_zzz.html#bfmlalt_z_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_bfmlalt_z_zzzi_, //!< <a href="../target/aarch64/bfmlalt_z_zzzi.html#bfmlalt_z_zzzi_">SVE</a>
  AMED_AARCH64_ENCODING_bfmmla_z_zzz_, //!< <a href="../target/aarch64/bfmmla_z_zzz.html#bfmmla_z_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_bgrp_z_zz_, //!< <a href="../target/aarch64/bgrp_z_zz.html#bgrp_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_bic_p_p_pp_z, //!< <a href="../target/aarch64/bic_p_p_pp.html#bic_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_bics_p_p_pp_z, //!< <a href="../target/aarch64/bic_p_p_pp.html#bics_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_bic_z_p_zz_, //!< <a href="../target/aarch64/bic_z_p_zz.html#bic_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_bic_z_zz_, //!< <a href="../target/aarch64/bic_z_zz.html#bic_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_brka_p_p_p_, //!< <a href="../target/aarch64/brka_p_p_p.html#brka_p_p_p_">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_brkas_p_p_p_z, //!< <a href="../target/aarch64/brka_p_p_p.html#brkas_p_p_p_z">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_brkb_p_p_p_, //!< <a href="../target/aarch64/brkb_p_p_p.html#brkb_p_p_p_">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_brkbs_p_p_p_z, //!< <a href="../target/aarch64/brkb_p_p_p.html#brkbs_p_p_p_z">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_brkn_p_p_pp_, //!< <a href="../target/aarch64/brkn_p_p_pp.html#brkn_p_p_pp_">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_brkns_p_p_pp_, //!< <a href="../target/aarch64/brkn_p_p_pp.html#brkns_p_p_pp_">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_brkpa_p_p_pp_, //!< <a href="../target/aarch64/brkpa_p_p_pp.html#brkpa_p_p_pp_">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_brkpas_p_p_pp_, //!< <a href="../target/aarch64/brkpa_p_p_pp.html#brkpas_p_p_pp_">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_brkpb_p_p_pp_, //!< <a href="../target/aarch64/brkpb_p_p_pp.html#brkpb_p_p_pp_">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_brkpbs_p_p_pp_, //!< <a href="../target/aarch64/brkpb_p_p_pp.html#brkpbs_p_p_pp_">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_bsl1n_z_zzz_, //!< <a href="../target/aarch64/bsl1n_z_zzz.html#bsl1n_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_bsl2n_z_zzz_, //!< <a href="../target/aarch64/bsl2n_z_zzz.html#bsl2n_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_bsl_z_zzz_, //!< <a href="../target/aarch64/bsl_z_zzz.html#bsl_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_cadd_z_zz_, //!< <a href="../target/aarch64/cadd_z_zz.html#cadd_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_cdot_z_zzz_, //!< <a href="../target/aarch64/cdot_z_zzz.html#cdot_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_cdot_z_zzzi_s, //!< <a href="../target/aarch64/cdot_z_zzzi.html#cdot_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_cdot_z_zzzi_d, //!< <a href="../target/aarch64/cdot_z_zzzi.html#cdot_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_clasta_r_p_z_, //!< <a href="../target/aarch64/clasta_r_p_z.html#clasta_r_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_clasta_v_p_z_, //!< <a href="../target/aarch64/clasta_v_p_z.html#clasta_v_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_clasta_z_p_zz_, //!< <a href="../target/aarch64/clasta_z_p_zz.html#clasta_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_clastb_r_p_z_, //!< <a href="../target/aarch64/clastb_r_p_z.html#clastb_r_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_clastb_v_p_z_, //!< <a href="../target/aarch64/clastb_v_p_z.html#clastb_v_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_clastb_z_p_zz_, //!< <a href="../target/aarch64/clastb_z_p_zz.html#clastb_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_cls_z_p_z_, //!< <a href="../target/aarch64/cls_z_p_z.html#cls_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_clz_z_p_z_, //!< <a href="../target/aarch64/clz_z_p_z.html#clz_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_cmla_z_zzz_, //!< <a href="../target/aarch64/cmla_z_zzz.html#cmla_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_cmla_z_zzzi_h, //!< <a href="../target/aarch64/cmla_z_zzzi.html#cmla_z_zzzi_h">16-bit</a>
  AMED_AARCH64_ENCODING_cmla_z_zzzi_s, //!< <a href="../target/aarch64/cmla_z_zzzi.html#cmla_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_cmpeq_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmpeq_p_p_zi_">Equal</a>
  AMED_AARCH64_ENCODING_cmpgt_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmpgt_p_p_zi_">Greater than</a>
  AMED_AARCH64_ENCODING_cmpge_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmpge_p_p_zi_">Greater than or equal</a>
  AMED_AARCH64_ENCODING_cmphi_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmphi_p_p_zi_">Higher</a>
  AMED_AARCH64_ENCODING_cmphs_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmphs_p_p_zi_">Higher or same</a>
  AMED_AARCH64_ENCODING_cmplt_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmplt_p_p_zi_">Less than</a>
  AMED_AARCH64_ENCODING_cmple_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmple_p_p_zi_">Less than or equal</a>
  AMED_AARCH64_ENCODING_cmplo_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmplo_p_p_zi_">Lower</a>
  AMED_AARCH64_ENCODING_cmpls_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmpls_p_p_zi_">Lower or same</a>
  AMED_AARCH64_ENCODING_cmpne_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmpne_p_p_zi_">Not equal</a>
  AMED_AARCH64_ENCODING_cmpeq_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmpeq_p_p_zw_">Equal</a>
  AMED_AARCH64_ENCODING_cmpgt_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmpgt_p_p_zw_">Greater than</a>
  AMED_AARCH64_ENCODING_cmpge_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmpge_p_p_zw_">Greater than or equal</a>
  AMED_AARCH64_ENCODING_cmphi_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmphi_p_p_zw_">Higher</a>
  AMED_AARCH64_ENCODING_cmphs_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmphs_p_p_zw_">Higher or same</a>
  AMED_AARCH64_ENCODING_cmplt_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmplt_p_p_zw_">Less than</a>
  AMED_AARCH64_ENCODING_cmple_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmple_p_p_zw_">Less than or equal</a>
  AMED_AARCH64_ENCODING_cmplo_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmplo_p_p_zw_">Lower</a>
  AMED_AARCH64_ENCODING_cmpls_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmpls_p_p_zw_">Lower or same</a>
  AMED_AARCH64_ENCODING_cmpne_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmpne_p_p_zw_">Not equal</a>
  AMED_AARCH64_ENCODING_cmpeq_p_p_zz_, //!< <a href="../target/aarch64/cmpeq_p_p_zz.html#cmpeq_p_p_zz_">Equal</a>
  AMED_AARCH64_ENCODING_cmpgt_p_p_zz_, //!< <a href="../target/aarch64/cmpeq_p_p_zz.html#cmpgt_p_p_zz_">Greater than</a>
  AMED_AARCH64_ENCODING_cmpge_p_p_zz_, //!< <a href="../target/aarch64/cmpeq_p_p_zz.html#cmpge_p_p_zz_">Greater than or equal</a>
  AMED_AARCH64_ENCODING_cmphi_p_p_zz_, //!< <a href="../target/aarch64/cmpeq_p_p_zz.html#cmphi_p_p_zz_">Higher</a>
  AMED_AARCH64_ENCODING_cmphs_p_p_zz_, //!< <a href="../target/aarch64/cmpeq_p_p_zz.html#cmphs_p_p_zz_">Higher or same</a>
  AMED_AARCH64_ENCODING_cmpne_p_p_zz_, //!< <a href="../target/aarch64/cmpeq_p_p_zz.html#cmpne_p_p_zz_">Not equal</a>
  AMED_AARCH64_ENCODING_cnot_z_p_z_, //!< <a href="../target/aarch64/cnot_z_p_z.html#cnot_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_cnt_z_p_z_, //!< <a href="../target/aarch64/cnt_z_p_z.html#cnt_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_cntb_r_s_, //!< <a href="../target/aarch64/cntb_r_s.html#cntb_r_s_">Byte</a>
  AMED_AARCH64_ENCODING_cntd_r_s_, //!< <a href="../target/aarch64/cntb_r_s.html#cntd_r_s_">Doubleword</a>
  AMED_AARCH64_ENCODING_cnth_r_s_, //!< <a href="../target/aarch64/cntb_r_s.html#cnth_r_s_">Halfword</a>
  AMED_AARCH64_ENCODING_cntw_r_s_, //!< <a href="../target/aarch64/cntb_r_s.html#cntw_r_s_">Word</a>
  AMED_AARCH64_ENCODING_cntp_r_p_p_, //!< <a href="../target/aarch64/cntp_r_p_p.html#cntp_r_p_p_">SVE</a>
  AMED_AARCH64_ENCODING_compact_z_p_z_, //!< <a href="../target/aarch64/compact_z_p_z.html#compact_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_cpy_z_o_i_, //!< <a href="../target/aarch64/cpy_z_o_i.html#cpy_z_o_i_">SVE</a>
  AMED_AARCH64_ENCODING_cpy_z_p_i_, //!< <a href="../target/aarch64/cpy_z_p_i.html#cpy_z_p_i_">SVE</a>
  AMED_AARCH64_ENCODING_cpy_z_p_r_, //!< <a href="../target/aarch64/cpy_z_p_r.html#cpy_z_p_r_">SVE</a>
  AMED_AARCH64_ENCODING_cpy_z_p_v_, //!< <a href="../target/aarch64/cpy_z_p_v.html#cpy_z_p_v_">SVE</a>
  AMED_AARCH64_ENCODING_ctermeq_rr_, //!< <a href="../target/aarch64/ctermeq_rr.html#ctermeq_rr_">Equal</a>
  AMED_AARCH64_ENCODING_ctermne_rr_, //!< <a href="../target/aarch64/ctermeq_rr.html#ctermne_rr_">Not equal</a>
  AMED_AARCH64_ENCODING_decb_r_rs_, //!< <a href="../target/aarch64/decb_r_rs.html#decb_r_rs_">Byte</a>
  AMED_AARCH64_ENCODING_decd_r_rs_, //!< <a href="../target/aarch64/decb_r_rs.html#decd_r_rs_">Doubleword</a>
  AMED_AARCH64_ENCODING_dech_r_rs_, //!< <a href="../target/aarch64/decb_r_rs.html#dech_r_rs_">Halfword</a>
  AMED_AARCH64_ENCODING_decw_r_rs_, //!< <a href="../target/aarch64/decb_r_rs.html#decw_r_rs_">Word</a>
  AMED_AARCH64_ENCODING_decd_z_zs_, //!< <a href="../target/aarch64/decd_z_zs.html#decd_z_zs_">Doubleword</a>
  AMED_AARCH64_ENCODING_dech_z_zs_, //!< <a href="../target/aarch64/decd_z_zs.html#dech_z_zs_">Halfword</a>
  AMED_AARCH64_ENCODING_decw_z_zs_, //!< <a href="../target/aarch64/decd_z_zs.html#decw_z_zs_">Word</a>
  AMED_AARCH64_ENCODING_decp_r_p_r_, //!< <a href="../target/aarch64/decp_r_p_r.html#decp_r_p_r_">SVE</a>
  AMED_AARCH64_ENCODING_decp_z_p_z_, //!< <a href="../target/aarch64/decp_z_p_z.html#decp_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_dup_z_i_, //!< <a href="../target/aarch64/dup_z_i.html#dup_z_i_">SVE</a>
  AMED_AARCH64_ENCODING_dup_z_r_, //!< <a href="../target/aarch64/dup_z_r.html#dup_z_r_">SVE</a>
  AMED_AARCH64_ENCODING_dup_z_zi_, //!< <a href="../target/aarch64/dup_z_zi.html#dup_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_dupm_z_i_, //!< <a href="../target/aarch64/dupm_z_i.html#dupm_z_i_">SVE</a>
  AMED_AARCH64_ENCODING_eor3_z_zzz_, //!< <a href="../target/aarch64/eor3_z_zzz.html#eor3_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_eor_p_p_pp_z, //!< <a href="../target/aarch64/eor_p_p_pp.html#eor_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_eors_p_p_pp_z, //!< <a href="../target/aarch64/eor_p_p_pp.html#eors_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_eor_z_p_zz_, //!< <a href="../target/aarch64/eor_z_p_zz.html#eor_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_eor_z_zi_, //!< <a href="../target/aarch64/eor_z_zi.html#eor_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_eor_z_zz_, //!< <a href="../target/aarch64/eor_z_zz.html#eor_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_eorbt_z_zz_, //!< <a href="../target/aarch64/eorbt_z_zz.html#eorbt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_eortb_z_zz_, //!< <a href="../target/aarch64/eortb_z_zz.html#eortb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_eorv_r_p_z_, //!< <a href="../target/aarch64/eorv_r_p_z.html#eorv_r_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_ext_z_zi_con, //!< <a href="../target/aarch64/ext_z_zi.html#ext_z_zi_con">Constructive</a>
  AMED_AARCH64_ENCODING_ext_z_zi_des, //!< <a href="../target/aarch64/ext_z_zi.html#ext_z_zi_des">Destructive</a>
  AMED_AARCH64_ENCODING_fabd_z_p_zz_, //!< <a href="../target/aarch64/fabd_z_p_zz.html#fabd_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fabs_z_p_z_, //!< <a href="../target/aarch64/fabs_z_p_z.html#fabs_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_facgt_p_p_zz_, //!< <a href="../target/aarch64/facge_p_p_zz.html#facgt_p_p_zz_">Greater than</a>
  AMED_AARCH64_ENCODING_facge_p_p_zz_, //!< <a href="../target/aarch64/facge_p_p_zz.html#facge_p_p_zz_">Greater than or equal</a>
  AMED_AARCH64_ENCODING_fadd_z_p_zs_, //!< <a href="../target/aarch64/fadd_z_p_zs.html#fadd_z_p_zs_">SVE</a>
  AMED_AARCH64_ENCODING_fadd_z_p_zz_, //!< <a href="../target/aarch64/fadd_z_p_zz.html#fadd_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fadd_z_zz_, //!< <a href="../target/aarch64/fadd_z_zz.html#fadd_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fadda_v_p_z_, //!< <a href="../target/aarch64/fadda_v_p_z.html#fadda_v_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_faddp_z_p_zz_, //!< <a href="../target/aarch64/faddp_z_p_zz.html#faddp_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_faddv_v_p_z_, //!< <a href="../target/aarch64/faddv_v_p_z.html#faddv_v_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_fcadd_z_p_zz_, //!< <a href="../target/aarch64/fcadd_z_p_zz.html#fcadd_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fcmeq_p_p_z0_, //!< <a href="../target/aarch64/fcmeq_p_p_z0.html#fcmeq_p_p_z0_">Equal</a>
  AMED_AARCH64_ENCODING_fcmgt_p_p_z0_, //!< <a href="../target/aarch64/fcmeq_p_p_z0.html#fcmgt_p_p_z0_">Greater than</a>
  AMED_AARCH64_ENCODING_fcmge_p_p_z0_, //!< <a href="../target/aarch64/fcmeq_p_p_z0.html#fcmge_p_p_z0_">Greater than or equal</a>
  AMED_AARCH64_ENCODING_fcmlt_p_p_z0_, //!< <a href="../target/aarch64/fcmeq_p_p_z0.html#fcmlt_p_p_z0_">Less than</a>
  AMED_AARCH64_ENCODING_fcmle_p_p_z0_, //!< <a href="../target/aarch64/fcmeq_p_p_z0.html#fcmle_p_p_z0_">Less than or equal</a>
  AMED_AARCH64_ENCODING_fcmne_p_p_z0_, //!< <a href="../target/aarch64/fcmeq_p_p_z0.html#fcmne_p_p_z0_">Not equal</a>
  AMED_AARCH64_ENCODING_fcmeq_p_p_zz_, //!< <a href="../target/aarch64/fcmeq_p_p_zz.html#fcmeq_p_p_zz_">Equal</a>
  AMED_AARCH64_ENCODING_fcmgt_p_p_zz_, //!< <a href="../target/aarch64/fcmeq_p_p_zz.html#fcmgt_p_p_zz_">Greater than</a>
  AMED_AARCH64_ENCODING_fcmge_p_p_zz_, //!< <a href="../target/aarch64/fcmeq_p_p_zz.html#fcmge_p_p_zz_">Greater than or equal</a>
  AMED_AARCH64_ENCODING_fcmne_p_p_zz_, //!< <a href="../target/aarch64/fcmeq_p_p_zz.html#fcmne_p_p_zz_">Not equal</a>
  AMED_AARCH64_ENCODING_fcmuo_p_p_zz_, //!< <a href="../target/aarch64/fcmeq_p_p_zz.html#fcmuo_p_p_zz_">Unordered</a>
  AMED_AARCH64_ENCODING_fcmla_z_p_zzz_, //!< <a href="../target/aarch64/fcmla_z_p_zzz.html#fcmla_z_p_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_fcmla_z_zzzi_h, //!< <a href="../target/aarch64/fcmla_z_zzzi.html#fcmla_z_zzzi_h">Half-precision</a>
  AMED_AARCH64_ENCODING_fcmla_z_zzzi_s, //!< <a href="../target/aarch64/fcmla_z_zzzi.html#fcmla_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_ENCODING_fcpy_z_p_i_, //!< <a href="../target/aarch64/fcpy_z_p_i.html#fcpy_z_p_i_">SVE</a>
  AMED_AARCH64_ENCODING_fcvt_z_p_z_h2s, //!< <a href="../target/aarch64/fcvt_z_p_z.html#fcvt_z_p_z_h2s">Half-precision to single-precision</a>
  AMED_AARCH64_ENCODING_fcvt_z_p_z_h2d, //!< <a href="../target/aarch64/fcvt_z_p_z.html#fcvt_z_p_z_h2d">Half-precision to double-precision</a>
  AMED_AARCH64_ENCODING_fcvt_z_p_z_s2h, //!< <a href="../target/aarch64/fcvt_z_p_z.html#fcvt_z_p_z_s2h">Single-precision to half-precision</a>
  AMED_AARCH64_ENCODING_fcvt_z_p_z_s2d, //!< <a href="../target/aarch64/fcvt_z_p_z.html#fcvt_z_p_z_s2d">Single-precision to double-precision</a>
  AMED_AARCH64_ENCODING_fcvt_z_p_z_d2h, //!< <a href="../target/aarch64/fcvt_z_p_z.html#fcvt_z_p_z_d2h">Double-precision to half-precision</a>
  AMED_AARCH64_ENCODING_fcvt_z_p_z_d2s, //!< <a href="../target/aarch64/fcvt_z_p_z.html#fcvt_z_p_z_d2s">Double-precision to single-precision</a>
  AMED_AARCH64_ENCODING_fcvtlt_z_p_z_h2s, //!< <a href="../target/aarch64/fcvtlt_z_p_z.html#fcvtlt_z_p_z_h2s">Half-precision to single-precision</a>
  AMED_AARCH64_ENCODING_fcvtlt_z_p_z_s2d, //!< <a href="../target/aarch64/fcvtlt_z_p_z.html#fcvtlt_z_p_z_s2d">Single-precision to double-precision</a>
  AMED_AARCH64_ENCODING_fcvtnt_z_p_z_s2h, //!< <a href="../target/aarch64/fcvtnt_z_p_z.html#fcvtnt_z_p_z_s2h">Single-precision to half-precision</a>
  AMED_AARCH64_ENCODING_fcvtnt_z_p_z_d2s, //!< <a href="../target/aarch64/fcvtnt_z_p_z.html#fcvtnt_z_p_z_d2s">Double-precision to single-precision</a>
  AMED_AARCH64_ENCODING_fcvtx_z_p_z_d2s, //!< <a href="../target/aarch64/fcvtx_z_p_z.html#fcvtx_z_p_z_d2s">Double-precision to single-precision</a>
  AMED_AARCH64_ENCODING_fcvtxnt_z_p_z_d2s, //!< <a href="../target/aarch64/fcvtxnt_z_p_z.html#fcvtxnt_z_p_z_d2s">Double-precision to single-precision</a>
  AMED_AARCH64_ENCODING_fcvtzs_z_p_z_fp162h, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_fp162h">Half-precision to 16-bit</a>
  AMED_AARCH64_ENCODING_fcvtzs_z_p_z_fp162w, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_fp162w">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_fcvtzs_z_p_z_fp162x, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_fp162x">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_fcvtzs_z_p_z_s2w, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_s2w">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_fcvtzs_z_p_z_s2x, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_s2x">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_fcvtzs_z_p_z_d2w, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_d2w">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_fcvtzs_z_p_z_d2x, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_d2x">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_fcvtzu_z_p_z_fp162h, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_fp162h">Half-precision to 16-bit</a>
  AMED_AARCH64_ENCODING_fcvtzu_z_p_z_fp162w, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_fp162w">Half-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_fcvtzu_z_p_z_fp162x, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_fp162x">Half-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_fcvtzu_z_p_z_s2w, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_s2w">Single-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_fcvtzu_z_p_z_s2x, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_s2x">Single-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_fcvtzu_z_p_z_d2w, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_d2w">Double-precision to 32-bit</a>
  AMED_AARCH64_ENCODING_fcvtzu_z_p_z_d2x, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_d2x">Double-precision to 64-bit</a>
  AMED_AARCH64_ENCODING_fdiv_z_p_zz_, //!< <a href="../target/aarch64/fdiv_z_p_zz.html#fdiv_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fdivr_z_p_zz_, //!< <a href="../target/aarch64/fdivr_z_p_zz.html#fdivr_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fdup_z_i_, //!< <a href="../target/aarch64/fdup_z_i.html#fdup_z_i_">SVE</a>
  AMED_AARCH64_ENCODING_fexpa_z_z_, //!< <a href="../target/aarch64/fexpa_z_z.html#fexpa_z_z_">SVE</a>
  AMED_AARCH64_ENCODING_flogb_z_p_z_, //!< <a href="../target/aarch64/flogb_z_p_z.html#flogb_z_p_z_">SVE2</a>
  AMED_AARCH64_ENCODING_fmad_z_p_zzz_, //!< <a href="../target/aarch64/fmad_z_p_zzz.html#fmad_z_p_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_fmax_z_p_zs_, //!< <a href="../target/aarch64/fmax_z_p_zs.html#fmax_z_p_zs_">SVE</a>
  AMED_AARCH64_ENCODING_fmax_z_p_zz_, //!< <a href="../target/aarch64/fmax_z_p_zz.html#fmax_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fmaxnm_z_p_zs_, //!< <a href="../target/aarch64/fmaxnm_z_p_zs.html#fmaxnm_z_p_zs_">SVE</a>
  AMED_AARCH64_ENCODING_fmaxnm_z_p_zz_, //!< <a href="../target/aarch64/fmaxnm_z_p_zz.html#fmaxnm_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fmaxnmp_z_p_zz_, //!< <a href="../target/aarch64/fmaxnmp_z_p_zz.html#fmaxnmp_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_fmaxnmv_v_p_z_, //!< <a href="../target/aarch64/fmaxnmv_v_p_z.html#fmaxnmv_v_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_fmaxp_z_p_zz_, //!< <a href="../target/aarch64/fmaxp_z_p_zz.html#fmaxp_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_fmaxv_v_p_z_, //!< <a href="../target/aarch64/fmaxv_v_p_z.html#fmaxv_v_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_fmin_z_p_zs_, //!< <a href="../target/aarch64/fmin_z_p_zs.html#fmin_z_p_zs_">SVE</a>
  AMED_AARCH64_ENCODING_fmin_z_p_zz_, //!< <a href="../target/aarch64/fmin_z_p_zz.html#fmin_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fminnm_z_p_zs_, //!< <a href="../target/aarch64/fminnm_z_p_zs.html#fminnm_z_p_zs_">SVE</a>
  AMED_AARCH64_ENCODING_fminnm_z_p_zz_, //!< <a href="../target/aarch64/fminnm_z_p_zz.html#fminnm_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fminnmp_z_p_zz_, //!< <a href="../target/aarch64/fminnmp_z_p_zz.html#fminnmp_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_fminnmv_v_p_z_, //!< <a href="../target/aarch64/fminnmv_v_p_z.html#fminnmv_v_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_fminp_z_p_zz_, //!< <a href="../target/aarch64/fminp_z_p_zz.html#fminp_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_fminv_v_p_z_, //!< <a href="../target/aarch64/fminv_v_p_z.html#fminv_v_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_fmla_z_p_zzz_, //!< <a href="../target/aarch64/fmla_z_p_zzz.html#fmla_z_p_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_fmla_z_zzzi_h, //!< <a href="../target/aarch64/fmla_z_zzzi.html#fmla_z_zzzi_h">Half-precision</a>
  AMED_AARCH64_ENCODING_fmla_z_zzzi_s, //!< <a href="../target/aarch64/fmla_z_zzzi.html#fmla_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_ENCODING_fmla_z_zzzi_d, //!< <a href="../target/aarch64/fmla_z_zzzi.html#fmla_z_zzzi_d">Double-precision</a>
  AMED_AARCH64_ENCODING_fmlalb_z_zzz_, //!< <a href="../target/aarch64/fmlalb_z_zzz.html#fmlalb_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_fmlalb_z_zzzi_s, //!< <a href="../target/aarch64/fmlalb_z_zzzi.html#fmlalb_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_ENCODING_fmlalt_z_zzz_, //!< <a href="../target/aarch64/fmlalt_z_zzz.html#fmlalt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_fmlalt_z_zzzi_s, //!< <a href="../target/aarch64/fmlalt_z_zzzi.html#fmlalt_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_ENCODING_fmls_z_p_zzz_, //!< <a href="../target/aarch64/fmls_z_p_zzz.html#fmls_z_p_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_fmls_z_zzzi_h, //!< <a href="../target/aarch64/fmls_z_zzzi.html#fmls_z_zzzi_h">Half-precision</a>
  AMED_AARCH64_ENCODING_fmls_z_zzzi_s, //!< <a href="../target/aarch64/fmls_z_zzzi.html#fmls_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_ENCODING_fmls_z_zzzi_d, //!< <a href="../target/aarch64/fmls_z_zzzi.html#fmls_z_zzzi_d">Double-precision</a>
  AMED_AARCH64_ENCODING_fmlslb_z_zzz_, //!< <a href="../target/aarch64/fmlslb_z_zzz.html#fmlslb_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_fmlslb_z_zzzi_s, //!< <a href="../target/aarch64/fmlslb_z_zzzi.html#fmlslb_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_ENCODING_fmlslt_z_zzz_, //!< <a href="../target/aarch64/fmlslt_z_zzz.html#fmlslt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_fmlslt_z_zzzi_s, //!< <a href="../target/aarch64/fmlslt_z_zzzi.html#fmlslt_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_ENCODING_fmmla_z_zzz_s, //!< <a href="../target/aarch64/fmmla_z_zzz.html#fmmla_z_zzz_s">32-bit element</a>
  AMED_AARCH64_ENCODING_fmmla_z_zzz_d, //!< <a href="../target/aarch64/fmmla_z_zzz.html#fmmla_z_zzz_d">64-bit element</a>
  AMED_AARCH64_ENCODING_fmsb_z_p_zzz_, //!< <a href="../target/aarch64/fmsb_z_p_zzz.html#fmsb_z_p_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_fmul_z_p_zs_, //!< <a href="../target/aarch64/fmul_z_p_zs.html#fmul_z_p_zs_">SVE</a>
  AMED_AARCH64_ENCODING_fmul_z_p_zz_, //!< <a href="../target/aarch64/fmul_z_p_zz.html#fmul_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fmul_z_zz_, //!< <a href="../target/aarch64/fmul_z_zz.html#fmul_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fmul_z_zzi_h, //!< <a href="../target/aarch64/fmul_z_zzi.html#fmul_z_zzi_h">Half-precision</a>
  AMED_AARCH64_ENCODING_fmul_z_zzi_s, //!< <a href="../target/aarch64/fmul_z_zzi.html#fmul_z_zzi_s">Single-precision</a>
  AMED_AARCH64_ENCODING_fmul_z_zzi_d, //!< <a href="../target/aarch64/fmul_z_zzi.html#fmul_z_zzi_d">Double-precision</a>
  AMED_AARCH64_ENCODING_fmulx_z_p_zz_, //!< <a href="../target/aarch64/fmulx_z_p_zz.html#fmulx_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fneg_z_p_z_, //!< <a href="../target/aarch64/fneg_z_p_z.html#fneg_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_fnmad_z_p_zzz_, //!< <a href="../target/aarch64/fnmad_z_p_zzz.html#fnmad_z_p_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_fnmla_z_p_zzz_, //!< <a href="../target/aarch64/fnmla_z_p_zzz.html#fnmla_z_p_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_fnmls_z_p_zzz_, //!< <a href="../target/aarch64/fnmls_z_p_zzz.html#fnmls_z_p_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_fnmsb_z_p_zzz_, //!< <a href="../target/aarch64/fnmsb_z_p_zzz.html#fnmsb_z_p_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_frecpe_z_z_, //!< <a href="../target/aarch64/frecpe_z_z.html#frecpe_z_z_">SVE</a>
  AMED_AARCH64_ENCODING_frecps_z_zz_, //!< <a href="../target/aarch64/frecps_z_zz.html#frecps_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_frecpx_z_p_z_, //!< <a href="../target/aarch64/frecpx_z_p_z.html#frecpx_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_frinti_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frinti_z_p_z_">Current mode</a>
  AMED_AARCH64_ENCODING_frintx_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frintx_z_p_z_">Current mode signalling inexact</a>
  AMED_AARCH64_ENCODING_frinta_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frinta_z_p_z_">Nearest with ties to away</a>
  AMED_AARCH64_ENCODING_frintn_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frintn_z_p_z_">Nearest with ties to even</a>
  AMED_AARCH64_ENCODING_frintz_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frintz_z_p_z_">Toward zero</a>
  AMED_AARCH64_ENCODING_frintm_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frintm_z_p_z_">Toward minus infinity</a>
  AMED_AARCH64_ENCODING_frintp_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frintp_z_p_z_">Toward plus infinity</a>
  AMED_AARCH64_ENCODING_frsqrte_z_z_, //!< <a href="../target/aarch64/frsqrte_z_z.html#frsqrte_z_z_">SVE</a>
  AMED_AARCH64_ENCODING_frsqrts_z_zz_, //!< <a href="../target/aarch64/frsqrts_z_zz.html#frsqrts_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fscale_z_p_zz_, //!< <a href="../target/aarch64/fscale_z_p_zz.html#fscale_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fsqrt_z_p_z_, //!< <a href="../target/aarch64/fsqrt_z_p_z.html#fsqrt_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_fsub_z_p_zs_, //!< <a href="../target/aarch64/fsub_z_p_zs.html#fsub_z_p_zs_">SVE</a>
  AMED_AARCH64_ENCODING_fsub_z_p_zz_, //!< <a href="../target/aarch64/fsub_z_p_zz.html#fsub_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fsub_z_zz_, //!< <a href="../target/aarch64/fsub_z_zz.html#fsub_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_fsubr_z_p_zs_, //!< <a href="../target/aarch64/fsubr_z_p_zs.html#fsubr_z_p_zs_">SVE</a>
  AMED_AARCH64_ENCODING_fsubr_z_p_zz_, //!< <a href="../target/aarch64/fsubr_z_p_zz.html#fsubr_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_ftmad_z_zzi_, //!< <a href="../target/aarch64/ftmad_z_zzi.html#ftmad_z_zzi_">SVE</a>
  AMED_AARCH64_ENCODING_ftsmul_z_zz_, //!< <a href="../target/aarch64/ftsmul_z_zz.html#ftsmul_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_ftssel_z_zz_, //!< <a href="../target/aarch64/ftssel_z_zz.html#ftssel_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_histcnt_z_p_zz_, //!< <a href="../target/aarch64/histcnt_z_p_zz.html#histcnt_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_histseg_z_zz_, //!< <a href="../target/aarch64/histseg_z_zz.html#histseg_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_incb_r_rs_, //!< <a href="../target/aarch64/incb_r_rs.html#incb_r_rs_">Byte</a>
  AMED_AARCH64_ENCODING_incd_r_rs_, //!< <a href="../target/aarch64/incb_r_rs.html#incd_r_rs_">Doubleword</a>
  AMED_AARCH64_ENCODING_inch_r_rs_, //!< <a href="../target/aarch64/incb_r_rs.html#inch_r_rs_">Halfword</a>
  AMED_AARCH64_ENCODING_incw_r_rs_, //!< <a href="../target/aarch64/incb_r_rs.html#incw_r_rs_">Word</a>
  AMED_AARCH64_ENCODING_incd_z_zs_, //!< <a href="../target/aarch64/incd_z_zs.html#incd_z_zs_">Doubleword</a>
  AMED_AARCH64_ENCODING_inch_z_zs_, //!< <a href="../target/aarch64/incd_z_zs.html#inch_z_zs_">Halfword</a>
  AMED_AARCH64_ENCODING_incw_z_zs_, //!< <a href="../target/aarch64/incd_z_zs.html#incw_z_zs_">Word</a>
  AMED_AARCH64_ENCODING_incp_r_p_r_, //!< <a href="../target/aarch64/incp_r_p_r.html#incp_r_p_r_">SVE</a>
  AMED_AARCH64_ENCODING_incp_z_p_z_, //!< <a href="../target/aarch64/incp_z_p_z.html#incp_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_index_z_ii_, //!< <a href="../target/aarch64/index_z_ii.html#index_z_ii_">SVE</a>
  AMED_AARCH64_ENCODING_index_z_ir_, //!< <a href="../target/aarch64/index_z_ir.html#index_z_ir_">SVE</a>
  AMED_AARCH64_ENCODING_index_z_ri_, //!< <a href="../target/aarch64/index_z_ri.html#index_z_ri_">SVE</a>
  AMED_AARCH64_ENCODING_index_z_rr_, //!< <a href="../target/aarch64/index_z_rr.html#index_z_rr_">SVE</a>
  AMED_AARCH64_ENCODING_insr_z_r_, //!< <a href="../target/aarch64/insr_z_r.html#insr_z_r_">SVE</a>
  AMED_AARCH64_ENCODING_insr_z_v_, //!< <a href="../target/aarch64/insr_z_v.html#insr_z_v_">SVE</a>
  AMED_AARCH64_ENCODING_lasta_r_p_z_, //!< <a href="../target/aarch64/lasta_r_p_z.html#lasta_r_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_lasta_v_p_z_, //!< <a href="../target/aarch64/lasta_v_p_z.html#lasta_v_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_lastb_r_p_z_, //!< <a href="../target/aarch64/lastb_r_p_z.html#lastb_r_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_lastb_v_p_z_, //!< <a href="../target/aarch64/lastb_v_p_z.html#lastb_v_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_ld1b_z_p_ai_s, //!< <a href="../target/aarch64/ld1b_z_p_ai.html#ld1b_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1b_z_p_ai_d, //!< <a href="../target/aarch64/ld1b_z_p_ai.html#ld1b_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1b_z_p_bi_u8, //!< <a href="../target/aarch64/ld1b_z_p_bi.html#ld1b_z_p_bi_u8">8-bit element</a>
  AMED_AARCH64_ENCODING_ld1b_z_p_bi_u16, //!< <a href="../target/aarch64/ld1b_z_p_bi.html#ld1b_z_p_bi_u16">16-bit element</a>
  AMED_AARCH64_ENCODING_ld1b_z_p_bi_u32, //!< <a href="../target/aarch64/ld1b_z_p_bi.html#ld1b_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1b_z_p_bi_u64, //!< <a href="../target/aarch64/ld1b_z_p_bi.html#ld1b_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1b_z_p_br_u8, //!< <a href="../target/aarch64/ld1b_z_p_br.html#ld1b_z_p_br_u8">8-bit element</a>
  AMED_AARCH64_ENCODING_ld1b_z_p_br_u16, //!< <a href="../target/aarch64/ld1b_z_p_br.html#ld1b_z_p_br_u16">16-bit element</a>
  AMED_AARCH64_ENCODING_ld1b_z_p_br_u32, //!< <a href="../target/aarch64/ld1b_z_p_br.html#ld1b_z_p_br_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1b_z_p_br_u64, //!< <a href="../target/aarch64/ld1b_z_p_br.html#ld1b_z_p_br_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1b_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1b_z_p_bz.html#ld1b_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1b_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ld1b_z_p_bz.html#ld1b_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1b_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1b_z_p_bz.html#ld1b_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1d_z_p_ai_d, //!< <a href="../target/aarch64/ld1d_z_p_ai.html#ld1d_z_p_ai_d">SVE</a>
  AMED_AARCH64_ENCODING_ld1d_z_p_bi_u64, //!< <a href="../target/aarch64/ld1d_z_p_bi.html#ld1d_z_p_bi_u64">SVE</a>
  AMED_AARCH64_ENCODING_ld1d_z_p_br_u64, //!< <a href="../target/aarch64/ld1d_z_p_br.html#ld1d_z_p_br_u64">SVE</a>
  AMED_AARCH64_ENCODING_ld1d_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ld1d_z_p_bz.html#ld1d_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_ld1d_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1d_z_p_bz.html#ld1d_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1d_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ld1d_z_p_bz.html#ld1d_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ld1d_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1d_z_p_bz.html#ld1d_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_ai_s, //!< <a href="../target/aarch64/ld1h_z_p_ai.html#ld1h_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_ai_d, //!< <a href="../target/aarch64/ld1h_z_p_ai.html#ld1h_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_bi_u16, //!< <a href="../target/aarch64/ld1h_z_p_bi.html#ld1h_z_p_bi_u16">16-bit element</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_bi_u32, //!< <a href="../target/aarch64/ld1h_z_p_bi.html#ld1h_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_bi_u64, //!< <a href="../target/aarch64/ld1h_z_p_bi.html#ld1h_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_br_u16, //!< <a href="../target/aarch64/ld1h_z_p_br.html#ld1h_z_p_br_u16">16-bit element</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_br_u32, //!< <a href="../target/aarch64/ld1h_z_p_br.html#ld1h_z_p_br_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_br_u64, //!< <a href="../target/aarch64/ld1h_z_p_br.html#ld1h_z_p_br_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/ld1h_z_p_bz.html#ld1h_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ld1h_z_p_bz.html#ld1h_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1h_z_p_bz.html#ld1h_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ld1h_z_p_bz.html#ld1h_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ld1h_z_p_bz.html#ld1h_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ld1h_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1h_z_p_bz.html#ld1h_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1rb_z_p_bi_u8, //!< <a href="../target/aarch64/ld1rb_z_p_bi.html#ld1rb_z_p_bi_u8">8-bit element</a>
  AMED_AARCH64_ENCODING_ld1rb_z_p_bi_u16, //!< <a href="../target/aarch64/ld1rb_z_p_bi.html#ld1rb_z_p_bi_u16">16-bit element</a>
  AMED_AARCH64_ENCODING_ld1rb_z_p_bi_u32, //!< <a href="../target/aarch64/ld1rb_z_p_bi.html#ld1rb_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1rb_z_p_bi_u64, //!< <a href="../target/aarch64/ld1rb_z_p_bi.html#ld1rb_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1rd_z_p_bi_u64, //!< <a href="../target/aarch64/ld1rd_z_p_bi.html#ld1rd_z_p_bi_u64">SVE</a>
  AMED_AARCH64_ENCODING_ld1rh_z_p_bi_u16, //!< <a href="../target/aarch64/ld1rh_z_p_bi.html#ld1rh_z_p_bi_u16">16-bit element</a>
  AMED_AARCH64_ENCODING_ld1rh_z_p_bi_u32, //!< <a href="../target/aarch64/ld1rh_z_p_bi.html#ld1rh_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1rh_z_p_bi_u64, //!< <a href="../target/aarch64/ld1rh_z_p_bi.html#ld1rh_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1rob_z_p_bi_u8, //!< <a href="../target/aarch64/ld1rob_z_p_bi.html#ld1rob_z_p_bi_u8">SVE</a>
  AMED_AARCH64_ENCODING_ld1rob_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1rob_z_p_br.html#ld1rob_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld1rod_z_p_bi_u64, //!< <a href="../target/aarch64/ld1rod_z_p_bi.html#ld1rod_z_p_bi_u64">SVE</a>
  AMED_AARCH64_ENCODING_ld1rod_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1rod_z_p_br.html#ld1rod_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld1roh_z_p_bi_u16, //!< <a href="../target/aarch64/ld1roh_z_p_bi.html#ld1roh_z_p_bi_u16">SVE</a>
  AMED_AARCH64_ENCODING_ld1roh_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1roh_z_p_br.html#ld1roh_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld1row_z_p_bi_u32, //!< <a href="../target/aarch64/ld1row_z_p_bi.html#ld1row_z_p_bi_u32">SVE</a>
  AMED_AARCH64_ENCODING_ld1row_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1row_z_p_br.html#ld1row_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld1rqb_z_p_bi_u8, //!< <a href="../target/aarch64/ld1rqb_z_p_bi.html#ld1rqb_z_p_bi_u8">SVE</a>
  AMED_AARCH64_ENCODING_ld1rqb_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1rqb_z_p_br.html#ld1rqb_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld1rqd_z_p_bi_u64, //!< <a href="../target/aarch64/ld1rqd_z_p_bi.html#ld1rqd_z_p_bi_u64">SVE</a>
  AMED_AARCH64_ENCODING_ld1rqd_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1rqd_z_p_br.html#ld1rqd_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld1rqh_z_p_bi_u16, //!< <a href="../target/aarch64/ld1rqh_z_p_bi.html#ld1rqh_z_p_bi_u16">SVE</a>
  AMED_AARCH64_ENCODING_ld1rqh_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1rqh_z_p_br.html#ld1rqh_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld1rqw_z_p_bi_u32, //!< <a href="../target/aarch64/ld1rqw_z_p_bi.html#ld1rqw_z_p_bi_u32">SVE</a>
  AMED_AARCH64_ENCODING_ld1rqw_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1rqw_z_p_br.html#ld1rqw_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld1rsb_z_p_bi_s16, //!< <a href="../target/aarch64/ld1rsb_z_p_bi.html#ld1rsb_z_p_bi_s16">16-bit element</a>
  AMED_AARCH64_ENCODING_ld1rsb_z_p_bi_s32, //!< <a href="../target/aarch64/ld1rsb_z_p_bi.html#ld1rsb_z_p_bi_s32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1rsb_z_p_bi_s64, //!< <a href="../target/aarch64/ld1rsb_z_p_bi.html#ld1rsb_z_p_bi_s64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1rsh_z_p_bi_s32, //!< <a href="../target/aarch64/ld1rsh_z_p_bi.html#ld1rsh_z_p_bi_s32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1rsh_z_p_bi_s64, //!< <a href="../target/aarch64/ld1rsh_z_p_bi.html#ld1rsh_z_p_bi_s64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1rsw_z_p_bi_s64, //!< <a href="../target/aarch64/ld1rsw_z_p_bi.html#ld1rsw_z_p_bi_s64">SVE</a>
  AMED_AARCH64_ENCODING_ld1rw_z_p_bi_u32, //!< <a href="../target/aarch64/ld1rw_z_p_bi.html#ld1rw_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1rw_z_p_bi_u64, //!< <a href="../target/aarch64/ld1rw_z_p_bi.html#ld1rw_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1sb_z_p_ai_s, //!< <a href="../target/aarch64/ld1sb_z_p_ai.html#ld1sb_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1sb_z_p_ai_d, //!< <a href="../target/aarch64/ld1sb_z_p_ai.html#ld1sb_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1sb_z_p_bi_s16, //!< <a href="../target/aarch64/ld1sb_z_p_bi.html#ld1sb_z_p_bi_s16">16-bit element</a>
  AMED_AARCH64_ENCODING_ld1sb_z_p_bi_s32, //!< <a href="../target/aarch64/ld1sb_z_p_bi.html#ld1sb_z_p_bi_s32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1sb_z_p_bi_s64, //!< <a href="../target/aarch64/ld1sb_z_p_bi.html#ld1sb_z_p_bi_s64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1sb_z_p_br_s16, //!< <a href="../target/aarch64/ld1sb_z_p_br.html#ld1sb_z_p_br_s16">16-bit element</a>
  AMED_AARCH64_ENCODING_ld1sb_z_p_br_s32, //!< <a href="../target/aarch64/ld1sb_z_p_br.html#ld1sb_z_p_br_s32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1sb_z_p_br_s64, //!< <a href="../target/aarch64/ld1sb_z_p_br.html#ld1sb_z_p_br_s64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1sb_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1sb_z_p_bz.html#ld1sb_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1sb_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ld1sb_z_p_bz.html#ld1sb_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1sb_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1sb_z_p_bz.html#ld1sb_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1sh_z_p_ai_s, //!< <a href="../target/aarch64/ld1sh_z_p_ai.html#ld1sh_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1sh_z_p_ai_d, //!< <a href="../target/aarch64/ld1sh_z_p_ai.html#ld1sh_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1sh_z_p_bi_s32, //!< <a href="../target/aarch64/ld1sh_z_p_bi.html#ld1sh_z_p_bi_s32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1sh_z_p_bi_s64, //!< <a href="../target/aarch64/ld1sh_z_p_bi.html#ld1sh_z_p_bi_s64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1sh_z_p_br_s32, //!< <a href="../target/aarch64/ld1sh_z_p_br.html#ld1sh_z_p_br_s32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1sh_z_p_br_s64, //!< <a href="../target/aarch64/ld1sh_z_p_br.html#ld1sh_z_p_br_s64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1sh_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/ld1sh_z_p_bz.html#ld1sh_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ld1sh_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ld1sh_z_p_bz.html#ld1sh_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_ld1sh_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1sh_z_p_bz.html#ld1sh_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1sh_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ld1sh_z_p_bz.html#ld1sh_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1sh_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ld1sh_z_p_bz.html#ld1sh_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ld1sh_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1sh_z_p_bz.html#ld1sh_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1sw_z_p_ai_d, //!< <a href="../target/aarch64/ld1sw_z_p_ai.html#ld1sw_z_p_ai_d">SVE</a>
  AMED_AARCH64_ENCODING_ld1sw_z_p_bi_s64, //!< <a href="../target/aarch64/ld1sw_z_p_bi.html#ld1sw_z_p_bi_s64">SVE</a>
  AMED_AARCH64_ENCODING_ld1sw_z_p_br_s64, //!< <a href="../target/aarch64/ld1sw_z_p_br.html#ld1sw_z_p_br_s64">SVE</a>
  AMED_AARCH64_ENCODING_ld1sw_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ld1sw_z_p_bz.html#ld1sw_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_ld1sw_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1sw_z_p_bz.html#ld1sw_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1sw_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ld1sw_z_p_bz.html#ld1sw_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ld1sw_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1sw_z_p_bz.html#ld1sw_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1w_z_p_ai_s, //!< <a href="../target/aarch64/ld1w_z_p_ai.html#ld1w_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1w_z_p_ai_d, //!< <a href="../target/aarch64/ld1w_z_p_ai.html#ld1w_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1w_z_p_bi_u32, //!< <a href="../target/aarch64/ld1w_z_p_bi.html#ld1w_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1w_z_p_bi_u64, //!< <a href="../target/aarch64/ld1w_z_p_bi.html#ld1w_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1w_z_p_br_u32, //!< <a href="../target/aarch64/ld1w_z_p_br.html#ld1w_z_p_br_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ld1w_z_p_br_u64, //!< <a href="../target/aarch64/ld1w_z_p_br.html#ld1w_z_p_br_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ld1w_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/ld1w_z_p_bz.html#ld1w_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ld1w_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ld1w_z_p_bz.html#ld1w_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_ld1w_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1w_z_p_bz.html#ld1w_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1w_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ld1w_z_p_bz.html#ld1w_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ld1w_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ld1w_z_p_bz.html#ld1w_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ld1w_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1w_z_p_bz.html#ld1w_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ld2b_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld2b_z_p_bi.html#ld2b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld2b_z_p_br_contiguous, //!< <a href="../target/aarch64/ld2b_z_p_br.html#ld2b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld2d_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld2d_z_p_bi.html#ld2d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld2d_z_p_br_contiguous, //!< <a href="../target/aarch64/ld2d_z_p_br.html#ld2d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld2h_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld2h_z_p_bi.html#ld2h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld2h_z_p_br_contiguous, //!< <a href="../target/aarch64/ld2h_z_p_br.html#ld2h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld2w_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld2w_z_p_bi.html#ld2w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld2w_z_p_br_contiguous, //!< <a href="../target/aarch64/ld2w_z_p_br.html#ld2w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld3b_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld3b_z_p_bi.html#ld3b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld3b_z_p_br_contiguous, //!< <a href="../target/aarch64/ld3b_z_p_br.html#ld3b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld3d_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld3d_z_p_bi.html#ld3d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld3d_z_p_br_contiguous, //!< <a href="../target/aarch64/ld3d_z_p_br.html#ld3d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld3h_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld3h_z_p_bi.html#ld3h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld3h_z_p_br_contiguous, //!< <a href="../target/aarch64/ld3h_z_p_br.html#ld3h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld3w_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld3w_z_p_bi.html#ld3w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld3w_z_p_br_contiguous, //!< <a href="../target/aarch64/ld3w_z_p_br.html#ld3w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld4b_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld4b_z_p_bi.html#ld4b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld4b_z_p_br_contiguous, //!< <a href="../target/aarch64/ld4b_z_p_br.html#ld4b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld4d_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld4d_z_p_bi.html#ld4d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld4d_z_p_br_contiguous, //!< <a href="../target/aarch64/ld4d_z_p_br.html#ld4d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld4h_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld4h_z_p_bi.html#ld4h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld4h_z_p_br_contiguous, //!< <a href="../target/aarch64/ld4h_z_p_br.html#ld4h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld4w_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld4w_z_p_bi.html#ld4w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ld4w_z_p_br_contiguous, //!< <a href="../target/aarch64/ld4w_z_p_br.html#ld4w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ldff1b_z_p_ai_s, //!< <a href="../target/aarch64/ldff1b_z_p_ai.html#ldff1b_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_ldff1b_z_p_ai_d, //!< <a href="../target/aarch64/ldff1b_z_p_ai.html#ldff1b_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_ldff1b_z_p_br_u8, //!< <a href="../target/aarch64/ldff1b_z_p_br.html#ldff1b_z_p_br_u8">8-bit element</a>
  AMED_AARCH64_ENCODING_ldff1b_z_p_br_u16, //!< <a href="../target/aarch64/ldff1b_z_p_br.html#ldff1b_z_p_br_u16">16-bit element</a>
  AMED_AARCH64_ENCODING_ldff1b_z_p_br_u32, //!< <a href="../target/aarch64/ldff1b_z_p_br.html#ldff1b_z_p_br_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ldff1b_z_p_br_u64, //!< <a href="../target/aarch64/ldff1b_z_p_br.html#ldff1b_z_p_br_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ldff1b_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1b_z_p_bz.html#ldff1b_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1b_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ldff1b_z_p_bz.html#ldff1b_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1b_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1b_z_p_bz.html#ldff1b_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1d_z_p_ai_d, //!< <a href="../target/aarch64/ldff1d_z_p_ai.html#ldff1d_z_p_ai_d">SVE</a>
  AMED_AARCH64_ENCODING_ldff1d_z_p_br_u64, //!< <a href="../target/aarch64/ldff1d_z_p_br.html#ldff1d_z_p_br_u64">SVE</a>
  AMED_AARCH64_ENCODING_ldff1d_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ldff1d_z_p_bz.html#ldff1d_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_ldff1d_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1d_z_p_bz.html#ldff1d_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1d_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ldff1d_z_p_bz.html#ldff1d_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ldff1d_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1d_z_p_bz.html#ldff1d_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1h_z_p_ai_s, //!< <a href="../target/aarch64/ldff1h_z_p_ai.html#ldff1h_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_ldff1h_z_p_ai_d, //!< <a href="../target/aarch64/ldff1h_z_p_ai.html#ldff1h_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_ldff1h_z_p_br_u16, //!< <a href="../target/aarch64/ldff1h_z_p_br.html#ldff1h_z_p_br_u16">16-bit element</a>
  AMED_AARCH64_ENCODING_ldff1h_z_p_br_u32, //!< <a href="../target/aarch64/ldff1h_z_p_br.html#ldff1h_z_p_br_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ldff1h_z_p_br_u64, //!< <a href="../target/aarch64/ldff1h_z_p_br.html#ldff1h_z_p_br_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ldff1h_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/ldff1h_z_p_bz.html#ldff1h_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ldff1h_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ldff1h_z_p_bz.html#ldff1h_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_ldff1h_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1h_z_p_bz.html#ldff1h_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1h_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ldff1h_z_p_bz.html#ldff1h_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1h_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ldff1h_z_p_bz.html#ldff1h_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ldff1h_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1h_z_p_bz.html#ldff1h_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1sb_z_p_ai_s, //!< <a href="../target/aarch64/ldff1sb_z_p_ai.html#ldff1sb_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_ldff1sb_z_p_ai_d, //!< <a href="../target/aarch64/ldff1sb_z_p_ai.html#ldff1sb_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_ldff1sb_z_p_br_s16, //!< <a href="../target/aarch64/ldff1sb_z_p_br.html#ldff1sb_z_p_br_s16">16-bit element</a>
  AMED_AARCH64_ENCODING_ldff1sb_z_p_br_s32, //!< <a href="../target/aarch64/ldff1sb_z_p_br.html#ldff1sb_z_p_br_s32">32-bit element</a>
  AMED_AARCH64_ENCODING_ldff1sb_z_p_br_s64, //!< <a href="../target/aarch64/ldff1sb_z_p_br.html#ldff1sb_z_p_br_s64">64-bit element</a>
  AMED_AARCH64_ENCODING_ldff1sb_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1sb_z_p_bz.html#ldff1sb_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1sb_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ldff1sb_z_p_bz.html#ldff1sb_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1sb_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1sb_z_p_bz.html#ldff1sb_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1sh_z_p_ai_s, //!< <a href="../target/aarch64/ldff1sh_z_p_ai.html#ldff1sh_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_ldff1sh_z_p_ai_d, //!< <a href="../target/aarch64/ldff1sh_z_p_ai.html#ldff1sh_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_ldff1sh_z_p_br_s32, //!< <a href="../target/aarch64/ldff1sh_z_p_br.html#ldff1sh_z_p_br_s32">32-bit element</a>
  AMED_AARCH64_ENCODING_ldff1sh_z_p_br_s64, //!< <a href="../target/aarch64/ldff1sh_z_p_br.html#ldff1sh_z_p_br_s64">64-bit element</a>
  AMED_AARCH64_ENCODING_ldff1sh_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/ldff1sh_z_p_bz.html#ldff1sh_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ldff1sh_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ldff1sh_z_p_bz.html#ldff1sh_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_ldff1sh_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1sh_z_p_bz.html#ldff1sh_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1sh_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ldff1sh_z_p_bz.html#ldff1sh_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1sh_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ldff1sh_z_p_bz.html#ldff1sh_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ldff1sh_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1sh_z_p_bz.html#ldff1sh_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1sw_z_p_ai_d, //!< <a href="../target/aarch64/ldff1sw_z_p_ai.html#ldff1sw_z_p_ai_d">SVE</a>
  AMED_AARCH64_ENCODING_ldff1sw_z_p_br_s64, //!< <a href="../target/aarch64/ldff1sw_z_p_br.html#ldff1sw_z_p_br_s64">SVE</a>
  AMED_AARCH64_ENCODING_ldff1sw_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ldff1sw_z_p_bz.html#ldff1sw_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_ldff1sw_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1sw_z_p_bz.html#ldff1sw_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1sw_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ldff1sw_z_p_bz.html#ldff1sw_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ldff1sw_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1sw_z_p_bz.html#ldff1sw_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1w_z_p_ai_s, //!< <a href="../target/aarch64/ldff1w_z_p_ai.html#ldff1w_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_ldff1w_z_p_ai_d, //!< <a href="../target/aarch64/ldff1w_z_p_ai.html#ldff1w_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_ldff1w_z_p_br_u32, //!< <a href="../target/aarch64/ldff1w_z_p_br.html#ldff1w_z_p_br_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ldff1w_z_p_br_u64, //!< <a href="../target/aarch64/ldff1w_z_p_br.html#ldff1w_z_p_br_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ldff1w_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/ldff1w_z_p_bz.html#ldff1w_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ldff1w_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ldff1w_z_p_bz.html#ldff1w_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_ldff1w_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1w_z_p_bz.html#ldff1w_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1w_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ldff1w_z_p_bz.html#ldff1w_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldff1w_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ldff1w_z_p_bz.html#ldff1w_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ldff1w_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1w_z_p_bz.html#ldff1w_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldnf1b_z_p_bi_u8, //!< <a href="../target/aarch64/ldnf1b_z_p_bi.html#ldnf1b_z_p_bi_u8">8-bit element</a>
  AMED_AARCH64_ENCODING_ldnf1b_z_p_bi_u16, //!< <a href="../target/aarch64/ldnf1b_z_p_bi.html#ldnf1b_z_p_bi_u16">16-bit element</a>
  AMED_AARCH64_ENCODING_ldnf1b_z_p_bi_u32, //!< <a href="../target/aarch64/ldnf1b_z_p_bi.html#ldnf1b_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ldnf1b_z_p_bi_u64, //!< <a href="../target/aarch64/ldnf1b_z_p_bi.html#ldnf1b_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ldnf1d_z_p_bi_u64, //!< <a href="../target/aarch64/ldnf1d_z_p_bi.html#ldnf1d_z_p_bi_u64">SVE</a>
  AMED_AARCH64_ENCODING_ldnf1h_z_p_bi_u16, //!< <a href="../target/aarch64/ldnf1h_z_p_bi.html#ldnf1h_z_p_bi_u16">16-bit element</a>
  AMED_AARCH64_ENCODING_ldnf1h_z_p_bi_u32, //!< <a href="../target/aarch64/ldnf1h_z_p_bi.html#ldnf1h_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ldnf1h_z_p_bi_u64, //!< <a href="../target/aarch64/ldnf1h_z_p_bi.html#ldnf1h_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ldnf1sb_z_p_bi_s16, //!< <a href="../target/aarch64/ldnf1sb_z_p_bi.html#ldnf1sb_z_p_bi_s16">16-bit element</a>
  AMED_AARCH64_ENCODING_ldnf1sb_z_p_bi_s32, //!< <a href="../target/aarch64/ldnf1sb_z_p_bi.html#ldnf1sb_z_p_bi_s32">32-bit element</a>
  AMED_AARCH64_ENCODING_ldnf1sb_z_p_bi_s64, //!< <a href="../target/aarch64/ldnf1sb_z_p_bi.html#ldnf1sb_z_p_bi_s64">64-bit element</a>
  AMED_AARCH64_ENCODING_ldnf1sh_z_p_bi_s32, //!< <a href="../target/aarch64/ldnf1sh_z_p_bi.html#ldnf1sh_z_p_bi_s32">32-bit element</a>
  AMED_AARCH64_ENCODING_ldnf1sh_z_p_bi_s64, //!< <a href="../target/aarch64/ldnf1sh_z_p_bi.html#ldnf1sh_z_p_bi_s64">64-bit element</a>
  AMED_AARCH64_ENCODING_ldnf1sw_z_p_bi_s64, //!< <a href="../target/aarch64/ldnf1sw_z_p_bi.html#ldnf1sw_z_p_bi_s64">SVE</a>
  AMED_AARCH64_ENCODING_ldnf1w_z_p_bi_u32, //!< <a href="../target/aarch64/ldnf1w_z_p_bi.html#ldnf1w_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_ENCODING_ldnf1w_z_p_bi_u64, //!< <a href="../target/aarch64/ldnf1w_z_p_bi.html#ldnf1w_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_ENCODING_ldnt1b_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/ldnt1b_z_p_ar.html#ldnt1b_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldnt1b_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1b_z_p_ar.html#ldnt1b_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldnt1b_z_p_bi_contiguous, //!< <a href="../target/aarch64/ldnt1b_z_p_bi.html#ldnt1b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ldnt1b_z_p_br_contiguous, //!< <a href="../target/aarch64/ldnt1b_z_p_br.html#ldnt1b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ldnt1d_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1d_z_p_ar.html#ldnt1d_z_p_ar_d_64_unscaled">SVE2</a>
  AMED_AARCH64_ENCODING_ldnt1d_z_p_bi_contiguous, //!< <a href="../target/aarch64/ldnt1d_z_p_bi.html#ldnt1d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ldnt1d_z_p_br_contiguous, //!< <a href="../target/aarch64/ldnt1d_z_p_br.html#ldnt1d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ldnt1h_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/ldnt1h_z_p_ar.html#ldnt1h_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldnt1h_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1h_z_p_ar.html#ldnt1h_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldnt1h_z_p_bi_contiguous, //!< <a href="../target/aarch64/ldnt1h_z_p_bi.html#ldnt1h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ldnt1h_z_p_br_contiguous, //!< <a href="../target/aarch64/ldnt1h_z_p_br.html#ldnt1h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ldnt1sb_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/ldnt1sb_z_p_ar.html#ldnt1sb_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldnt1sb_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1sb_z_p_ar.html#ldnt1sb_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldnt1sh_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/ldnt1sh_z_p_ar.html#ldnt1sh_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldnt1sh_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1sh_z_p_ar.html#ldnt1sh_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldnt1sw_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1sw_z_p_ar.html#ldnt1sw_z_p_ar_d_64_unscaled">SVE2</a>
  AMED_AARCH64_ENCODING_ldnt1w_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/ldnt1w_z_p_ar.html#ldnt1w_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldnt1w_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1w_z_p_ar.html#ldnt1w_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_ldnt1w_z_p_bi_contiguous, //!< <a href="../target/aarch64/ldnt1w_z_p_bi.html#ldnt1w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ldnt1w_z_p_br_contiguous, //!< <a href="../target/aarch64/ldnt1w_z_p_br.html#ldnt1w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_ldr_p_bi_, //!< <a href="../target/aarch64/ldr_p_bi.html#ldr_p_bi_">SVE</a>
  AMED_AARCH64_ENCODING_ldr_z_bi_, //!< <a href="../target/aarch64/ldr_z_bi.html#ldr_z_bi_">SVE</a>
  AMED_AARCH64_ENCODING_lsl_z_p_zi_, //!< <a href="../target/aarch64/lsl_z_p_zi.html#lsl_z_p_zi_">SVE</a>
  AMED_AARCH64_ENCODING_lsl_z_p_zw_, //!< <a href="../target/aarch64/lsl_z_p_zw.html#lsl_z_p_zw_">SVE</a>
  AMED_AARCH64_ENCODING_lsl_z_p_zz_, //!< <a href="../target/aarch64/lsl_z_p_zz.html#lsl_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_lsl_z_zi_, //!< <a href="../target/aarch64/lsl_z_zi.html#lsl_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_lsl_z_zw_, //!< <a href="../target/aarch64/lsl_z_zw.html#lsl_z_zw_">SVE</a>
  AMED_AARCH64_ENCODING_lslr_z_p_zz_, //!< <a href="../target/aarch64/lslr_z_p_zz.html#lslr_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_lsr_z_p_zi_, //!< <a href="../target/aarch64/lsr_z_p_zi.html#lsr_z_p_zi_">SVE</a>
  AMED_AARCH64_ENCODING_lsr_z_p_zw_, //!< <a href="../target/aarch64/lsr_z_p_zw.html#lsr_z_p_zw_">SVE</a>
  AMED_AARCH64_ENCODING_lsr_z_p_zz_, //!< <a href="../target/aarch64/lsr_z_p_zz.html#lsr_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_lsr_z_zi_, //!< <a href="../target/aarch64/lsr_z_zi.html#lsr_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_lsr_z_zw_, //!< <a href="../target/aarch64/lsr_z_zw.html#lsr_z_zw_">SVE</a>
  AMED_AARCH64_ENCODING_lsrr_z_p_zz_, //!< <a href="../target/aarch64/lsrr_z_p_zz.html#lsrr_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_mad_z_p_zzz_, //!< <a href="../target/aarch64/mad_z_p_zzz.html#mad_z_p_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_match_p_p_zz_, //!< <a href="../target/aarch64/match_p_p_zz.html#match_p_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_mla_z_p_zzz_, //!< <a href="../target/aarch64/mla_z_p_zzz.html#mla_z_p_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_mla_z_zzzi_h, //!< <a href="../target/aarch64/mla_z_zzzi.html#mla_z_zzzi_h">16-bit</a>
  AMED_AARCH64_ENCODING_mla_z_zzzi_s, //!< <a href="../target/aarch64/mla_z_zzzi.html#mla_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_mla_z_zzzi_d, //!< <a href="../target/aarch64/mla_z_zzzi.html#mla_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_mls_z_p_zzz_, //!< <a href="../target/aarch64/mls_z_p_zzz.html#mls_z_p_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_mls_z_zzzi_h, //!< <a href="../target/aarch64/mls_z_zzzi.html#mls_z_zzzi_h">16-bit</a>
  AMED_AARCH64_ENCODING_mls_z_zzzi_s, //!< <a href="../target/aarch64/mls_z_zzzi.html#mls_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_mls_z_zzzi_d, //!< <a href="../target/aarch64/mls_z_zzzi.html#mls_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_movprfx_z_p_z_, //!< <a href="../target/aarch64/movprfx_z_p_z.html#movprfx_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_movprfx_z_z_, //!< <a href="../target/aarch64/movprfx_z_z.html#movprfx_z_z_">SVE</a>
  AMED_AARCH64_ENCODING_msb_z_p_zzz_, //!< <a href="../target/aarch64/msb_z_p_zzz.html#msb_z_p_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_mul_z_p_zz_, //!< <a href="../target/aarch64/mul_z_p_zz.html#mul_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_mul_z_zi_, //!< <a href="../target/aarch64/mul_z_zi.html#mul_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_mul_z_zz_, //!< <a href="../target/aarch64/mul_z_zz.html#mul_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_mul_z_zzi_h, //!< <a href="../target/aarch64/mul_z_zzi.html#mul_z_zzi_h">16-bit</a>
  AMED_AARCH64_ENCODING_mul_z_zzi_s, //!< <a href="../target/aarch64/mul_z_zzi.html#mul_z_zzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_mul_z_zzi_d, //!< <a href="../target/aarch64/mul_z_zzi.html#mul_z_zzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_nand_p_p_pp_z, //!< <a href="../target/aarch64/nand_p_p_pp.html#nand_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_nands_p_p_pp_z, //!< <a href="../target/aarch64/nand_p_p_pp.html#nands_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_nbsl_z_zzz_, //!< <a href="../target/aarch64/nbsl_z_zzz.html#nbsl_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_neg_z_p_z_, //!< <a href="../target/aarch64/neg_z_p_z.html#neg_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_nmatch_p_p_zz_, //!< <a href="../target/aarch64/nmatch_p_p_zz.html#nmatch_p_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_nor_p_p_pp_z, //!< <a href="../target/aarch64/nor_p_p_pp.html#nor_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_nors_p_p_pp_z, //!< <a href="../target/aarch64/nor_p_p_pp.html#nors_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_not_z_p_z_, //!< <a href="../target/aarch64/not_z_p_z.html#not_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_orn_p_p_pp_z, //!< <a href="../target/aarch64/orn_p_p_pp.html#orn_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_orns_p_p_pp_z, //!< <a href="../target/aarch64/orn_p_p_pp.html#orns_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_orr_p_p_pp_z, //!< <a href="../target/aarch64/orr_p_p_pp.html#orr_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_orrs_p_p_pp_z, //!< <a href="../target/aarch64/orr_p_p_pp.html#orrs_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_orr_z_p_zz_, //!< <a href="../target/aarch64/orr_z_p_zz.html#orr_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_orr_z_zi_, //!< <a href="../target/aarch64/orr_z_zi.html#orr_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_orr_z_zz_, //!< <a href="../target/aarch64/orr_z_zz.html#orr_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_orv_r_p_z_, //!< <a href="../target/aarch64/orv_r_p_z.html#orv_r_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_pfalse_p_, //!< <a href="../target/aarch64/pfalse_p.html#pfalse_p_">SVE</a>
  AMED_AARCH64_ENCODING_pfirst_p_p_p_, //!< <a href="../target/aarch64/pfirst_p_p_p.html#pfirst_p_p_p_">SVE</a>
  AMED_AARCH64_ENCODING_pmul_z_zz_, //!< <a href="../target/aarch64/pmul_z_zz.html#pmul_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_pmullb_z_zz_, //!< <a href="../target/aarch64/pmullb_z_zz.html#pmullb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_pmullt_z_zz_, //!< <a href="../target/aarch64/pmullt_z_zz.html#pmullt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_pnext_p_p_p_, //!< <a href="../target/aarch64/pnext_p_p_p.html#pnext_p_p_p_">SVE</a>
  AMED_AARCH64_ENCODING_prfb_i_p_ai_s, //!< <a href="../target/aarch64/prfb_i_p_ai.html#prfb_i_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_prfb_i_p_ai_d, //!< <a href="../target/aarch64/prfb_i_p_ai.html#prfb_i_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_prfb_i_p_bi_s, //!< <a href="../target/aarch64/prfb_i_p_bi.html#prfb_i_p_bi_s">SVE</a>
  AMED_AARCH64_ENCODING_prfb_i_p_br_s, //!< <a href="../target/aarch64/prfb_i_p_br.html#prfb_i_p_br_s">SVE</a>
  AMED_AARCH64_ENCODING_prfb_i_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/prfb_i_p_bz.html#prfb_i_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_ENCODING_prfb_i_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/prfb_i_p_bz.html#prfb_i_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_prfb_i_p_bz_d_64_scaled, //!< <a href="../target/aarch64/prfb_i_p_bz.html#prfb_i_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_prfd_i_p_ai_s, //!< <a href="../target/aarch64/prfd_i_p_ai.html#prfd_i_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_prfd_i_p_ai_d, //!< <a href="../target/aarch64/prfd_i_p_ai.html#prfd_i_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_prfd_i_p_bi_s, //!< <a href="../target/aarch64/prfd_i_p_bi.html#prfd_i_p_bi_s">SVE</a>
  AMED_AARCH64_ENCODING_prfd_i_p_br_s, //!< <a href="../target/aarch64/prfd_i_p_br.html#prfd_i_p_br_s">SVE</a>
  AMED_AARCH64_ENCODING_prfd_i_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/prfd_i_p_bz.html#prfd_i_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_ENCODING_prfd_i_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/prfd_i_p_bz.html#prfd_i_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_prfd_i_p_bz_d_64_scaled, //!< <a href="../target/aarch64/prfd_i_p_bz.html#prfd_i_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_prfh_i_p_ai_s, //!< <a href="../target/aarch64/prfh_i_p_ai.html#prfh_i_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_prfh_i_p_ai_d, //!< <a href="../target/aarch64/prfh_i_p_ai.html#prfh_i_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_prfh_i_p_bi_s, //!< <a href="../target/aarch64/prfh_i_p_bi.html#prfh_i_p_bi_s">SVE</a>
  AMED_AARCH64_ENCODING_prfh_i_p_br_s, //!< <a href="../target/aarch64/prfh_i_p_br.html#prfh_i_p_br_s">SVE</a>
  AMED_AARCH64_ENCODING_prfh_i_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/prfh_i_p_bz.html#prfh_i_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_ENCODING_prfh_i_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/prfh_i_p_bz.html#prfh_i_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_prfh_i_p_bz_d_64_scaled, //!< <a href="../target/aarch64/prfh_i_p_bz.html#prfh_i_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_prfw_i_p_ai_s, //!< <a href="../target/aarch64/prfw_i_p_ai.html#prfw_i_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_prfw_i_p_ai_d, //!< <a href="../target/aarch64/prfw_i_p_ai.html#prfw_i_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_prfw_i_p_bi_s, //!< <a href="../target/aarch64/prfw_i_p_bi.html#prfw_i_p_bi_s">SVE</a>
  AMED_AARCH64_ENCODING_prfw_i_p_br_s, //!< <a href="../target/aarch64/prfw_i_p_br.html#prfw_i_p_br_s">SVE</a>
  AMED_AARCH64_ENCODING_prfw_i_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/prfw_i_p_bz.html#prfw_i_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_ENCODING_prfw_i_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/prfw_i_p_bz.html#prfw_i_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_prfw_i_p_bz_d_64_scaled, //!< <a href="../target/aarch64/prfw_i_p_bz.html#prfw_i_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_ptest_p_p_, //!< <a href="../target/aarch64/ptest_p_p.html#ptest_p_p_">SVE</a>
  AMED_AARCH64_ENCODING_ptrue_p_s_, //!< <a href="../target/aarch64/ptrue_p_s.html#ptrue_p_s_">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_ptrues_p_s_, //!< <a href="../target/aarch64/ptrue_p_s.html#ptrues_p_s_">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_punpkhi_p_p_, //!< <a href="../target/aarch64/punpkhi_p_p.html#punpkhi_p_p_">High half</a>
  AMED_AARCH64_ENCODING_punpklo_p_p_, //!< <a href="../target/aarch64/punpkhi_p_p.html#punpklo_p_p_">Low half</a>
  AMED_AARCH64_ENCODING_raddhnb_z_zz_, //!< <a href="../target/aarch64/raddhnb_z_zz.html#raddhnb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_raddhnt_z_zz_, //!< <a href="../target/aarch64/raddhnt_z_zz.html#raddhnt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_rax1_z_zz_, //!< <a href="../target/aarch64/rax1_z_zz.html#rax1_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_rbit_z_p_z_, //!< <a href="../target/aarch64/rbit_z_p_z.html#rbit_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_rdffr_p_f_, //!< <a href="../target/aarch64/rdffr_p_f.html#rdffr_p_f_">SVE</a>
  AMED_AARCH64_ENCODING_rdffr_p_p_f_, //!< <a href="../target/aarch64/rdffr_p_p_f.html#rdffr_p_p_f_">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_rdffrs_p_p_f_, //!< <a href="../target/aarch64/rdffr_p_p_f.html#rdffrs_p_p_f_">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_rdvl_r_i_, //!< <a href="../target/aarch64/rdvl_r_i.html#rdvl_r_i_">SVE</a>
  AMED_AARCH64_ENCODING_rev_p_p_, //!< <a href="../target/aarch64/rev_p_p.html#rev_p_p_">SVE</a>
  AMED_AARCH64_ENCODING_rev_z_z_, //!< <a href="../target/aarch64/rev_z_z.html#rev_z_z_">SVE</a>
  AMED_AARCH64_ENCODING_revb_z_z_, //!< <a href="../target/aarch64/revb_z_z.html#revb_z_z_">Byte</a>
  AMED_AARCH64_ENCODING_revh_z_z_, //!< <a href="../target/aarch64/revb_z_z.html#revh_z_z_">Halfword</a>
  AMED_AARCH64_ENCODING_revw_z_z_, //!< <a href="../target/aarch64/revb_z_z.html#revw_z_z_">Word</a>
  AMED_AARCH64_ENCODING_rshrnb_z_zi_, //!< <a href="../target/aarch64/rshrnb_z_zi.html#rshrnb_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_rshrnt_z_zi_, //!< <a href="../target/aarch64/rshrnt_z_zi.html#rshrnt_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_rsubhnb_z_zz_, //!< <a href="../target/aarch64/rsubhnb_z_zz.html#rsubhnb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_rsubhnt_z_zz_, //!< <a href="../target/aarch64/rsubhnt_z_zz.html#rsubhnt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_saba_z_zzz_, //!< <a href="../target/aarch64/saba_z_zzz.html#saba_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_sabalb_z_zzz_, //!< <a href="../target/aarch64/sabalb_z_zzz.html#sabalb_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_sabalt_z_zzz_, //!< <a href="../target/aarch64/sabalt_z_zzz.html#sabalt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_sabd_z_p_zz_, //!< <a href="../target/aarch64/sabd_z_p_zz.html#sabd_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_sabdlb_z_zz_, //!< <a href="../target/aarch64/sabdlb_z_zz.html#sabdlb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sabdlt_z_zz_, //!< <a href="../target/aarch64/sabdlt_z_zz.html#sabdlt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sadalp_z_p_z_, //!< <a href="../target/aarch64/sadalp_z_p_z.html#sadalp_z_p_z_">SVE2</a>
  AMED_AARCH64_ENCODING_saddlb_z_zz_, //!< <a href="../target/aarch64/saddlb_z_zz.html#saddlb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_saddlbt_z_zz_, //!< <a href="../target/aarch64/saddlbt_z_zz.html#saddlbt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_saddlt_z_zz_, //!< <a href="../target/aarch64/saddlt_z_zz.html#saddlt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_saddv_r_p_z_, //!< <a href="../target/aarch64/saddv_r_p_z.html#saddv_r_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_saddwb_z_zz_, //!< <a href="../target/aarch64/saddwb_z_zz.html#saddwb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_saddwt_z_zz_, //!< <a href="../target/aarch64/saddwt_z_zz.html#saddwt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sbclb_z_zzz_, //!< <a href="../target/aarch64/sbclb_z_zzz.html#sbclb_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_sbclt_z_zzz_, //!< <a href="../target/aarch64/sbclt_z_zzz.html#sbclt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_scvtf_z_p_z_h2fp16, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_h2fp16">16-bit to half-precision</a>
  AMED_AARCH64_ENCODING_scvtf_z_p_z_w2fp16, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_w2fp16">32-bit to half-precision</a>
  AMED_AARCH64_ENCODING_scvtf_z_p_z_w2s, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_w2s">32-bit to single-precision</a>
  AMED_AARCH64_ENCODING_scvtf_z_p_z_w2d, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_w2d">32-bit to double-precision</a>
  AMED_AARCH64_ENCODING_scvtf_z_p_z_x2fp16, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_x2fp16">64-bit to half-precision</a>
  AMED_AARCH64_ENCODING_scvtf_z_p_z_x2s, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_x2s">64-bit to single-precision</a>
  AMED_AARCH64_ENCODING_scvtf_z_p_z_x2d, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_x2d">64-bit to double-precision</a>
  AMED_AARCH64_ENCODING_sdiv_z_p_zz_, //!< <a href="../target/aarch64/sdiv_z_p_zz.html#sdiv_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_sdivr_z_p_zz_, //!< <a href="../target/aarch64/sdivr_z_p_zz.html#sdivr_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_sdot_z_zzz_, //!< <a href="../target/aarch64/sdot_z_zzz.html#sdot_z_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_sdot_z_zzzi_s, //!< <a href="../target/aarch64/sdot_z_zzzi.html#sdot_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_sdot_z_zzzi_d, //!< <a href="../target/aarch64/sdot_z_zzzi.html#sdot_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_sel_p_p_pp_, //!< <a href="../target/aarch64/sel_p_p_pp.html#sel_p_p_pp_">SVE</a>
  AMED_AARCH64_ENCODING_sel_z_p_zz_, //!< <a href="../target/aarch64/sel_z_p_zz.html#sel_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_setffr_f_, //!< <a href="../target/aarch64/setffr_f.html#setffr_f_">SVE</a>
  AMED_AARCH64_ENCODING_shadd_z_p_zz_, //!< <a href="../target/aarch64/shadd_z_p_zz.html#shadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_shrnb_z_zi_, //!< <a href="../target/aarch64/shrnb_z_zi.html#shrnb_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_shrnt_z_zi_, //!< <a href="../target/aarch64/shrnt_z_zi.html#shrnt_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_shsub_z_p_zz_, //!< <a href="../target/aarch64/shsub_z_p_zz.html#shsub_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_shsubr_z_p_zz_, //!< <a href="../target/aarch64/shsubr_z_p_zz.html#shsubr_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sli_z_zzi_, //!< <a href="../target/aarch64/sli_z_zzi.html#sli_z_zzi_">SVE2</a>
  AMED_AARCH64_ENCODING_sm4e_z_zz_, //!< <a href="../target/aarch64/sm4e_z_zz.html#sm4e_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sm4ekey_z_zz_, //!< <a href="../target/aarch64/sm4ekey_z_zz.html#sm4ekey_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_smax_z_p_zz_, //!< <a href="../target/aarch64/smax_z_p_zz.html#smax_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_smax_z_zi_, //!< <a href="../target/aarch64/smax_z_zi.html#smax_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_smaxp_z_p_zz_, //!< <a href="../target/aarch64/smaxp_z_p_zz.html#smaxp_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_smaxv_r_p_z_, //!< <a href="../target/aarch64/smaxv_r_p_z.html#smaxv_r_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_smin_z_p_zz_, //!< <a href="../target/aarch64/smin_z_p_zz.html#smin_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_smin_z_zi_, //!< <a href="../target/aarch64/smin_z_zi.html#smin_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_sminp_z_p_zz_, //!< <a href="../target/aarch64/sminp_z_p_zz.html#sminp_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sminv_r_p_z_, //!< <a href="../target/aarch64/sminv_r_p_z.html#sminv_r_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_smlalb_z_zzz_, //!< <a href="../target/aarch64/smlalb_z_zzz.html#smlalb_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_smlalb_z_zzzi_s, //!< <a href="../target/aarch64/smlalb_z_zzzi.html#smlalb_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_smlalb_z_zzzi_d, //!< <a href="../target/aarch64/smlalb_z_zzzi.html#smlalb_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_smlalt_z_zzz_, //!< <a href="../target/aarch64/smlalt_z_zzz.html#smlalt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_smlalt_z_zzzi_s, //!< <a href="../target/aarch64/smlalt_z_zzzi.html#smlalt_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_smlalt_z_zzzi_d, //!< <a href="../target/aarch64/smlalt_z_zzzi.html#smlalt_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_smlslb_z_zzz_, //!< <a href="../target/aarch64/smlslb_z_zzz.html#smlslb_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_smlslb_z_zzzi_s, //!< <a href="../target/aarch64/smlslb_z_zzzi.html#smlslb_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_smlslb_z_zzzi_d, //!< <a href="../target/aarch64/smlslb_z_zzzi.html#smlslb_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_smlslt_z_zzz_, //!< <a href="../target/aarch64/smlslt_z_zzz.html#smlslt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_smlslt_z_zzzi_s, //!< <a href="../target/aarch64/smlslt_z_zzzi.html#smlslt_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_smlslt_z_zzzi_d, //!< <a href="../target/aarch64/smlslt_z_zzzi.html#smlslt_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_smmla_z_zzz_, //!< <a href="../target/aarch64/smmla_z_zzz.html#smmla_z_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_smulh_z_p_zz_, //!< <a href="../target/aarch64/smulh_z_p_zz.html#smulh_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_smulh_z_zz_, //!< <a href="../target/aarch64/smulh_z_zz.html#smulh_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_smullb_z_zz_, //!< <a href="../target/aarch64/smullb_z_zz.html#smullb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_smullb_z_zzi_s, //!< <a href="../target/aarch64/smullb_z_zzi.html#smullb_z_zzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_smullb_z_zzi_d, //!< <a href="../target/aarch64/smullb_z_zzi.html#smullb_z_zzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_smullt_z_zz_, //!< <a href="../target/aarch64/smullt_z_zz.html#smullt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_smullt_z_zzi_s, //!< <a href="../target/aarch64/smullt_z_zzi.html#smullt_z_zzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_smullt_z_zzi_d, //!< <a href="../target/aarch64/smullt_z_zzi.html#smullt_z_zzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_splice_z_p_zz_con, //!< <a href="../target/aarch64/splice_z_p_zz.html#splice_z_p_zz_con">Constructive</a>
  AMED_AARCH64_ENCODING_splice_z_p_zz_des, //!< <a href="../target/aarch64/splice_z_p_zz.html#splice_z_p_zz_des">Destructive</a>
  AMED_AARCH64_ENCODING_sqabs_z_p_z_, //!< <a href="../target/aarch64/sqabs_z_p_z.html#sqabs_z_p_z_">SVE2</a>
  AMED_AARCH64_ENCODING_sqadd_z_p_zz_, //!< <a href="../target/aarch64/sqadd_z_p_zz.html#sqadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqadd_z_zi_, //!< <a href="../target/aarch64/sqadd_z_zi.html#sqadd_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_sqadd_z_zz_, //!< <a href="../target/aarch64/sqadd_z_zz.html#sqadd_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_sqcadd_z_zz_, //!< <a href="../target/aarch64/sqcadd_z_zz.html#sqcadd_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqdecb_r_rs_sx, //!< <a href="../target/aarch64/sqdecb_r_rs.html#sqdecb_r_rs_sx">32-bit</a>
  AMED_AARCH64_ENCODING_sqdecb_r_rs_x, //!< <a href="../target/aarch64/sqdecb_r_rs.html#sqdecb_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_sqdecd_r_rs_sx, //!< <a href="../target/aarch64/sqdecd_r_rs.html#sqdecd_r_rs_sx">32-bit</a>
  AMED_AARCH64_ENCODING_sqdecd_r_rs_x, //!< <a href="../target/aarch64/sqdecd_r_rs.html#sqdecd_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_sqdecd_z_zs_, //!< <a href="../target/aarch64/sqdecd_z_zs.html#sqdecd_z_zs_">SVE</a>
  AMED_AARCH64_ENCODING_sqdech_r_rs_sx, //!< <a href="../target/aarch64/sqdech_r_rs.html#sqdech_r_rs_sx">32-bit</a>
  AMED_AARCH64_ENCODING_sqdech_r_rs_x, //!< <a href="../target/aarch64/sqdech_r_rs.html#sqdech_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_sqdech_z_zs_, //!< <a href="../target/aarch64/sqdech_z_zs.html#sqdech_z_zs_">SVE</a>
  AMED_AARCH64_ENCODING_sqdecp_r_p_r_sx, //!< <a href="../target/aarch64/sqdecp_r_p_r.html#sqdecp_r_p_r_sx">32-bit</a>
  AMED_AARCH64_ENCODING_sqdecp_r_p_r_x, //!< <a href="../target/aarch64/sqdecp_r_p_r.html#sqdecp_r_p_r_x">64-bit</a>
  AMED_AARCH64_ENCODING_sqdecp_z_p_z_, //!< <a href="../target/aarch64/sqdecp_z_p_z.html#sqdecp_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_sqdecw_r_rs_sx, //!< <a href="../target/aarch64/sqdecw_r_rs.html#sqdecw_r_rs_sx">32-bit</a>
  AMED_AARCH64_ENCODING_sqdecw_r_rs_x, //!< <a href="../target/aarch64/sqdecw_r_rs.html#sqdecw_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_sqdecw_z_zs_, //!< <a href="../target/aarch64/sqdecw_z_zs.html#sqdecw_z_zs_">SVE</a>
  AMED_AARCH64_ENCODING_sqdmlalb_z_zzz_, //!< <a href="../target/aarch64/sqdmlalb_z_zzz.html#sqdmlalb_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqdmlalb_z_zzzi_s, //!< <a href="../target/aarch64/sqdmlalb_z_zzzi.html#sqdmlalb_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_sqdmlalb_z_zzzi_d, //!< <a href="../target/aarch64/sqdmlalb_z_zzzi.html#sqdmlalb_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_sqdmlalbt_z_zzz_, //!< <a href="../target/aarch64/sqdmlalbt_z_zzz.html#sqdmlalbt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqdmlalt_z_zzz_, //!< <a href="../target/aarch64/sqdmlalt_z_zzz.html#sqdmlalt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqdmlalt_z_zzzi_s, //!< <a href="../target/aarch64/sqdmlalt_z_zzzi.html#sqdmlalt_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_sqdmlalt_z_zzzi_d, //!< <a href="../target/aarch64/sqdmlalt_z_zzzi.html#sqdmlalt_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_sqdmlslb_z_zzz_, //!< <a href="../target/aarch64/sqdmlslb_z_zzz.html#sqdmlslb_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqdmlslb_z_zzzi_s, //!< <a href="../target/aarch64/sqdmlslb_z_zzzi.html#sqdmlslb_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_sqdmlslb_z_zzzi_d, //!< <a href="../target/aarch64/sqdmlslb_z_zzzi.html#sqdmlslb_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_sqdmlslbt_z_zzz_, //!< <a href="../target/aarch64/sqdmlslbt_z_zzz.html#sqdmlslbt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqdmlslt_z_zzz_, //!< <a href="../target/aarch64/sqdmlslt_z_zzz.html#sqdmlslt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqdmlslt_z_zzzi_s, //!< <a href="../target/aarch64/sqdmlslt_z_zzzi.html#sqdmlslt_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_sqdmlslt_z_zzzi_d, //!< <a href="../target/aarch64/sqdmlslt_z_zzzi.html#sqdmlslt_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_sqdmulh_z_zz_, //!< <a href="../target/aarch64/sqdmulh_z_zz.html#sqdmulh_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqdmulh_z_zzi_h, //!< <a href="../target/aarch64/sqdmulh_z_zzi.html#sqdmulh_z_zzi_h">16-bit</a>
  AMED_AARCH64_ENCODING_sqdmulh_z_zzi_s, //!< <a href="../target/aarch64/sqdmulh_z_zzi.html#sqdmulh_z_zzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_sqdmulh_z_zzi_d, //!< <a href="../target/aarch64/sqdmulh_z_zzi.html#sqdmulh_z_zzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_sqdmullb_z_zz_, //!< <a href="../target/aarch64/sqdmullb_z_zz.html#sqdmullb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqdmullb_z_zzi_s, //!< <a href="../target/aarch64/sqdmullb_z_zzi.html#sqdmullb_z_zzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_sqdmullb_z_zzi_d, //!< <a href="../target/aarch64/sqdmullb_z_zzi.html#sqdmullb_z_zzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_sqdmullt_z_zz_, //!< <a href="../target/aarch64/sqdmullt_z_zz.html#sqdmullt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqdmullt_z_zzi_s, //!< <a href="../target/aarch64/sqdmullt_z_zzi.html#sqdmullt_z_zzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_sqdmullt_z_zzi_d, //!< <a href="../target/aarch64/sqdmullt_z_zzi.html#sqdmullt_z_zzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_sqincb_r_rs_sx, //!< <a href="../target/aarch64/sqincb_r_rs.html#sqincb_r_rs_sx">32-bit</a>
  AMED_AARCH64_ENCODING_sqincb_r_rs_x, //!< <a href="../target/aarch64/sqincb_r_rs.html#sqincb_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_sqincd_r_rs_sx, //!< <a href="../target/aarch64/sqincd_r_rs.html#sqincd_r_rs_sx">32-bit</a>
  AMED_AARCH64_ENCODING_sqincd_r_rs_x, //!< <a href="../target/aarch64/sqincd_r_rs.html#sqincd_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_sqincd_z_zs_, //!< <a href="../target/aarch64/sqincd_z_zs.html#sqincd_z_zs_">SVE</a>
  AMED_AARCH64_ENCODING_sqinch_r_rs_sx, //!< <a href="../target/aarch64/sqinch_r_rs.html#sqinch_r_rs_sx">32-bit</a>
  AMED_AARCH64_ENCODING_sqinch_r_rs_x, //!< <a href="../target/aarch64/sqinch_r_rs.html#sqinch_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_sqinch_z_zs_, //!< <a href="../target/aarch64/sqinch_z_zs.html#sqinch_z_zs_">SVE</a>
  AMED_AARCH64_ENCODING_sqincp_r_p_r_sx, //!< <a href="../target/aarch64/sqincp_r_p_r.html#sqincp_r_p_r_sx">32-bit</a>
  AMED_AARCH64_ENCODING_sqincp_r_p_r_x, //!< <a href="../target/aarch64/sqincp_r_p_r.html#sqincp_r_p_r_x">64-bit</a>
  AMED_AARCH64_ENCODING_sqincp_z_p_z_, //!< <a href="../target/aarch64/sqincp_z_p_z.html#sqincp_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_sqincw_r_rs_sx, //!< <a href="../target/aarch64/sqincw_r_rs.html#sqincw_r_rs_sx">32-bit</a>
  AMED_AARCH64_ENCODING_sqincw_r_rs_x, //!< <a href="../target/aarch64/sqincw_r_rs.html#sqincw_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_sqincw_z_zs_, //!< <a href="../target/aarch64/sqincw_z_zs.html#sqincw_z_zs_">SVE</a>
  AMED_AARCH64_ENCODING_sqneg_z_p_z_, //!< <a href="../target/aarch64/sqneg_z_p_z.html#sqneg_z_p_z_">SVE2</a>
  AMED_AARCH64_ENCODING_sqrdcmlah_z_zzz_, //!< <a href="../target/aarch64/sqrdcmlah_z_zzz.html#sqrdcmlah_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqrdcmlah_z_zzzi_h, //!< <a href="../target/aarch64/sqrdcmlah_z_zzzi.html#sqrdcmlah_z_zzzi_h">16-bit</a>
  AMED_AARCH64_ENCODING_sqrdcmlah_z_zzzi_s, //!< <a href="../target/aarch64/sqrdcmlah_z_zzzi.html#sqrdcmlah_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_sqrdmlah_z_zzz_, //!< <a href="../target/aarch64/sqrdmlah_z_zzz.html#sqrdmlah_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqrdmlah_z_zzzi_h, //!< <a href="../target/aarch64/sqrdmlah_z_zzzi.html#sqrdmlah_z_zzzi_h">16-bit</a>
  AMED_AARCH64_ENCODING_sqrdmlah_z_zzzi_s, //!< <a href="../target/aarch64/sqrdmlah_z_zzzi.html#sqrdmlah_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_sqrdmlah_z_zzzi_d, //!< <a href="../target/aarch64/sqrdmlah_z_zzzi.html#sqrdmlah_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_sqrdmlsh_z_zzz_, //!< <a href="../target/aarch64/sqrdmlsh_z_zzz.html#sqrdmlsh_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqrdmlsh_z_zzzi_h, //!< <a href="../target/aarch64/sqrdmlsh_z_zzzi.html#sqrdmlsh_z_zzzi_h">16-bit</a>
  AMED_AARCH64_ENCODING_sqrdmlsh_z_zzzi_s, //!< <a href="../target/aarch64/sqrdmlsh_z_zzzi.html#sqrdmlsh_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_sqrdmlsh_z_zzzi_d, //!< <a href="../target/aarch64/sqrdmlsh_z_zzzi.html#sqrdmlsh_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_sqrdmulh_z_zz_, //!< <a href="../target/aarch64/sqrdmulh_z_zz.html#sqrdmulh_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqrdmulh_z_zzi_h, //!< <a href="../target/aarch64/sqrdmulh_z_zzi.html#sqrdmulh_z_zzi_h">16-bit</a>
  AMED_AARCH64_ENCODING_sqrdmulh_z_zzi_s, //!< <a href="../target/aarch64/sqrdmulh_z_zzi.html#sqrdmulh_z_zzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_sqrdmulh_z_zzi_d, //!< <a href="../target/aarch64/sqrdmulh_z_zzi.html#sqrdmulh_z_zzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_sqrshl_z_p_zz_, //!< <a href="../target/aarch64/sqrshl_z_p_zz.html#sqrshl_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqrshlr_z_p_zz_, //!< <a href="../target/aarch64/sqrshlr_z_p_zz.html#sqrshlr_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqrshrnb_z_zi_, //!< <a href="../target/aarch64/sqrshrnb_z_zi.html#sqrshrnb_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_sqrshrnt_z_zi_, //!< <a href="../target/aarch64/sqrshrnt_z_zi.html#sqrshrnt_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_sqrshrunb_z_zi_, //!< <a href="../target/aarch64/sqrshrunb_z_zi.html#sqrshrunb_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_sqrshrunt_z_zi_, //!< <a href="../target/aarch64/sqrshrunt_z_zi.html#sqrshrunt_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_sqshl_z_p_zi_, //!< <a href="../target/aarch64/sqshl_z_p_zi.html#sqshl_z_p_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_sqshl_z_p_zz_, //!< <a href="../target/aarch64/sqshl_z_p_zz.html#sqshl_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqshlr_z_p_zz_, //!< <a href="../target/aarch64/sqshlr_z_p_zz.html#sqshlr_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqshlu_z_p_zi_, //!< <a href="../target/aarch64/sqshlu_z_p_zi.html#sqshlu_z_p_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_sqshrnb_z_zi_, //!< <a href="../target/aarch64/sqshrnb_z_zi.html#sqshrnb_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_sqshrnt_z_zi_, //!< <a href="../target/aarch64/sqshrnt_z_zi.html#sqshrnt_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_sqshrunb_z_zi_, //!< <a href="../target/aarch64/sqshrunb_z_zi.html#sqshrunb_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_sqshrunt_z_zi_, //!< <a href="../target/aarch64/sqshrunt_z_zi.html#sqshrunt_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_sqsub_z_p_zz_, //!< <a href="../target/aarch64/sqsub_z_p_zz.html#sqsub_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqsub_z_zi_, //!< <a href="../target/aarch64/sqsub_z_zi.html#sqsub_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_sqsub_z_zz_, //!< <a href="../target/aarch64/sqsub_z_zz.html#sqsub_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_sqsubr_z_p_zz_, //!< <a href="../target/aarch64/sqsubr_z_p_zz.html#sqsubr_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqxtnb_z_zz_, //!< <a href="../target/aarch64/sqxtnb_z_zz.html#sqxtnb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqxtnt_z_zz_, //!< <a href="../target/aarch64/sqxtnt_z_zz.html#sqxtnt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqxtunb_z_zz_, //!< <a href="../target/aarch64/sqxtunb_z_zz.html#sqxtunb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sqxtunt_z_zz_, //!< <a href="../target/aarch64/sqxtunt_z_zz.html#sqxtunt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_srhadd_z_p_zz_, //!< <a href="../target/aarch64/srhadd_z_p_zz.html#srhadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sri_z_zzi_, //!< <a href="../target/aarch64/sri_z_zzi.html#sri_z_zzi_">SVE2</a>
  AMED_AARCH64_ENCODING_srshl_z_p_zz_, //!< <a href="../target/aarch64/srshl_z_p_zz.html#srshl_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_srshlr_z_p_zz_, //!< <a href="../target/aarch64/srshlr_z_p_zz.html#srshlr_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_srshr_z_p_zi_, //!< <a href="../target/aarch64/srshr_z_p_zi.html#srshr_z_p_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_srsra_z_zi_, //!< <a href="../target/aarch64/srsra_z_zi.html#srsra_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_sshllb_z_zi_, //!< <a href="../target/aarch64/sshllb_z_zi.html#sshllb_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_sshllt_z_zi_, //!< <a href="../target/aarch64/sshllt_z_zi.html#sshllt_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_ssra_z_zi_, //!< <a href="../target/aarch64/ssra_z_zi.html#ssra_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_ssublb_z_zz_, //!< <a href="../target/aarch64/ssublb_z_zz.html#ssublb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_ssublbt_z_zz_, //!< <a href="../target/aarch64/ssublbt_z_zz.html#ssublbt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_ssublt_z_zz_, //!< <a href="../target/aarch64/ssublt_z_zz.html#ssublt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_ssubltb_z_zz_, //!< <a href="../target/aarch64/ssubltb_z_zz.html#ssubltb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_ssubwb_z_zz_, //!< <a href="../target/aarch64/ssubwb_z_zz.html#ssubwb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_ssubwt_z_zz_, //!< <a href="../target/aarch64/ssubwt_z_zz.html#ssubwt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_st1b_z_p_ai_s, //!< <a href="../target/aarch64/st1b_z_p_ai.html#st1b_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_st1b_z_p_ai_d, //!< <a href="../target/aarch64/st1b_z_p_ai.html#st1b_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_st1b_z_p_bi_, //!< <a href="../target/aarch64/st1b_z_p_bi.html#st1b_z_p_bi_">SVE</a>
  AMED_AARCH64_ENCODING_st1b_z_p_br_, //!< <a href="../target/aarch64/st1b_z_p_br.html#st1b_z_p_br_">SVE</a>
  AMED_AARCH64_ENCODING_st1b_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/st1b_z_p_bz.html#st1b_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_st1b_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/st1b_z_p_bz.html#st1b_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_st1b_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/st1b_z_p_bz.html#st1b_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_st1d_z_p_ai_d, //!< <a href="../target/aarch64/st1d_z_p_ai.html#st1d_z_p_ai_d">SVE</a>
  AMED_AARCH64_ENCODING_st1d_z_p_bi_, //!< <a href="../target/aarch64/st1d_z_p_bi.html#st1d_z_p_bi_">SVE</a>
  AMED_AARCH64_ENCODING_st1d_z_p_br_, //!< <a href="../target/aarch64/st1d_z_p_br.html#st1d_z_p_br_">SVE</a>
  AMED_AARCH64_ENCODING_st1d_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/st1d_z_p_bz.html#st1d_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_st1d_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/st1d_z_p_bz.html#st1d_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_st1d_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/st1d_z_p_bz.html#st1d_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_st1d_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/st1d_z_p_bz.html#st1d_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_st1h_z_p_ai_s, //!< <a href="../target/aarch64/st1h_z_p_ai.html#st1h_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_st1h_z_p_ai_d, //!< <a href="../target/aarch64/st1h_z_p_ai.html#st1h_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_st1h_z_p_bi_, //!< <a href="../target/aarch64/st1h_z_p_bi.html#st1h_z_p_bi_">SVE</a>
  AMED_AARCH64_ENCODING_st1h_z_p_br_, //!< <a href="../target/aarch64/st1h_z_p_br.html#st1h_z_p_br_">SVE</a>
  AMED_AARCH64_ENCODING_st1h_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/st1h_z_p_bz.html#st1h_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_ENCODING_st1h_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/st1h_z_p_bz.html#st1h_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_st1h_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/st1h_z_p_bz.html#st1h_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_st1h_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/st1h_z_p_bz.html#st1h_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_st1h_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/st1h_z_p_bz.html#st1h_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_st1h_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/st1h_z_p_bz.html#st1h_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_st1w_z_p_ai_s, //!< <a href="../target/aarch64/st1w_z_p_ai.html#st1w_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_ENCODING_st1w_z_p_ai_d, //!< <a href="../target/aarch64/st1w_z_p_ai.html#st1w_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_ENCODING_st1w_z_p_bi_, //!< <a href="../target/aarch64/st1w_z_p_bi.html#st1w_z_p_bi_">SVE</a>
  AMED_AARCH64_ENCODING_st1w_z_p_br_, //!< <a href="../target/aarch64/st1w_z_p_br.html#st1w_z_p_br_">SVE</a>
  AMED_AARCH64_ENCODING_st1w_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/st1w_z_p_bz.html#st1w_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_ENCODING_st1w_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/st1w_z_p_bz.html#st1w_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_ENCODING_st1w_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/st1w_z_p_bz.html#st1w_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_ENCODING_st1w_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/st1w_z_p_bz.html#st1w_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_st1w_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/st1w_z_p_bz.html#st1w_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_ENCODING_st1w_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/st1w_z_p_bz.html#st1w_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_st2b_z_p_bi_contiguous, //!< <a href="../target/aarch64/st2b_z_p_bi.html#st2b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st2b_z_p_br_contiguous, //!< <a href="../target/aarch64/st2b_z_p_br.html#st2b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st2d_z_p_bi_contiguous, //!< <a href="../target/aarch64/st2d_z_p_bi.html#st2d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st2d_z_p_br_contiguous, //!< <a href="../target/aarch64/st2d_z_p_br.html#st2d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st2h_z_p_bi_contiguous, //!< <a href="../target/aarch64/st2h_z_p_bi.html#st2h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st2h_z_p_br_contiguous, //!< <a href="../target/aarch64/st2h_z_p_br.html#st2h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st2w_z_p_bi_contiguous, //!< <a href="../target/aarch64/st2w_z_p_bi.html#st2w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st2w_z_p_br_contiguous, //!< <a href="../target/aarch64/st2w_z_p_br.html#st2w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st3b_z_p_bi_contiguous, //!< <a href="../target/aarch64/st3b_z_p_bi.html#st3b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st3b_z_p_br_contiguous, //!< <a href="../target/aarch64/st3b_z_p_br.html#st3b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st3d_z_p_bi_contiguous, //!< <a href="../target/aarch64/st3d_z_p_bi.html#st3d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st3d_z_p_br_contiguous, //!< <a href="../target/aarch64/st3d_z_p_br.html#st3d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st3h_z_p_bi_contiguous, //!< <a href="../target/aarch64/st3h_z_p_bi.html#st3h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st3h_z_p_br_contiguous, //!< <a href="../target/aarch64/st3h_z_p_br.html#st3h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st3w_z_p_bi_contiguous, //!< <a href="../target/aarch64/st3w_z_p_bi.html#st3w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st3w_z_p_br_contiguous, //!< <a href="../target/aarch64/st3w_z_p_br.html#st3w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st4b_z_p_bi_contiguous, //!< <a href="../target/aarch64/st4b_z_p_bi.html#st4b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st4b_z_p_br_contiguous, //!< <a href="../target/aarch64/st4b_z_p_br.html#st4b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st4d_z_p_bi_contiguous, //!< <a href="../target/aarch64/st4d_z_p_bi.html#st4d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st4d_z_p_br_contiguous, //!< <a href="../target/aarch64/st4d_z_p_br.html#st4d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st4h_z_p_bi_contiguous, //!< <a href="../target/aarch64/st4h_z_p_bi.html#st4h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st4h_z_p_br_contiguous, //!< <a href="../target/aarch64/st4h_z_p_br.html#st4h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st4w_z_p_bi_contiguous, //!< <a href="../target/aarch64/st4w_z_p_bi.html#st4w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_st4w_z_p_br_contiguous, //!< <a href="../target/aarch64/st4w_z_p_br.html#st4w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_stnt1b_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/stnt1b_z_p_ar.html#stnt1b_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_stnt1b_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/stnt1b_z_p_ar.html#stnt1b_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_stnt1b_z_p_bi_contiguous, //!< <a href="../target/aarch64/stnt1b_z_p_bi.html#stnt1b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_stnt1b_z_p_br_contiguous, //!< <a href="../target/aarch64/stnt1b_z_p_br.html#stnt1b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_stnt1d_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/stnt1d_z_p_ar.html#stnt1d_z_p_ar_d_64_unscaled">SVE2</a>
  AMED_AARCH64_ENCODING_stnt1d_z_p_bi_contiguous, //!< <a href="../target/aarch64/stnt1d_z_p_bi.html#stnt1d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_stnt1d_z_p_br_contiguous, //!< <a href="../target/aarch64/stnt1d_z_p_br.html#stnt1d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_stnt1h_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/stnt1h_z_p_ar.html#stnt1h_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_stnt1h_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/stnt1h_z_p_ar.html#stnt1h_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_stnt1h_z_p_bi_contiguous, //!< <a href="../target/aarch64/stnt1h_z_p_bi.html#stnt1h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_stnt1h_z_p_br_contiguous, //!< <a href="../target/aarch64/stnt1h_z_p_br.html#stnt1h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_stnt1w_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/stnt1w_z_p_ar.html#stnt1w_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_stnt1w_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/stnt1w_z_p_ar.html#stnt1w_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_ENCODING_stnt1w_z_p_bi_contiguous, //!< <a href="../target/aarch64/stnt1w_z_p_bi.html#stnt1w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_stnt1w_z_p_br_contiguous, //!< <a href="../target/aarch64/stnt1w_z_p_br.html#stnt1w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_ENCODING_str_p_bi_, //!< <a href="../target/aarch64/str_p_bi.html#str_p_bi_">SVE</a>
  AMED_AARCH64_ENCODING_str_z_bi_, //!< <a href="../target/aarch64/str_z_bi.html#str_z_bi_">SVE</a>
  AMED_AARCH64_ENCODING_sub_z_p_zz_, //!< <a href="../target/aarch64/sub_z_p_zz.html#sub_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_sub_z_zi_, //!< <a href="../target/aarch64/sub_z_zi.html#sub_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_sub_z_zz_, //!< <a href="../target/aarch64/sub_z_zz.html#sub_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_subhnb_z_zz_, //!< <a href="../target/aarch64/subhnb_z_zz.html#subhnb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_subhnt_z_zz_, //!< <a href="../target/aarch64/subhnt_z_zz.html#subhnt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_subr_z_p_zz_, //!< <a href="../target/aarch64/subr_z_p_zz.html#subr_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_subr_z_zi_, //!< <a href="../target/aarch64/subr_z_zi.html#subr_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_sudot_z_zzzi_s, //!< <a href="../target/aarch64/sudot_z_zzzi.html#sudot_z_zzzi_s">SVE</a>
  AMED_AARCH64_ENCODING_sunpkhi_z_z_, //!< <a href="../target/aarch64/sunpkhi_z_z.html#sunpkhi_z_z_">High half</a>
  AMED_AARCH64_ENCODING_sunpklo_z_z_, //!< <a href="../target/aarch64/sunpkhi_z_z.html#sunpklo_z_z_">Low half</a>
  AMED_AARCH64_ENCODING_suqadd_z_p_zz_, //!< <a href="../target/aarch64/suqadd_z_p_zz.html#suqadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_sxtb_z_p_z_, //!< <a href="../target/aarch64/sxtb_z_p_z.html#sxtb_z_p_z_">Byte</a>
  AMED_AARCH64_ENCODING_sxth_z_p_z_, //!< <a href="../target/aarch64/sxtb_z_p_z.html#sxth_z_p_z_">Halfword</a>
  AMED_AARCH64_ENCODING_sxtw_z_p_z_, //!< <a href="../target/aarch64/sxtb_z_p_z.html#sxtw_z_p_z_">Word</a>
  AMED_AARCH64_ENCODING_tbl_z_zz_1, //!< <a href="../target/aarch64/tbl_z_zz.html#tbl_z_zz_1">SVE</a>
  AMED_AARCH64_ENCODING_tbl_z_zz_2, //!< <a href="../target/aarch64/tbl_z_zz.html#tbl_z_zz_2">SVE2</a>
  AMED_AARCH64_ENCODING_tbx_z_zz_, //!< <a href="../target/aarch64/tbx_z_zz.html#tbx_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_trn1_p_pp_, //!< <a href="../target/aarch64/trn1_p_pp.html#trn1_p_pp_">Even</a>
  AMED_AARCH64_ENCODING_trn2_p_pp_, //!< <a href="../target/aarch64/trn1_p_pp.html#trn2_p_pp_">Odd</a>
  AMED_AARCH64_ENCODING_trn1_z_zz_, //!< <a href="../target/aarch64/trn1_z_zz.html#trn1_z_zz_">Even</a>
  AMED_AARCH64_ENCODING_trn1_z_zz_q, //!< <a href="../target/aarch64/trn1_z_zz.html#trn1_z_zz_q">Even (quadwords)</a>
  AMED_AARCH64_ENCODING_trn2_z_zz_, //!< <a href="../target/aarch64/trn1_z_zz.html#trn2_z_zz_">Odd</a>
  AMED_AARCH64_ENCODING_trn2_z_zz_q, //!< <a href="../target/aarch64/trn1_z_zz.html#trn2_z_zz_q">Odd (quadwords)</a>
  AMED_AARCH64_ENCODING_uaba_z_zzz_, //!< <a href="../target/aarch64/uaba_z_zzz.html#uaba_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_uabalb_z_zzz_, //!< <a href="../target/aarch64/uabalb_z_zzz.html#uabalb_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_uabalt_z_zzz_, //!< <a href="../target/aarch64/uabalt_z_zzz.html#uabalt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_uabd_z_p_zz_, //!< <a href="../target/aarch64/uabd_z_p_zz.html#uabd_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_uabdlb_z_zz_, //!< <a href="../target/aarch64/uabdlb_z_zz.html#uabdlb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uabdlt_z_zz_, //!< <a href="../target/aarch64/uabdlt_z_zz.html#uabdlt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uadalp_z_p_z_, //!< <a href="../target/aarch64/uadalp_z_p_z.html#uadalp_z_p_z_">SVE2</a>
  AMED_AARCH64_ENCODING_uaddlb_z_zz_, //!< <a href="../target/aarch64/uaddlb_z_zz.html#uaddlb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uaddlt_z_zz_, //!< <a href="../target/aarch64/uaddlt_z_zz.html#uaddlt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uaddv_r_p_z_, //!< <a href="../target/aarch64/uaddv_r_p_z.html#uaddv_r_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_uaddwb_z_zz_, //!< <a href="../target/aarch64/uaddwb_z_zz.html#uaddwb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uaddwt_z_zz_, //!< <a href="../target/aarch64/uaddwt_z_zz.html#uaddwt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_ucvtf_z_p_z_h2fp16, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_h2fp16">16-bit to half-precision</a>
  AMED_AARCH64_ENCODING_ucvtf_z_p_z_w2fp16, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_w2fp16">32-bit to half-precision</a>
  AMED_AARCH64_ENCODING_ucvtf_z_p_z_w2s, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_w2s">32-bit to single-precision</a>
  AMED_AARCH64_ENCODING_ucvtf_z_p_z_w2d, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_w2d">32-bit to double-precision</a>
  AMED_AARCH64_ENCODING_ucvtf_z_p_z_x2fp16, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_x2fp16">64-bit to half-precision</a>
  AMED_AARCH64_ENCODING_ucvtf_z_p_z_x2s, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_x2s">64-bit to single-precision</a>
  AMED_AARCH64_ENCODING_ucvtf_z_p_z_x2d, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_x2d">64-bit to double-precision</a>
  AMED_AARCH64_ENCODING_udiv_z_p_zz_, //!< <a href="../target/aarch64/udiv_z_p_zz.html#udiv_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_udivr_z_p_zz_, //!< <a href="../target/aarch64/udivr_z_p_zz.html#udivr_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_udot_z_zzz_, //!< <a href="../target/aarch64/udot_z_zzz.html#udot_z_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_udot_z_zzzi_s, //!< <a href="../target/aarch64/udot_z_zzzi.html#udot_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_udot_z_zzzi_d, //!< <a href="../target/aarch64/udot_z_zzzi.html#udot_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_uhadd_z_p_zz_, //!< <a href="../target/aarch64/uhadd_z_p_zz.html#uhadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uhsub_z_p_zz_, //!< <a href="../target/aarch64/uhsub_z_p_zz.html#uhsub_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uhsubr_z_p_zz_, //!< <a href="../target/aarch64/uhsubr_z_p_zz.html#uhsubr_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_umax_z_p_zz_, //!< <a href="../target/aarch64/umax_z_p_zz.html#umax_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_umax_z_zi_, //!< <a href="../target/aarch64/umax_z_zi.html#umax_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_umaxp_z_p_zz_, //!< <a href="../target/aarch64/umaxp_z_p_zz.html#umaxp_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_umaxv_r_p_z_, //!< <a href="../target/aarch64/umaxv_r_p_z.html#umaxv_r_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_umin_z_p_zz_, //!< <a href="../target/aarch64/umin_z_p_zz.html#umin_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_umin_z_zi_, //!< <a href="../target/aarch64/umin_z_zi.html#umin_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_uminp_z_p_zz_, //!< <a href="../target/aarch64/uminp_z_p_zz.html#uminp_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uminv_r_p_z_, //!< <a href="../target/aarch64/uminv_r_p_z.html#uminv_r_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_umlalb_z_zzz_, //!< <a href="../target/aarch64/umlalb_z_zzz.html#umlalb_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_umlalb_z_zzzi_s, //!< <a href="../target/aarch64/umlalb_z_zzzi.html#umlalb_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_umlalb_z_zzzi_d, //!< <a href="../target/aarch64/umlalb_z_zzzi.html#umlalb_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_umlalt_z_zzz_, //!< <a href="../target/aarch64/umlalt_z_zzz.html#umlalt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_umlalt_z_zzzi_s, //!< <a href="../target/aarch64/umlalt_z_zzzi.html#umlalt_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_umlalt_z_zzzi_d, //!< <a href="../target/aarch64/umlalt_z_zzzi.html#umlalt_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_umlslb_z_zzz_, //!< <a href="../target/aarch64/umlslb_z_zzz.html#umlslb_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_umlslb_z_zzzi_s, //!< <a href="../target/aarch64/umlslb_z_zzzi.html#umlslb_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_umlslb_z_zzzi_d, //!< <a href="../target/aarch64/umlslb_z_zzzi.html#umlslb_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_umlslt_z_zzz_, //!< <a href="../target/aarch64/umlslt_z_zzz.html#umlslt_z_zzz_">SVE2</a>
  AMED_AARCH64_ENCODING_umlslt_z_zzzi_s, //!< <a href="../target/aarch64/umlslt_z_zzzi.html#umlslt_z_zzzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_umlslt_z_zzzi_d, //!< <a href="../target/aarch64/umlslt_z_zzzi.html#umlslt_z_zzzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_ummla_z_zzz_, //!< <a href="../target/aarch64/ummla_z_zzz.html#ummla_z_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_umulh_z_p_zz_, //!< <a href="../target/aarch64/umulh_z_p_zz.html#umulh_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_umulh_z_zz_, //!< <a href="../target/aarch64/umulh_z_zz.html#umulh_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_umullb_z_zz_, //!< <a href="../target/aarch64/umullb_z_zz.html#umullb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_umullb_z_zzi_s, //!< <a href="../target/aarch64/umullb_z_zzi.html#umullb_z_zzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_umullb_z_zzi_d, //!< <a href="../target/aarch64/umullb_z_zzi.html#umullb_z_zzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_umullt_z_zz_, //!< <a href="../target/aarch64/umullt_z_zz.html#umullt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_umullt_z_zzi_s, //!< <a href="../target/aarch64/umullt_z_zzi.html#umullt_z_zzi_s">32-bit</a>
  AMED_AARCH64_ENCODING_umullt_z_zzi_d, //!< <a href="../target/aarch64/umullt_z_zzi.html#umullt_z_zzi_d">64-bit</a>
  AMED_AARCH64_ENCODING_uqadd_z_p_zz_, //!< <a href="../target/aarch64/uqadd_z_p_zz.html#uqadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uqadd_z_zi_, //!< <a href="../target/aarch64/uqadd_z_zi.html#uqadd_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_uqadd_z_zz_, //!< <a href="../target/aarch64/uqadd_z_zz.html#uqadd_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_uqdecb_r_rs_uw, //!< <a href="../target/aarch64/uqdecb_r_rs.html#uqdecb_r_rs_uw">32-bit</a>
  AMED_AARCH64_ENCODING_uqdecb_r_rs_x, //!< <a href="../target/aarch64/uqdecb_r_rs.html#uqdecb_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_uqdecd_r_rs_uw, //!< <a href="../target/aarch64/uqdecd_r_rs.html#uqdecd_r_rs_uw">32-bit</a>
  AMED_AARCH64_ENCODING_uqdecd_r_rs_x, //!< <a href="../target/aarch64/uqdecd_r_rs.html#uqdecd_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_uqdecd_z_zs_, //!< <a href="../target/aarch64/uqdecd_z_zs.html#uqdecd_z_zs_">SVE</a>
  AMED_AARCH64_ENCODING_uqdech_r_rs_uw, //!< <a href="../target/aarch64/uqdech_r_rs.html#uqdech_r_rs_uw">32-bit</a>
  AMED_AARCH64_ENCODING_uqdech_r_rs_x, //!< <a href="../target/aarch64/uqdech_r_rs.html#uqdech_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_uqdech_z_zs_, //!< <a href="../target/aarch64/uqdech_z_zs.html#uqdech_z_zs_">SVE</a>
  AMED_AARCH64_ENCODING_uqdecp_r_p_r_uw, //!< <a href="../target/aarch64/uqdecp_r_p_r.html#uqdecp_r_p_r_uw">32-bit</a>
  AMED_AARCH64_ENCODING_uqdecp_r_p_r_x, //!< <a href="../target/aarch64/uqdecp_r_p_r.html#uqdecp_r_p_r_x">64-bit</a>
  AMED_AARCH64_ENCODING_uqdecp_z_p_z_, //!< <a href="../target/aarch64/uqdecp_z_p_z.html#uqdecp_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_uqdecw_r_rs_uw, //!< <a href="../target/aarch64/uqdecw_r_rs.html#uqdecw_r_rs_uw">32-bit</a>
  AMED_AARCH64_ENCODING_uqdecw_r_rs_x, //!< <a href="../target/aarch64/uqdecw_r_rs.html#uqdecw_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_uqdecw_z_zs_, //!< <a href="../target/aarch64/uqdecw_z_zs.html#uqdecw_z_zs_">SVE</a>
  AMED_AARCH64_ENCODING_uqincb_r_rs_uw, //!< <a href="../target/aarch64/uqincb_r_rs.html#uqincb_r_rs_uw">32-bit</a>
  AMED_AARCH64_ENCODING_uqincb_r_rs_x, //!< <a href="../target/aarch64/uqincb_r_rs.html#uqincb_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_uqincd_r_rs_uw, //!< <a href="../target/aarch64/uqincd_r_rs.html#uqincd_r_rs_uw">32-bit</a>
  AMED_AARCH64_ENCODING_uqincd_r_rs_x, //!< <a href="../target/aarch64/uqincd_r_rs.html#uqincd_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_uqincd_z_zs_, //!< <a href="../target/aarch64/uqincd_z_zs.html#uqincd_z_zs_">SVE</a>
  AMED_AARCH64_ENCODING_uqinch_r_rs_uw, //!< <a href="../target/aarch64/uqinch_r_rs.html#uqinch_r_rs_uw">32-bit</a>
  AMED_AARCH64_ENCODING_uqinch_r_rs_x, //!< <a href="../target/aarch64/uqinch_r_rs.html#uqinch_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_uqinch_z_zs_, //!< <a href="../target/aarch64/uqinch_z_zs.html#uqinch_z_zs_">SVE</a>
  AMED_AARCH64_ENCODING_uqincp_r_p_r_uw, //!< <a href="../target/aarch64/uqincp_r_p_r.html#uqincp_r_p_r_uw">32-bit</a>
  AMED_AARCH64_ENCODING_uqincp_r_p_r_x, //!< <a href="../target/aarch64/uqincp_r_p_r.html#uqincp_r_p_r_x">64-bit</a>
  AMED_AARCH64_ENCODING_uqincp_z_p_z_, //!< <a href="../target/aarch64/uqincp_z_p_z.html#uqincp_z_p_z_">SVE</a>
  AMED_AARCH64_ENCODING_uqincw_r_rs_uw, //!< <a href="../target/aarch64/uqincw_r_rs.html#uqincw_r_rs_uw">32-bit</a>
  AMED_AARCH64_ENCODING_uqincw_r_rs_x, //!< <a href="../target/aarch64/uqincw_r_rs.html#uqincw_r_rs_x">64-bit</a>
  AMED_AARCH64_ENCODING_uqincw_z_zs_, //!< <a href="../target/aarch64/uqincw_z_zs.html#uqincw_z_zs_">SVE</a>
  AMED_AARCH64_ENCODING_uqrshl_z_p_zz_, //!< <a href="../target/aarch64/uqrshl_z_p_zz.html#uqrshl_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uqrshlr_z_p_zz_, //!< <a href="../target/aarch64/uqrshlr_z_p_zz.html#uqrshlr_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uqrshrnb_z_zi_, //!< <a href="../target/aarch64/uqrshrnb_z_zi.html#uqrshrnb_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_uqrshrnt_z_zi_, //!< <a href="../target/aarch64/uqrshrnt_z_zi.html#uqrshrnt_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_uqshl_z_p_zi_, //!< <a href="../target/aarch64/uqshl_z_p_zi.html#uqshl_z_p_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_uqshl_z_p_zz_, //!< <a href="../target/aarch64/uqshl_z_p_zz.html#uqshl_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uqshlr_z_p_zz_, //!< <a href="../target/aarch64/uqshlr_z_p_zz.html#uqshlr_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uqshrnb_z_zi_, //!< <a href="../target/aarch64/uqshrnb_z_zi.html#uqshrnb_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_uqshrnt_z_zi_, //!< <a href="../target/aarch64/uqshrnt_z_zi.html#uqshrnt_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_uqsub_z_p_zz_, //!< <a href="../target/aarch64/uqsub_z_p_zz.html#uqsub_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uqsub_z_zi_, //!< <a href="../target/aarch64/uqsub_z_zi.html#uqsub_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_uqsub_z_zz_, //!< <a href="../target/aarch64/uqsub_z_zz.html#uqsub_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_uqsubr_z_p_zz_, //!< <a href="../target/aarch64/uqsubr_z_p_zz.html#uqsubr_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uqxtnb_z_zz_, //!< <a href="../target/aarch64/uqxtnb_z_zz.html#uqxtnb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uqxtnt_z_zz_, //!< <a href="../target/aarch64/uqxtnt_z_zz.html#uqxtnt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_urecpe_z_p_z_, //!< <a href="../target/aarch64/urecpe_z_p_z.html#urecpe_z_p_z_">SVE2</a>
  AMED_AARCH64_ENCODING_urhadd_z_p_zz_, //!< <a href="../target/aarch64/urhadd_z_p_zz.html#urhadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_urshl_z_p_zz_, //!< <a href="../target/aarch64/urshl_z_p_zz.html#urshl_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_urshlr_z_p_zz_, //!< <a href="../target/aarch64/urshlr_z_p_zz.html#urshlr_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_urshr_z_p_zi_, //!< <a href="../target/aarch64/urshr_z_p_zi.html#urshr_z_p_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_ursqrte_z_p_z_, //!< <a href="../target/aarch64/ursqrte_z_p_z.html#ursqrte_z_p_z_">SVE2</a>
  AMED_AARCH64_ENCODING_ursra_z_zi_, //!< <a href="../target/aarch64/ursra_z_zi.html#ursra_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_usdot_z_zzz_s, //!< <a href="../target/aarch64/usdot_z_zzz.html#usdot_z_zzz_s">SVE</a>
  AMED_AARCH64_ENCODING_usdot_z_zzzi_s, //!< <a href="../target/aarch64/usdot_z_zzzi.html#usdot_z_zzzi_s">SVE</a>
  AMED_AARCH64_ENCODING_ushllb_z_zi_, //!< <a href="../target/aarch64/ushllb_z_zi.html#ushllb_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_ushllt_z_zi_, //!< <a href="../target/aarch64/ushllt_z_zi.html#ushllt_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_usmmla_z_zzz_, //!< <a href="../target/aarch64/usmmla_z_zzz.html#usmmla_z_zzz_">SVE</a>
  AMED_AARCH64_ENCODING_usqadd_z_p_zz_, //!< <a href="../target/aarch64/usqadd_z_p_zz.html#usqadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_usra_z_zi_, //!< <a href="../target/aarch64/usra_z_zi.html#usra_z_zi_">SVE2</a>
  AMED_AARCH64_ENCODING_usublb_z_zz_, //!< <a href="../target/aarch64/usublb_z_zz.html#usublb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_usublt_z_zz_, //!< <a href="../target/aarch64/usublt_z_zz.html#usublt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_usubwb_z_zz_, //!< <a href="../target/aarch64/usubwb_z_zz.html#usubwb_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_usubwt_z_zz_, //!< <a href="../target/aarch64/usubwt_z_zz.html#usubwt_z_zz_">SVE2</a>
  AMED_AARCH64_ENCODING_uunpkhi_z_z_, //!< <a href="../target/aarch64/uunpkhi_z_z.html#uunpkhi_z_z_">High half</a>
  AMED_AARCH64_ENCODING_uunpklo_z_z_, //!< <a href="../target/aarch64/uunpkhi_z_z.html#uunpklo_z_z_">Low half</a>
  AMED_AARCH64_ENCODING_uxtb_z_p_z_, //!< <a href="../target/aarch64/uxtb_z_p_z.html#uxtb_z_p_z_">Byte</a>
  AMED_AARCH64_ENCODING_uxth_z_p_z_, //!< <a href="../target/aarch64/uxtb_z_p_z.html#uxth_z_p_z_">Halfword</a>
  AMED_AARCH64_ENCODING_uxtw_z_p_z_, //!< <a href="../target/aarch64/uxtb_z_p_z.html#uxtw_z_p_z_">Word</a>
  AMED_AARCH64_ENCODING_uzp1_p_pp_, //!< <a href="../target/aarch64/uzp1_p_pp.html#uzp1_p_pp_">Even</a>
  AMED_AARCH64_ENCODING_uzp2_p_pp_, //!< <a href="../target/aarch64/uzp1_p_pp.html#uzp2_p_pp_">Odd</a>
  AMED_AARCH64_ENCODING_uzp1_z_zz_, //!< <a href="../target/aarch64/uzp1_z_zz.html#uzp1_z_zz_">Even</a>
  AMED_AARCH64_ENCODING_uzp1_z_zz_q, //!< <a href="../target/aarch64/uzp1_z_zz.html#uzp1_z_zz_q">Even (quadwords)</a>
  AMED_AARCH64_ENCODING_uzp2_z_zz_, //!< <a href="../target/aarch64/uzp1_z_zz.html#uzp2_z_zz_">Odd</a>
  AMED_AARCH64_ENCODING_uzp2_z_zz_q, //!< <a href="../target/aarch64/uzp1_z_zz.html#uzp2_z_zz_q">Odd (quadwords)</a>
  AMED_AARCH64_ENCODING_whilege_p_p_rr_, //!< <a href="../target/aarch64/whilege_p_p_rr.html#whilege_p_p_rr_">SVE2</a>
  AMED_AARCH64_ENCODING_whilegt_p_p_rr_, //!< <a href="../target/aarch64/whilegt_p_p_rr.html#whilegt_p_p_rr_">SVE2</a>
  AMED_AARCH64_ENCODING_whilehi_p_p_rr_, //!< <a href="../target/aarch64/whilehi_p_p_rr.html#whilehi_p_p_rr_">SVE2</a>
  AMED_AARCH64_ENCODING_whilehs_p_p_rr_, //!< <a href="../target/aarch64/whilehs_p_p_rr.html#whilehs_p_p_rr_">SVE2</a>
  AMED_AARCH64_ENCODING_whilele_p_p_rr_, //!< <a href="../target/aarch64/whilele_p_p_rr.html#whilele_p_p_rr_">SVE</a>
  AMED_AARCH64_ENCODING_whilelo_p_p_rr_, //!< <a href="../target/aarch64/whilelo_p_p_rr.html#whilelo_p_p_rr_">SVE</a>
  AMED_AARCH64_ENCODING_whilels_p_p_rr_, //!< <a href="../target/aarch64/whilels_p_p_rr.html#whilels_p_p_rr_">SVE</a>
  AMED_AARCH64_ENCODING_whilelt_p_p_rr_, //!< <a href="../target/aarch64/whilelt_p_p_rr.html#whilelt_p_p_rr_">SVE</a>
  AMED_AARCH64_ENCODING_whilerw_p_rr_, //!< <a href="../target/aarch64/whilerw_p_rr.html#whilerw_p_rr_">SVE2</a>
  AMED_AARCH64_ENCODING_whilewr_p_rr_, //!< <a href="../target/aarch64/whilewr_p_rr.html#whilewr_p_rr_">SVE2</a>
  AMED_AARCH64_ENCODING_wrffr_f_p_, //!< <a href="../target/aarch64/wrffr_f_p.html#wrffr_f_p_">SVE</a>
  AMED_AARCH64_ENCODING_xar_z_zzi_, //!< <a href="../target/aarch64/xar_z_zzi.html#xar_z_zzi_">SVE2</a>
  AMED_AARCH64_ENCODING_zip2_p_pp_, //!< <a href="../target/aarch64/zip1_p_pp.html#zip2_p_pp_">High halves</a>
  AMED_AARCH64_ENCODING_zip1_p_pp_, //!< <a href="../target/aarch64/zip1_p_pp.html#zip1_p_pp_">Low halves</a>
  AMED_AARCH64_ENCODING_zip2_z_zz_, //!< <a href="../target/aarch64/zip1_z_zz.html#zip2_z_zz_">High halves</a>
  AMED_AARCH64_ENCODING_zip2_z_zz_q, //!< <a href="../target/aarch64/zip1_z_zz.html#zip2_z_zz_q">High halves (quadwords)</a>
  AMED_AARCH64_ENCODING_zip1_z_zz_, //!< <a href="../target/aarch64/zip1_z_zz.html#zip1_z_zz_">Low halves</a>
  AMED_AARCH64_ENCODING_zip1_z_zz_q, //!< <a href="../target/aarch64/zip1_z_zz.html#zip1_z_zz_q">Low halves (quadwords)</a>
  AMED_AARCH64_ENCODING_BIC_and_z_zi_, //!< <a href="../target/aarch64/BIC_and_z_zi.html#BIC_and_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_CMPLE_cmpge_p_p_zz_, //!< <a href="../target/aarch64/CMPLE_cmpeq_p_p_zz.html#CMPLE_cmpge_p_p_zz_">Greater than or equal</a>
  AMED_AARCH64_ENCODING_CMPLO_cmphi_p_p_zz_, //!< <a href="../target/aarch64/CMPLO_cmpeq_p_p_zz.html#CMPLO_cmphi_p_p_zz_">Higher</a>
  AMED_AARCH64_ENCODING_CMPLS_cmphs_p_p_zz_, //!< <a href="../target/aarch64/CMPLS_cmpeq_p_p_zz.html#CMPLS_cmphs_p_p_zz_">Higher or same</a>
  AMED_AARCH64_ENCODING_CMPLT_cmpgt_p_p_zz_, //!< <a href="../target/aarch64/CMPLT_cmpeq_p_p_zz.html#CMPLT_cmpgt_p_p_zz_">Greater than</a>
  AMED_AARCH64_ENCODING_EON_eor_z_zi_, //!< <a href="../target/aarch64/EON_eor_z_zi.html#EON_eor_z_zi_">SVE</a>
  AMED_AARCH64_ENCODING_FACLE_facge_p_p_zz_, //!< <a href="../target/aarch64/FACLE_facge_p_p_zz.html#FACLE_facge_p_p_zz_">Greater than or equal</a>
  AMED_AARCH64_ENCODING_FACLT_facgt_p_p_zz_, //!< <a href="../target/aarch64/FACLT_facge_p_p_zz.html#FACLT_facgt_p_p_zz_">Greater than</a>
  AMED_AARCH64_ENCODING_FCMLE_fcmge_p_p_zz_, //!< <a href="../target/aarch64/FCMLE_fcmeq_p_p_zz.html#FCMLE_fcmge_p_p_zz_">Greater than or equal</a>
  AMED_AARCH64_ENCODING_FCMLT_fcmgt_p_p_zz_, //!< <a href="../target/aarch64/FCMLT_fcmeq_p_p_zz.html#FCMLT_fcmgt_p_p_zz_">Greater than</a>
  AMED_AARCH64_ENCODING_FMOV_cpy_z_p_i_, //!< <a href="../target/aarch64/FMOV_cpy_z_p_i.html#FMOV_cpy_z_p_i_">SVE</a>
  AMED_AARCH64_ENCODING_FMOV_dup_z_i_, //!< <a href="../target/aarch64/FMOV_dup_z_i.html#FMOV_dup_z_i_">SVE</a>
  AMED_AARCH64_ENCODING_FMOV_fcpy_z_p_i_, //!< <a href="../target/aarch64/FMOV_fcpy_z_p_i.html#FMOV_fcpy_z_p_i_">SVE</a>
  AMED_AARCH64_ENCODING_FMOV_fdup_z_i_, //!< <a href="../target/aarch64/FMOV_fdup_z_i.html#FMOV_fdup_z_i_">SVE</a>
  AMED_AARCH64_ENCODING_MOV_and_p_p_pp_z, //!< <a href="../target/aarch64/MOV_and_p_p_pp.html#MOV_and_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_MOV_cpy_z_o_i_, //!< <a href="../target/aarch64/MOV_cpy_z_o_i.html#MOV_cpy_z_o_i_">SVE</a>
  AMED_AARCH64_ENCODING_MOV_cpy_z_p_i_, //!< <a href="../target/aarch64/MOV_cpy_z_p_i.html#MOV_cpy_z_p_i_">SVE</a>
  AMED_AARCH64_ENCODING_MOV_cpy_z_p_r_, //!< <a href="../target/aarch64/MOV_cpy_z_p_r.html#MOV_cpy_z_p_r_">SVE</a>
  AMED_AARCH64_ENCODING_MOV_cpy_z_p_v_, //!< <a href="../target/aarch64/MOV_cpy_z_p_v.html#MOV_cpy_z_p_v_">SVE</a>
  AMED_AARCH64_ENCODING_MOV_dup_z_i_, //!< <a href="../target/aarch64/MOV_dup_z_i.html#MOV_dup_z_i_">SVE</a>
  AMED_AARCH64_ENCODING_MOV_dup_z_r_, //!< <a href="../target/aarch64/MOV_dup_z_r.html#MOV_dup_z_r_">SVE</a>
  AMED_AARCH64_ENCODING_MOV_dup_z_zi_, //!< <a href="../target/aarch64/MOV_dup_z_zi.html#MOV_dup_z_zi_">MOV_dup_z_zi_</a>
  AMED_AARCH64_ENCODING_MOV_dupm_z_i_, //!< <a href="../target/aarch64/MOV_dupm_z_i.html#MOV_dupm_z_i_">SVE</a>
  AMED_AARCH64_ENCODING_MOV_orr_p_p_pp_z, //!< <a href="../target/aarch64/MOV_orr_p_p_pp.html#MOV_orr_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_MOV_orr_z_zz_, //!< <a href="../target/aarch64/MOV_orr_z_zz.html#MOV_orr_z_zz_">SVE</a>
  AMED_AARCH64_ENCODING_MOV_sel_p_p_pp_, //!< <a href="../target/aarch64/MOV_sel_p_p_pp.html#MOV_sel_p_p_pp_">SVE</a>
  AMED_AARCH64_ENCODING_MOV_sel_z_p_zz_, //!< <a href="../target/aarch64/MOV_sel_z_p_zz.html#MOV_sel_z_p_zz_">SVE</a>
  AMED_AARCH64_ENCODING_MOVS_ands_p_p_pp_z, //!< <a href="../target/aarch64/MOVS_and_p_p_pp.html#MOVS_ands_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_MOVS_orrs_p_p_pp_z, //!< <a href="../target/aarch64/MOVS_orr_p_p_pp.html#MOVS_orrs_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_NOT_eor_p_p_pp_z, //!< <a href="../target/aarch64/NOT_eor_p_p_pp.html#NOT_eor_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_ENCODING_NOTS_eors_p_p_pp_z, //!< <a href="../target/aarch64/NOTS_eor_p_p_pp.html#NOTS_eors_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_ENCODING_ORN_orr_z_zi_, //!< <a href="../target/aarch64/ORN_orr_z_zi.html#ORN_orr_z_zi_">SVE</a>
} amed_aarch64_encoding;

#define AMED_AARCH64_TLBI_OP_MAX_TEXT_LENGTH (12 + 1)

typedef enum _amed_aarch64_tlbi_op
{
  AMED_AARCH64_TLBI_OP_NONE,
  AMED_AARCH64_TLBI_OP_ALLE1,
  AMED_AARCH64_TLBI_OP_ALLE1IS,
  AMED_AARCH64_TLBI_OP_ALLE1OS,
  AMED_AARCH64_TLBI_OP_ALLE2,
  AMED_AARCH64_TLBI_OP_ALLE2IS,
  AMED_AARCH64_TLBI_OP_ALLE2OS,
  AMED_AARCH64_TLBI_OP_ALLE3,
  AMED_AARCH64_TLBI_OP_ALLE3IS,
  AMED_AARCH64_TLBI_OP_ALLE3OS,
  AMED_AARCH64_TLBI_OP_ASIDE1,
  AMED_AARCH64_TLBI_OP_ASIDE1IS,
  AMED_AARCH64_TLBI_OP_ASIDE1OS,
  AMED_AARCH64_TLBI_OP_IPAS2E1,
  AMED_AARCH64_TLBI_OP_IPAS2E1IS,
  AMED_AARCH64_TLBI_OP_IPAS2E1OS,
  AMED_AARCH64_TLBI_OP_IPAS2LE1,
  AMED_AARCH64_TLBI_OP_IPAS2LE1IS,
  AMED_AARCH64_TLBI_OP_IPAS2LE1OS,
  AMED_AARCH64_TLBI_OP_RIPAS2E1,
  AMED_AARCH64_TLBI_OP_RIPAS2E1IS,
  AMED_AARCH64_TLBI_OP_RIPAS2E1OS,
  AMED_AARCH64_TLBI_OP_RIPAS2LE1,
  AMED_AARCH64_TLBI_OP_RIPAS2LE1IS,
  AMED_AARCH64_TLBI_OP_RIPAS2LE1OS,
  AMED_AARCH64_TLBI_OP_RVAAE1,
  AMED_AARCH64_TLBI_OP_RVAAE1IS,
  AMED_AARCH64_TLBI_OP_RVAAE1OS,
  AMED_AARCH64_TLBI_OP_RVAALE1,
  AMED_AARCH64_TLBI_OP_RVAALE1IS,
  AMED_AARCH64_TLBI_OP_RVAALE1OS,
  AMED_AARCH64_TLBI_OP_RVAE1,
  AMED_AARCH64_TLBI_OP_RVAE1IS,
  AMED_AARCH64_TLBI_OP_RVAE1OS,
  AMED_AARCH64_TLBI_OP_RVAE2,
  AMED_AARCH64_TLBI_OP_RVAE2IS,
  AMED_AARCH64_TLBI_OP_RVAE2OS,
  AMED_AARCH64_TLBI_OP_RVAE3,
  AMED_AARCH64_TLBI_OP_RVAE3IS,
  AMED_AARCH64_TLBI_OP_RVAE3OS,
  AMED_AARCH64_TLBI_OP_RVALE1,
  AMED_AARCH64_TLBI_OP_RVALE1IS,
  AMED_AARCH64_TLBI_OP_RVALE1OS,
  AMED_AARCH64_TLBI_OP_RVALE2,
  AMED_AARCH64_TLBI_OP_RVALE2IS,
  AMED_AARCH64_TLBI_OP_RVALE2OS,
  AMED_AARCH64_TLBI_OP_RVALE3,
  AMED_AARCH64_TLBI_OP_RVALE3IS,
  AMED_AARCH64_TLBI_OP_RVALE3OS,
  AMED_AARCH64_TLBI_OP_VAAE1,
  AMED_AARCH64_TLBI_OP_VAAE1IS,
  AMED_AARCH64_TLBI_OP_VAAE1OS,
  AMED_AARCH64_TLBI_OP_VAALE1,
  AMED_AARCH64_TLBI_OP_VAALE1IS,
  AMED_AARCH64_TLBI_OP_VAALE1OS,
  AMED_AARCH64_TLBI_OP_VAE1,
  AMED_AARCH64_TLBI_OP_VAE1IS,
  AMED_AARCH64_TLBI_OP_VAE1OS,
  AMED_AARCH64_TLBI_OP_VAE2,
  AMED_AARCH64_TLBI_OP_VAE2IS,
  AMED_AARCH64_TLBI_OP_VAE2OS,
  AMED_AARCH64_TLBI_OP_VAE3,
  AMED_AARCH64_TLBI_OP_VAE3IS,
  AMED_AARCH64_TLBI_OP_VAE3OS,
  AMED_AARCH64_TLBI_OP_VALE1,
  AMED_AARCH64_TLBI_OP_VALE1IS,
  AMED_AARCH64_TLBI_OP_VALE1OS,
  AMED_AARCH64_TLBI_OP_VALE2,
  AMED_AARCH64_TLBI_OP_VALE2IS,
  AMED_AARCH64_TLBI_OP_VALE2OS,
  AMED_AARCH64_TLBI_OP_VALE3,
  AMED_AARCH64_TLBI_OP_VALE3IS,
  AMED_AARCH64_TLBI_OP_VALE3OS,
  AMED_AARCH64_TLBI_OP_VMALLE1,
  AMED_AARCH64_TLBI_OP_VMALLE1IS,
  AMED_AARCH64_TLBI_OP_VMALLE1OS,
  AMED_AARCH64_TLBI_OP_VMALLS12E1,
  AMED_AARCH64_TLBI_OP_VMALLS12E1IS,
  AMED_AARCH64_TLBI_OP_VMALLS12E1OS,
} amed_aarch64_tlbi_op;

#define AMED_AARCH64_REGISTER_MAX_TEXT_LENGTH (4 + 1)

typedef enum _amed_aarch64_register
{
  AMED_AARCH64_REGISTER_NONE,
  AMED_AARCH64_REGISTER_W0,
  AMED_AARCH64_REGISTER_W1,
  AMED_AARCH64_REGISTER_W2,
  AMED_AARCH64_REGISTER_W3,
  AMED_AARCH64_REGISTER_W4,
  AMED_AARCH64_REGISTER_W5,
  AMED_AARCH64_REGISTER_W6,
  AMED_AARCH64_REGISTER_W7,
  AMED_AARCH64_REGISTER_W8,
  AMED_AARCH64_REGISTER_W9,
  AMED_AARCH64_REGISTER_W10,
  AMED_AARCH64_REGISTER_W11,
  AMED_AARCH64_REGISTER_W12,
  AMED_AARCH64_REGISTER_W13,
  AMED_AARCH64_REGISTER_W14,
  AMED_AARCH64_REGISTER_W15,
  AMED_AARCH64_REGISTER_W16,
  AMED_AARCH64_REGISTER_W17,
  AMED_AARCH64_REGISTER_W18,
  AMED_AARCH64_REGISTER_W19,
  AMED_AARCH64_REGISTER_W20,
  AMED_AARCH64_REGISTER_W21,
  AMED_AARCH64_REGISTER_W22,
  AMED_AARCH64_REGISTER_W23,
  AMED_AARCH64_REGISTER_W24,
  AMED_AARCH64_REGISTER_W25,
  AMED_AARCH64_REGISTER_W26,
  AMED_AARCH64_REGISTER_W27,
  AMED_AARCH64_REGISTER_W28,
  AMED_AARCH64_REGISTER_W29,
  AMED_AARCH64_REGISTER_W30,
  AMED_AARCH64_REGISTER_WZR,
  AMED_AARCH64_REGISTER_WSP,
  AMED_AARCH64_REGISTER_X0,
  AMED_AARCH64_REGISTER_X1,
  AMED_AARCH64_REGISTER_X2,
  AMED_AARCH64_REGISTER_X3,
  AMED_AARCH64_REGISTER_X4,
  AMED_AARCH64_REGISTER_X5,
  AMED_AARCH64_REGISTER_X6,
  AMED_AARCH64_REGISTER_X7,
  AMED_AARCH64_REGISTER_X8,
  AMED_AARCH64_REGISTER_X9,
  AMED_AARCH64_REGISTER_X10,
  AMED_AARCH64_REGISTER_X11,
  AMED_AARCH64_REGISTER_X12,
  AMED_AARCH64_REGISTER_X13,
  AMED_AARCH64_REGISTER_X14,
  AMED_AARCH64_REGISTER_X15,
  AMED_AARCH64_REGISTER_X16,
  AMED_AARCH64_REGISTER_X17,
  AMED_AARCH64_REGISTER_X18,
  AMED_AARCH64_REGISTER_X19,
  AMED_AARCH64_REGISTER_X20,
  AMED_AARCH64_REGISTER_X21,
  AMED_AARCH64_REGISTER_X22,
  AMED_AARCH64_REGISTER_X23,
  AMED_AARCH64_REGISTER_X24,
  AMED_AARCH64_REGISTER_X25,
  AMED_AARCH64_REGISTER_X26,
  AMED_AARCH64_REGISTER_X27,
  AMED_AARCH64_REGISTER_X28,
  AMED_AARCH64_REGISTER_X29,
  AMED_AARCH64_REGISTER_X30,
  AMED_AARCH64_REGISTER_XZR,
  AMED_AARCH64_REGISTER_SP,
  AMED_AARCH64_REGISTER_PC,
  AMED_AARCH64_REGISTER_B0,
  AMED_AARCH64_REGISTER_B1,
  AMED_AARCH64_REGISTER_B2,
  AMED_AARCH64_REGISTER_B3,
  AMED_AARCH64_REGISTER_B4,
  AMED_AARCH64_REGISTER_B5,
  AMED_AARCH64_REGISTER_B6,
  AMED_AARCH64_REGISTER_B7,
  AMED_AARCH64_REGISTER_B8,
  AMED_AARCH64_REGISTER_B9,
  AMED_AARCH64_REGISTER_B10,
  AMED_AARCH64_REGISTER_B11,
  AMED_AARCH64_REGISTER_B12,
  AMED_AARCH64_REGISTER_B13,
  AMED_AARCH64_REGISTER_B14,
  AMED_AARCH64_REGISTER_B15,
  AMED_AARCH64_REGISTER_B16,
  AMED_AARCH64_REGISTER_B17,
  AMED_AARCH64_REGISTER_B18,
  AMED_AARCH64_REGISTER_B19,
  AMED_AARCH64_REGISTER_B20,
  AMED_AARCH64_REGISTER_B21,
  AMED_AARCH64_REGISTER_B22,
  AMED_AARCH64_REGISTER_B23,
  AMED_AARCH64_REGISTER_B24,
  AMED_AARCH64_REGISTER_B25,
  AMED_AARCH64_REGISTER_B26,
  AMED_AARCH64_REGISTER_B27,
  AMED_AARCH64_REGISTER_B28,
  AMED_AARCH64_REGISTER_B29,
  AMED_AARCH64_REGISTER_B30,
  AMED_AARCH64_REGISTER_B31,
  AMED_AARCH64_REGISTER_H0,
  AMED_AARCH64_REGISTER_H1,
  AMED_AARCH64_REGISTER_H2,
  AMED_AARCH64_REGISTER_H3,
  AMED_AARCH64_REGISTER_H4,
  AMED_AARCH64_REGISTER_H5,
  AMED_AARCH64_REGISTER_H6,
  AMED_AARCH64_REGISTER_H7,
  AMED_AARCH64_REGISTER_H8,
  AMED_AARCH64_REGISTER_H9,
  AMED_AARCH64_REGISTER_H10,
  AMED_AARCH64_REGISTER_H11,
  AMED_AARCH64_REGISTER_H12,
  AMED_AARCH64_REGISTER_H13,
  AMED_AARCH64_REGISTER_H14,
  AMED_AARCH64_REGISTER_H15,
  AMED_AARCH64_REGISTER_H16,
  AMED_AARCH64_REGISTER_H17,
  AMED_AARCH64_REGISTER_H18,
  AMED_AARCH64_REGISTER_H19,
  AMED_AARCH64_REGISTER_H20,
  AMED_AARCH64_REGISTER_H21,
  AMED_AARCH64_REGISTER_H22,
  AMED_AARCH64_REGISTER_H23,
  AMED_AARCH64_REGISTER_H24,
  AMED_AARCH64_REGISTER_H25,
  AMED_AARCH64_REGISTER_H26,
  AMED_AARCH64_REGISTER_H27,
  AMED_AARCH64_REGISTER_H28,
  AMED_AARCH64_REGISTER_H29,
  AMED_AARCH64_REGISTER_H30,
  AMED_AARCH64_REGISTER_H31,
  AMED_AARCH64_REGISTER_S0,
  AMED_AARCH64_REGISTER_S1,
  AMED_AARCH64_REGISTER_S2,
  AMED_AARCH64_REGISTER_S3,
  AMED_AARCH64_REGISTER_S4,
  AMED_AARCH64_REGISTER_S5,
  AMED_AARCH64_REGISTER_S6,
  AMED_AARCH64_REGISTER_S7,
  AMED_AARCH64_REGISTER_S8,
  AMED_AARCH64_REGISTER_S9,
  AMED_AARCH64_REGISTER_S10,
  AMED_AARCH64_REGISTER_S11,
  AMED_AARCH64_REGISTER_S12,
  AMED_AARCH64_REGISTER_S13,
  AMED_AARCH64_REGISTER_S14,
  AMED_AARCH64_REGISTER_S15,
  AMED_AARCH64_REGISTER_S16,
  AMED_AARCH64_REGISTER_S17,
  AMED_AARCH64_REGISTER_S18,
  AMED_AARCH64_REGISTER_S19,
  AMED_AARCH64_REGISTER_S20,
  AMED_AARCH64_REGISTER_S21,
  AMED_AARCH64_REGISTER_S22,
  AMED_AARCH64_REGISTER_S23,
  AMED_AARCH64_REGISTER_S24,
  AMED_AARCH64_REGISTER_S25,
  AMED_AARCH64_REGISTER_S26,
  AMED_AARCH64_REGISTER_S27,
  AMED_AARCH64_REGISTER_S28,
  AMED_AARCH64_REGISTER_S29,
  AMED_AARCH64_REGISTER_S30,
  AMED_AARCH64_REGISTER_S31,
  AMED_AARCH64_REGISTER_D0,
  AMED_AARCH64_REGISTER_D1,
  AMED_AARCH64_REGISTER_D2,
  AMED_AARCH64_REGISTER_D3,
  AMED_AARCH64_REGISTER_D4,
  AMED_AARCH64_REGISTER_D5,
  AMED_AARCH64_REGISTER_D6,
  AMED_AARCH64_REGISTER_D7,
  AMED_AARCH64_REGISTER_D8,
  AMED_AARCH64_REGISTER_D9,
  AMED_AARCH64_REGISTER_D10,
  AMED_AARCH64_REGISTER_D11,
  AMED_AARCH64_REGISTER_D12,
  AMED_AARCH64_REGISTER_D13,
  AMED_AARCH64_REGISTER_D14,
  AMED_AARCH64_REGISTER_D15,
  AMED_AARCH64_REGISTER_D16,
  AMED_AARCH64_REGISTER_D17,
  AMED_AARCH64_REGISTER_D18,
  AMED_AARCH64_REGISTER_D19,
  AMED_AARCH64_REGISTER_D20,
  AMED_AARCH64_REGISTER_D21,
  AMED_AARCH64_REGISTER_D22,
  AMED_AARCH64_REGISTER_D23,
  AMED_AARCH64_REGISTER_D24,
  AMED_AARCH64_REGISTER_D25,
  AMED_AARCH64_REGISTER_D26,
  AMED_AARCH64_REGISTER_D27,
  AMED_AARCH64_REGISTER_D28,
  AMED_AARCH64_REGISTER_D29,
  AMED_AARCH64_REGISTER_D30,
  AMED_AARCH64_REGISTER_D31,
  AMED_AARCH64_REGISTER_Q0,
  AMED_AARCH64_REGISTER_Q1,
  AMED_AARCH64_REGISTER_Q2,
  AMED_AARCH64_REGISTER_Q3,
  AMED_AARCH64_REGISTER_Q4,
  AMED_AARCH64_REGISTER_Q5,
  AMED_AARCH64_REGISTER_Q6,
  AMED_AARCH64_REGISTER_Q7,
  AMED_AARCH64_REGISTER_Q8,
  AMED_AARCH64_REGISTER_Q9,
  AMED_AARCH64_REGISTER_Q10,
  AMED_AARCH64_REGISTER_Q11,
  AMED_AARCH64_REGISTER_Q12,
  AMED_AARCH64_REGISTER_Q13,
  AMED_AARCH64_REGISTER_Q14,
  AMED_AARCH64_REGISTER_Q15,
  AMED_AARCH64_REGISTER_Q16,
  AMED_AARCH64_REGISTER_Q17,
  AMED_AARCH64_REGISTER_Q18,
  AMED_AARCH64_REGISTER_Q19,
  AMED_AARCH64_REGISTER_Q20,
  AMED_AARCH64_REGISTER_Q21,
  AMED_AARCH64_REGISTER_Q22,
  AMED_AARCH64_REGISTER_Q23,
  AMED_AARCH64_REGISTER_Q24,
  AMED_AARCH64_REGISTER_Q25,
  AMED_AARCH64_REGISTER_Q26,
  AMED_AARCH64_REGISTER_Q27,
  AMED_AARCH64_REGISTER_Q28,
  AMED_AARCH64_REGISTER_Q29,
  AMED_AARCH64_REGISTER_Q30,
  AMED_AARCH64_REGISTER_Q31,
  AMED_AARCH64_REGISTER_V0,
  AMED_AARCH64_REGISTER_V1,
  AMED_AARCH64_REGISTER_V2,
  AMED_AARCH64_REGISTER_V3,
  AMED_AARCH64_REGISTER_V4,
  AMED_AARCH64_REGISTER_V5,
  AMED_AARCH64_REGISTER_V6,
  AMED_AARCH64_REGISTER_V7,
  AMED_AARCH64_REGISTER_V8,
  AMED_AARCH64_REGISTER_V9,
  AMED_AARCH64_REGISTER_V10,
  AMED_AARCH64_REGISTER_V11,
  AMED_AARCH64_REGISTER_V12,
  AMED_AARCH64_REGISTER_V13,
  AMED_AARCH64_REGISTER_V14,
  AMED_AARCH64_REGISTER_V15,
  AMED_AARCH64_REGISTER_V16,
  AMED_AARCH64_REGISTER_V17,
  AMED_AARCH64_REGISTER_V18,
  AMED_AARCH64_REGISTER_V19,
  AMED_AARCH64_REGISTER_V20,
  AMED_AARCH64_REGISTER_V21,
  AMED_AARCH64_REGISTER_V22,
  AMED_AARCH64_REGISTER_V23,
  AMED_AARCH64_REGISTER_V24,
  AMED_AARCH64_REGISTER_V25,
  AMED_AARCH64_REGISTER_V26,
  AMED_AARCH64_REGISTER_V27,
  AMED_AARCH64_REGISTER_V28,
  AMED_AARCH64_REGISTER_V29,
  AMED_AARCH64_REGISTER_V30,
  AMED_AARCH64_REGISTER_V31,
  AMED_AARCH64_REGISTER_P0,
  AMED_AARCH64_REGISTER_P1,
  AMED_AARCH64_REGISTER_P2,
  AMED_AARCH64_REGISTER_P3,
  AMED_AARCH64_REGISTER_P4,
  AMED_AARCH64_REGISTER_P5,
  AMED_AARCH64_REGISTER_P6,
  AMED_AARCH64_REGISTER_P7,
  AMED_AARCH64_REGISTER_P8,
  AMED_AARCH64_REGISTER_P9,
  AMED_AARCH64_REGISTER_P10,
  AMED_AARCH64_REGISTER_P11,
  AMED_AARCH64_REGISTER_P12,
  AMED_AARCH64_REGISTER_P13,
  AMED_AARCH64_REGISTER_P14,
  AMED_AARCH64_REGISTER_P15,
  AMED_AARCH64_REGISTER_Z0,
  AMED_AARCH64_REGISTER_Z1,
  AMED_AARCH64_REGISTER_Z2,
  AMED_AARCH64_REGISTER_Z3,
  AMED_AARCH64_REGISTER_Z4,
  AMED_AARCH64_REGISTER_Z5,
  AMED_AARCH64_REGISTER_Z6,
  AMED_AARCH64_REGISTER_Z7,
  AMED_AARCH64_REGISTER_Z8,
  AMED_AARCH64_REGISTER_Z9,
  AMED_AARCH64_REGISTER_Z10,
  AMED_AARCH64_REGISTER_Z11,
  AMED_AARCH64_REGISTER_Z12,
  AMED_AARCH64_REGISTER_Z13,
  AMED_AARCH64_REGISTER_Z14,
  AMED_AARCH64_REGISTER_Z15,
  AMED_AARCH64_REGISTER_Z16,
  AMED_AARCH64_REGISTER_Z17,
  AMED_AARCH64_REGISTER_Z18,
  AMED_AARCH64_REGISTER_Z19,
  AMED_AARCH64_REGISTER_Z20,
  AMED_AARCH64_REGISTER_Z21,
  AMED_AARCH64_REGISTER_Z22,
  AMED_AARCH64_REGISTER_Z23,
  AMED_AARCH64_REGISTER_Z24,
  AMED_AARCH64_REGISTER_Z25,
  AMED_AARCH64_REGISTER_Z26,
  AMED_AARCH64_REGISTER_Z27,
  AMED_AARCH64_REGISTER_Z28,
  AMED_AARCH64_REGISTER_Z29,
  AMED_AARCH64_REGISTER_Z30,
  AMED_AARCH64_REGISTER_Z31,
} amed_aarch64_register;

#define AMED_AARCH64_CCLASS_MAX_TEXT_LENGTH (38 + 1)

typedef enum _amed_aarch64_cclass
{
  AMED_AARCH64_CCLASS_NONE,
  AMED_AARCH64_CCLASS_invalid, //!< <a href="../target/aarch64/invalid.html#invalid">INVALID</a>
  AMED_AARCH64_CCLASS_ADC_no_s, //!< <a href="../target/aarch64/ADC.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_ADCS_s, //!< <a href="../target/aarch64/ADCS.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_ADD_addsub_ext_no_s, //!< <a href="../target/aarch64/ADD_addsub_ext.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_ADD_addsub_imm_no_s, //!< <a href="../target/aarch64/ADD_addsub_imm.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_ADD_addsub_shift_no_s, //!< <a href="../target/aarch64/ADD_addsub_shift.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_ADDG_64_addsub_immtags, //!< <a href="../target/aarch64/ADDG.html#ADDG_64_addsub_immtags">Integer</a>
  AMED_AARCH64_CCLASS_ADDS_addsub_ext_s, //!< <a href="../target/aarch64/ADDS_addsub_ext.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_ADDS_addsub_imm_s, //!< <a href="../target/aarch64/ADDS_addsub_imm.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_ADDS_addsub_shift_s, //!< <a href="../target/aarch64/ADDS_addsub_shift.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_ADR_only_pcreladdr, //!< <a href="../target/aarch64/ADR.html#ADR_only_pcreladdr">Literal</a>
  AMED_AARCH64_CCLASS_ADRP_only_pcreladdr, //!< <a href="../target/aarch64/ADRP.html#ADRP_only_pcreladdr">Literal</a>
  AMED_AARCH64_CCLASS_AND_log_imm_no_s, //!< <a href="../target/aarch64/AND_log_imm.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_AND_log_shift_no_s, //!< <a href="../target/aarch64/AND_log_shift.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_ANDS_log_imm_s, //!< <a href="../target/aarch64/ANDS_log_imm.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_ANDS_log_shift_s, //!< <a href="../target/aarch64/ANDS_log_shift.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_ASRV_general, //!< <a href="../target/aarch64/ASRV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_AUTDA_general, //!< <a href="../target/aarch64/AUTDA.html#general">Integer</a>
  AMED_AARCH64_CCLASS_AUTDB_general, //!< <a href="../target/aarch64/AUTDB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_AUTIA_general, //!< <a href="../target/aarch64/AUTIA.html#general">Integer</a>
  AMED_AARCH64_CCLASS_AUTIA_system, //!< <a href="../target/aarch64/AUTIA.html#system">System</a>
  AMED_AARCH64_CCLASS_AUTIB_general, //!< <a href="../target/aarch64/AUTIB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_AUTIB_system, //!< <a href="../target/aarch64/AUTIB.html#system">System</a>
  AMED_AARCH64_CCLASS_AXFLAG_M_pstate, //!< <a href="../target/aarch64/AXFLAG.html#AXFLAG_M_pstate">System</a>
  AMED_AARCH64_CCLASS_B_only_condbranch, //!< <a href="../target/aarch64/B_cond.html#B_only_condbranch">19-bit signed PC-relative branch offset</a>
  AMED_AARCH64_CCLASS_B_only_branch_imm, //!< <a href="../target/aarch64/B_uncond.html#B_only_branch_imm">26-bit signed PC-relative branch offset</a>
  AMED_AARCH64_CCLASS_BFM_nofill, //!< <a href="../target/aarch64/BFM.html#nofill">Leaving other bits unchanged</a>
  AMED_AARCH64_CCLASS_BIC_log_shift_no_s, //!< <a href="../target/aarch64/BIC_log_shift.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_BICS_s, //!< <a href="../target/aarch64/BICS.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_BL_only_branch_imm, //!< <a href="../target/aarch64/BL.html#BL_only_branch_imm">26-bit signed PC-relative branch offset</a>
  AMED_AARCH64_CCLASS_BLR_64_branch_reg, //!< <a href="../target/aarch64/BLR.html#BLR_64_branch_reg">Integer</a>
  AMED_AARCH64_CCLASS_BLRA_general, //!< <a href="../target/aarch64/BLRA.html#general">Integer</a>
  AMED_AARCH64_CCLASS_BR_64_branch_reg, //!< <a href="../target/aarch64/BR.html#BR_64_branch_reg">Integer</a>
  AMED_AARCH64_CCLASS_BRA_general, //!< <a href="../target/aarch64/BRA.html#general">Integer</a>
  AMED_AARCH64_CCLASS_BRK_EX_exception, //!< <a href="../target/aarch64/BRK.html#BRK_EX_exception">System</a>
  AMED_AARCH64_CCLASS_BTI_HB_hints, //!< <a href="../target/aarch64/BTI.html#BTI_HB_hints">System</a>
  AMED_AARCH64_CCLASS_CAS_base_register, //!< <a href="../target/aarch64/CAS.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_CASB_base_register, //!< <a href="../target/aarch64/CASB.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_CASH_base_register, //!< <a href="../target/aarch64/CASH.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_CASP_base_register, //!< <a href="../target/aarch64/CASP.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_CBNZ_br19, //!< <a href="../target/aarch64/CBNZ.html#br19">19-bit signed PC-relative branch offset</a>
  AMED_AARCH64_CCLASS_CBZ_br19, //!< <a href="../target/aarch64/CBZ.html#br19">19-bit signed PC-relative branch offset</a>
  AMED_AARCH64_CCLASS_CCMN_imm_imm5u, //!< <a href="../target/aarch64/CCMN_imm.html#imm5u">5-bit unsigned immediate</a>
  AMED_AARCH64_CCLASS_CCMN_reg_general, //!< <a href="../target/aarch64/CCMN_reg.html#general">Integer</a>
  AMED_AARCH64_CCLASS_CCMP_imm_imm5u, //!< <a href="../target/aarch64/CCMP_imm.html#imm5u">5-bit unsigned immediate</a>
  AMED_AARCH64_CCLASS_CCMP_reg_general, //!< <a href="../target/aarch64/CCMP_reg.html#general">Integer</a>
  AMED_AARCH64_CCLASS_CFINV_M_pstate, //!< <a href="../target/aarch64/CFINV.html#CFINV_M_pstate">System</a>
  AMED_AARCH64_CCLASS_CLREX_BN_barriers, //!< <a href="../target/aarch64/CLREX.html#CLREX_BN_barriers">System</a>
  AMED_AARCH64_CCLASS_CLS_int_general, //!< <a href="../target/aarch64/CLS_int.html#general">Integer</a>
  AMED_AARCH64_CCLASS_CLZ_int_general, //!< <a href="../target/aarch64/CLZ_int.html#general">Integer</a>
  AMED_AARCH64_CCLASS_CRC32_crc, //!< <a href="../target/aarch64/CRC32.html#crc">CRC</a>
  AMED_AARCH64_CCLASS_CRC32C_crc, //!< <a href="../target/aarch64/CRC32C.html#crc">CRC</a>
  AMED_AARCH64_CCLASS_CSDB_HI_hints, //!< <a href="../target/aarch64/CSDB.html#CSDB_HI_hints">System</a>
  AMED_AARCH64_CCLASS_CSEL_general, //!< <a href="../target/aarch64/CSEL.html#general">Integer</a>
  AMED_AARCH64_CCLASS_CSINC_general, //!< <a href="../target/aarch64/CSINC.html#general">Integer</a>
  AMED_AARCH64_CCLASS_CSINV_general, //!< <a href="../target/aarch64/CSINV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_CSNEG_general, //!< <a href="../target/aarch64/CSNEG.html#general">Integer</a>
  AMED_AARCH64_CCLASS_DCPS1_DC_exception, //!< <a href="../target/aarch64/DCPS1.html#DCPS1_DC_exception">System</a>
  AMED_AARCH64_CCLASS_DCPS2_DC_exception, //!< <a href="../target/aarch64/DCPS2.html#DCPS2_DC_exception">System</a>
  AMED_AARCH64_CCLASS_DCPS3_DC_exception, //!< <a href="../target/aarch64/DCPS3.html#DCPS3_DC_exception">System</a>
  AMED_AARCH64_CCLASS_DGH_HI_hints, //!< <a href="../target/aarch64/DGH.html#DGH_HI_hints">System</a>
  AMED_AARCH64_CCLASS_DMB_BO_barriers, //!< <a href="../target/aarch64/DMB.html#DMB_BO_barriers">System</a>
  AMED_AARCH64_CCLASS_DRPS_64E_branch_reg, //!< <a href="../target/aarch64/DRPS.html#DRPS_64E_branch_reg">System</a>
  AMED_AARCH64_CCLASS_DSB_DSB_BO_barriers, //!< <a href="../target/aarch64/DSB.html#DSB_BO_barriers">System</a>
  AMED_AARCH64_CCLASS_EON_no_s, //!< <a href="../target/aarch64/EON.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_EOR_log_imm_no_s, //!< <a href="../target/aarch64/EOR_log_imm.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_EOR_log_shift_general, //!< <a href="../target/aarch64/EOR_log_shift.html#general">Integer</a>
  AMED_AARCH64_CCLASS_ERET_64E_branch_reg, //!< <a href="../target/aarch64/ERET.html#ERET_64E_branch_reg">System</a>
  AMED_AARCH64_CCLASS_ERETA_general, //!< <a href="../target/aarch64/ERETA.html#general">Integer</a>
  AMED_AARCH64_CCLASS_ESB_HI_hints, //!< <a href="../target/aarch64/ESB.html#ESB_HI_hints">System</a>
  AMED_AARCH64_CCLASS_EXTR_general, //!< <a href="../target/aarch64/EXTR.html#general">Integer</a>
  AMED_AARCH64_CCLASS_GMI_64G_dp_2src, //!< <a href="../target/aarch64/GMI.html#GMI_64G_dp_2src">Integer</a>
  AMED_AARCH64_CCLASS_HINT_HM_hints, //!< <a href="../target/aarch64/HINT.html#HINT_HM_hints">System</a>
  AMED_AARCH64_CCLASS_HLT_EX_exception, //!< <a href="../target/aarch64/HLT.html#HLT_EX_exception">System</a>
  AMED_AARCH64_CCLASS_HVC_EX_exception, //!< <a href="../target/aarch64/HVC.html#HVC_EX_exception">System</a>
  AMED_AARCH64_CCLASS_IRG_64I_dp_2src, //!< <a href="../target/aarch64/IRG.html#IRG_64I_dp_2src">Integer</a>
  AMED_AARCH64_CCLASS_ISB_BI_barriers, //!< <a href="../target/aarch64/ISB.html#ISB_BI_barriers">System</a>
  AMED_AARCH64_CCLASS_LDADD_general, //!< <a href="../target/aarch64/LDADD.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDADDB_general, //!< <a href="../target/aarch64/LDADDB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDADDH_general, //!< <a href="../target/aarch64/LDADDH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDAPR_general, //!< <a href="../target/aarch64/LDAPR.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDAPRB_32L_memop, //!< <a href="../target/aarch64/LDAPRB.html#LDAPRB_32L_memop">Integer</a>
  AMED_AARCH64_CCLASS_LDAPRH_32L_memop, //!< <a href="../target/aarch64/LDAPRH.html#LDAPRH_32L_memop">Integer</a>
  AMED_AARCH64_CCLASS_LDAPUR_gen_base_plus_offset, //!< <a href="../target/aarch64/LDAPUR_gen.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDAPURB_32_ldapstl_unscaled, //!< <a href="../target/aarch64/LDAPURB.html#LDAPURB_32_ldapstl_unscaled">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDAPURH_32_ldapstl_unscaled, //!< <a href="../target/aarch64/LDAPURH.html#LDAPURH_32_ldapstl_unscaled">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDAPURSB_base_plus_offset, //!< <a href="../target/aarch64/LDAPURSB.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDAPURSH_base_plus_offset, //!< <a href="../target/aarch64/LDAPURSH.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDAPURSW_64_ldapstl_unscaled, //!< <a href="../target/aarch64/LDAPURSW.html#LDAPURSW_64_ldapstl_unscaled">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDAR_base_register, //!< <a href="../target/aarch64/LDAR.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_LDARB_LR32_ldstexcl, //!< <a href="../target/aarch64/LDARB.html#LDARB_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_LDARH_LR32_ldstexcl, //!< <a href="../target/aarch64/LDARH.html#LDARH_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_LDAXP_base_register, //!< <a href="../target/aarch64/LDAXP.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_LDAXR_base_register, //!< <a href="../target/aarch64/LDAXR.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_LDAXRB_LR32_ldstexcl, //!< <a href="../target/aarch64/LDAXRB.html#LDAXRB_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_LDAXRH_LR32_ldstexcl, //!< <a href="../target/aarch64/LDAXRH.html#LDAXRH_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_LDCLR_general, //!< <a href="../target/aarch64/LDCLR.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDCLRB_general, //!< <a href="../target/aarch64/LDCLRB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDCLRH_general, //!< <a href="../target/aarch64/LDCLRH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDEOR_general, //!< <a href="../target/aarch64/LDEOR.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDEORB_general, //!< <a href="../target/aarch64/LDEORB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDEORH_general, //!< <a href="../target/aarch64/LDEORH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDG_64Loffset_ldsttags, //!< <a href="../target/aarch64/LDG.html#LDG_64Loffset_ldsttags">Integer</a>
  AMED_AARCH64_CCLASS_LDGM_64bulk_ldsttags, //!< <a href="../target/aarch64/LDGM.html#LDGM_64bulk_ldsttags">Integer</a>
  AMED_AARCH64_CCLASS_LDLAR_base_register, //!< <a href="../target/aarch64/LDLAR.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_LDLARB_LR32_ldstexcl, //!< <a href="../target/aarch64/LDLARB.html#LDLARB_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_LDLARH_LR32_ldstexcl, //!< <a href="../target/aarch64/LDLARH.html#LDLARH_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_LDNP_gen_signed_scaled_offset, //!< <a href="../target/aarch64/LDNP_gen.html#signed_scaled_offset">Signed offset</a>
  AMED_AARCH64_CCLASS_LDP_gen_post_indexed, //!< <a href="../target/aarch64/LDP_gen.html#post_indexed">Post-index</a>
  AMED_AARCH64_CCLASS_LDP_gen_pre_indexed, //!< <a href="../target/aarch64/LDP_gen.html#pre_indexed">Pre-index</a>
  AMED_AARCH64_CCLASS_LDP_gen_signed_scaled_offset, //!< <a href="../target/aarch64/LDP_gen.html#signed_scaled_offset">Signed offset</a>
  AMED_AARCH64_CCLASS_LDPSW_64_ldstpair_post, //!< <a href="../target/aarch64/LDPSW.html#LDPSW_64_ldstpair_post">Post-index</a>
  AMED_AARCH64_CCLASS_LDPSW_64_ldstpair_pre, //!< <a href="../target/aarch64/LDPSW.html#LDPSW_64_ldstpair_pre">Pre-index</a>
  AMED_AARCH64_CCLASS_LDPSW_64_ldstpair_off, //!< <a href="../target/aarch64/LDPSW.html#LDPSW_64_ldstpair_off">Signed offset</a>
  AMED_AARCH64_CCLASS_LDR_imm_gen_post_indexed, //!< <a href="../target/aarch64/LDR_imm_gen.html#post_indexed">Post-index</a>
  AMED_AARCH64_CCLASS_LDR_imm_gen_pre_indexed, //!< <a href="../target/aarch64/LDR_imm_gen.html#pre_indexed">Pre-index</a>
  AMED_AARCH64_CCLASS_LDR_imm_gen_unsigned_scaled_offset, //!< <a href="../target/aarch64/LDR_imm_gen.html#unsigned_scaled_offset">Unsigned offset</a>
  AMED_AARCH64_CCLASS_LDR_lit_gen_literal, //!< <a href="../target/aarch64/LDR_lit_gen.html#literal">Literal</a>
  AMED_AARCH64_CCLASS_LDR_reg_gen_general, //!< <a href="../target/aarch64/LDR_reg_gen.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDRA_base_plus_offset, //!< <a href="../target/aarch64/LDRA.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDRB_32_ldst_immpost, //!< <a href="../target/aarch64/LDRB_imm.html#LDRB_32_ldst_immpost">Post-index</a>
  AMED_AARCH64_CCLASS_LDRB_32_ldst_immpre, //!< <a href="../target/aarch64/LDRB_imm.html#LDRB_32_ldst_immpre">Pre-index</a>
  AMED_AARCH64_CCLASS_LDRB_32_ldst_pos, //!< <a href="../target/aarch64/LDRB_imm.html#LDRB_32_ldst_pos">Unsigned offset</a>
  AMED_AARCH64_CCLASS_LDRB_reg_32, //!< <a href="../target/aarch64/LDRB_reg.html#32">32-bit</a>
  AMED_AARCH64_CCLASS_LDRH_32_ldst_immpost, //!< <a href="../target/aarch64/LDRH_imm.html#LDRH_32_ldst_immpost">Post-index</a>
  AMED_AARCH64_CCLASS_LDRH_32_ldst_immpre, //!< <a href="../target/aarch64/LDRH_imm.html#LDRH_32_ldst_immpre">Pre-index</a>
  AMED_AARCH64_CCLASS_LDRH_32_ldst_pos, //!< <a href="../target/aarch64/LDRH_imm.html#LDRH_32_ldst_pos">Unsigned offset</a>
  AMED_AARCH64_CCLASS_LDRH_32_ldst_regoff, //!< <a href="../target/aarch64/LDRH_reg.html#LDRH_32_ldst_regoff">32-bit</a>
  AMED_AARCH64_CCLASS_LDRSB_imm_post_indexed, //!< <a href="../target/aarch64/LDRSB_imm.html#post_indexed">Post-index</a>
  AMED_AARCH64_CCLASS_LDRSB_imm_pre_indexed, //!< <a href="../target/aarch64/LDRSB_imm.html#pre_indexed">Pre-index</a>
  AMED_AARCH64_CCLASS_LDRSB_imm_unsigned_scaled_offset, //!< <a href="../target/aarch64/LDRSB_imm.html#unsigned_scaled_offset">Unsigned offset</a>
  AMED_AARCH64_CCLASS_LDRSB_reg_general, //!< <a href="../target/aarch64/LDRSB_reg.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDRSH_imm_post_indexed, //!< <a href="../target/aarch64/LDRSH_imm.html#post_indexed">Post-index</a>
  AMED_AARCH64_CCLASS_LDRSH_imm_pre_indexed, //!< <a href="../target/aarch64/LDRSH_imm.html#pre_indexed">Pre-index</a>
  AMED_AARCH64_CCLASS_LDRSH_imm_unsigned_scaled_offset, //!< <a href="../target/aarch64/LDRSH_imm.html#unsigned_scaled_offset">Unsigned offset</a>
  AMED_AARCH64_CCLASS_LDRSH_reg_general, //!< <a href="../target/aarch64/LDRSH_reg.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDRSW_64_ldst_immpost, //!< <a href="../target/aarch64/LDRSW_imm.html#LDRSW_64_ldst_immpost">Post-index</a>
  AMED_AARCH64_CCLASS_LDRSW_64_ldst_immpre, //!< <a href="../target/aarch64/LDRSW_imm.html#LDRSW_64_ldst_immpre">Pre-index</a>
  AMED_AARCH64_CCLASS_LDRSW_64_ldst_pos, //!< <a href="../target/aarch64/LDRSW_imm.html#LDRSW_64_ldst_pos">Unsigned offset</a>
  AMED_AARCH64_CCLASS_LDRSW_64_loadlit, //!< <a href="../target/aarch64/LDRSW_lit.html#LDRSW_64_loadlit">Literal</a>
  AMED_AARCH64_CCLASS_LDRSW_64_ldst_regoff, //!< <a href="../target/aarch64/LDRSW_reg.html#LDRSW_64_ldst_regoff">64-bit</a>
  AMED_AARCH64_CCLASS_LDSET_general, //!< <a href="../target/aarch64/LDSET.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDSETB_general, //!< <a href="../target/aarch64/LDSETB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDSETH_general, //!< <a href="../target/aarch64/LDSETH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDSMAX_general, //!< <a href="../target/aarch64/LDSMAX.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDSMAXB_general, //!< <a href="../target/aarch64/LDSMAXB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDSMAXH_general, //!< <a href="../target/aarch64/LDSMAXH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDSMIN_general, //!< <a href="../target/aarch64/LDSMIN.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDSMINB_general, //!< <a href="../target/aarch64/LDSMINB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDSMINH_general, //!< <a href="../target/aarch64/LDSMINH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDTR_base_plus_offset, //!< <a href="../target/aarch64/LDTR.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDTRB_32_ldst_unpriv, //!< <a href="../target/aarch64/LDTRB.html#LDTRB_32_ldst_unpriv">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDTRH_32_ldst_unpriv, //!< <a href="../target/aarch64/LDTRH.html#LDTRH_32_ldst_unpriv">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDTRSB_base_plus_offset, //!< <a href="../target/aarch64/LDTRSB.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDTRSH_base_plus_offset, //!< <a href="../target/aarch64/LDTRSH.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDTRSW_64_ldst_unpriv, //!< <a href="../target/aarch64/LDTRSW.html#LDTRSW_64_ldst_unpriv">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDUMAX_general, //!< <a href="../target/aarch64/LDUMAX.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDUMAXB_general, //!< <a href="../target/aarch64/LDUMAXB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDUMAXH_general, //!< <a href="../target/aarch64/LDUMAXH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDUMIN_general, //!< <a href="../target/aarch64/LDUMIN.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDUMINB_general, //!< <a href="../target/aarch64/LDUMINB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDUMINH_general, //!< <a href="../target/aarch64/LDUMINH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LDUR_gen_base_plus_offset, //!< <a href="../target/aarch64/LDUR_gen.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDURB_32_ldst_unscaled, //!< <a href="../target/aarch64/LDURB.html#LDURB_32_ldst_unscaled">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDURH_32_ldst_unscaled, //!< <a href="../target/aarch64/LDURH.html#LDURH_32_ldst_unscaled">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDURSB_base_plus_offset, //!< <a href="../target/aarch64/LDURSB.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDURSH_base_plus_offset, //!< <a href="../target/aarch64/LDURSH.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDURSW_64_ldst_unscaled, //!< <a href="../target/aarch64/LDURSW.html#LDURSW_64_ldst_unscaled">Unscaled offset</a>
  AMED_AARCH64_CCLASS_LDXP_base_register, //!< <a href="../target/aarch64/LDXP.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_LDXR_base_register, //!< <a href="../target/aarch64/LDXR.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_LDXRB_LR32_ldstexcl, //!< <a href="../target/aarch64/LDXRB.html#LDXRB_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_LDXRH_LR32_ldstexcl, //!< <a href="../target/aarch64/LDXRH.html#LDXRH_LR32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_LSLV_general, //!< <a href="../target/aarch64/LSLV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LSRV_general, //!< <a href="../target/aarch64/LSRV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_MADD_general, //!< <a href="../target/aarch64/MADD.html#general">Integer</a>
  AMED_AARCH64_CCLASS_MOVK_imm18_packed, //!< <a href="../target/aarch64/MOVK.html#imm18_packed">Immediate packed into 16-bit value and 2-bit shift</a>
  AMED_AARCH64_CCLASS_MOVN_imm18_packed, //!< <a href="../target/aarch64/MOVN.html#imm18_packed">Immediate packed into 16-bit value and 2-bit shift</a>
  AMED_AARCH64_CCLASS_MOVZ_imm18_packed, //!< <a href="../target/aarch64/MOVZ.html#imm18_packed">Immediate packed into 16-bit value and 2-bit shift</a>
  AMED_AARCH64_CCLASS_MRS_RS_systemmove, //!< <a href="../target/aarch64/MRS.html#MRS_RS_systemmove">System</a>
  AMED_AARCH64_CCLASS_MSR_SI_pstate, //!< <a href="../target/aarch64/MSR_imm.html#MSR_SI_pstate">System</a>
  AMED_AARCH64_CCLASS_MSR_SR_systemmove, //!< <a href="../target/aarch64/MSR_reg.html#MSR_SR_systemmove">System</a>
  AMED_AARCH64_CCLASS_MSUB_general, //!< <a href="../target/aarch64/MSUB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_NOP_HI_hints, //!< <a href="../target/aarch64/NOP.html#NOP_HI_hints">System</a>
  AMED_AARCH64_CCLASS_ORN_log_shift_no_s, //!< <a href="../target/aarch64/ORN_log_shift.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_ORR_log_imm_no_s, //!< <a href="../target/aarch64/ORR_log_imm.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_ORR_log_shift_no_s, //!< <a href="../target/aarch64/ORR_log_shift.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_PACDA_general, //!< <a href="../target/aarch64/PACDA.html#general">Integer</a>
  AMED_AARCH64_CCLASS_PACDB_general, //!< <a href="../target/aarch64/PACDB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_PACGA_64P_dp_2src, //!< <a href="../target/aarch64/PACGA.html#PACGA_64P_dp_2src">Integer</a>
  AMED_AARCH64_CCLASS_PACIA_general, //!< <a href="../target/aarch64/PACIA.html#general">Integer</a>
  AMED_AARCH64_CCLASS_PACIA_system, //!< <a href="../target/aarch64/PACIA.html#system">System</a>
  AMED_AARCH64_CCLASS_PACIB_general, //!< <a href="../target/aarch64/PACIB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_PACIB_system, //!< <a href="../target/aarch64/PACIB.html#system">System</a>
  AMED_AARCH64_CCLASS_PRFM_P_ldst_pos, //!< <a href="../target/aarch64/PRFM_imm.html#PRFM_P_ldst_pos">Unsigned offset</a>
  AMED_AARCH64_CCLASS_PRFM_P_loadlit, //!< <a href="../target/aarch64/PRFM_lit.html#PRFM_P_loadlit">Literal</a>
  AMED_AARCH64_CCLASS_PRFM_P_ldst_regoff, //!< <a href="../target/aarch64/PRFM_reg.html#PRFM_P_ldst_regoff">Integer</a>
  AMED_AARCH64_CCLASS_PRFUM_P_ldst_unscaled, //!< <a href="../target/aarch64/PRFUM.html#PRFUM_P_ldst_unscaled">Unscaled offset</a>
  AMED_AARCH64_CCLASS_PSB_HC_hints, //!< <a href="../target/aarch64/PSB.html#PSB_HC_hints">System</a>
  AMED_AARCH64_CCLASS_PSSBB_only_barriers, //!< <a href="../target/aarch64/PSSBB.html#PSSBB_only_barriers">System</a>
  AMED_AARCH64_CCLASS_RBIT_int_general, //!< <a href="../target/aarch64/RBIT_int.html#general">Integer</a>
  AMED_AARCH64_CCLASS_RET_64R_branch_reg, //!< <a href="../target/aarch64/RET.html#RET_64R_branch_reg">Integer</a>
  AMED_AARCH64_CCLASS_RETA_general, //!< <a href="../target/aarch64/RETA.html#general">Integer</a>
  AMED_AARCH64_CCLASS_REV_general, //!< <a href="../target/aarch64/REV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_REV16_int_general, //!< <a href="../target/aarch64/REV16_int.html#general">Integer</a>
  AMED_AARCH64_CCLASS_REV32_64_dp_1src, //!< <a href="../target/aarch64/REV32_int.html#REV32_64_dp_1src">64-bit</a>
  AMED_AARCH64_CCLASS_RMIF_only_rmif, //!< <a href="../target/aarch64/RMIF.html#RMIF_only_rmif">Integer</a>
  AMED_AARCH64_CCLASS_RORV_general, //!< <a href="../target/aarch64/RORV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_SB_only_barriers, //!< <a href="../target/aarch64/SB.html#SB_only_barriers">System</a>
  AMED_AARCH64_CCLASS_SBC_no_s, //!< <a href="../target/aarch64/SBC.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_SBCS_s, //!< <a href="../target/aarch64/SBCS.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_SBFM_signed_fill, //!< <a href="../target/aarch64/SBFM.html#signed_fill">With sign replication to left and zeros to right</a>
  AMED_AARCH64_CCLASS_SDIV_general, //!< <a href="../target/aarch64/SDIV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_SETF_general, //!< <a href="../target/aarch64/SETF.html#general">Integer</a>
  AMED_AARCH64_CCLASS_SEV_HI_hints, //!< <a href="../target/aarch64/SEV.html#SEV_HI_hints">System</a>
  AMED_AARCH64_CCLASS_SEVL_HI_hints, //!< <a href="../target/aarch64/SEVL.html#SEVL_HI_hints">System</a>
  AMED_AARCH64_CCLASS_SMADDL_SMADDL_64WA_dp_3src, //!< <a href="../target/aarch64/SMADDL.html#SMADDL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_CCLASS_SMC_EX_exception, //!< <a href="../target/aarch64/SMC.html#SMC_EX_exception">System</a>
  AMED_AARCH64_CCLASS_SMSUBL_SMSUBL_64WA_dp_3src, //!< <a href="../target/aarch64/SMSUBL.html#SMSUBL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_CCLASS_SMULH_64_dp_3src, //!< <a href="../target/aarch64/SMULH.html#SMULH_64_dp_3src">64-bit</a>
  AMED_AARCH64_CCLASS_SSBB_only_barriers, //!< <a href="../target/aarch64/SSBB.html#SSBB_only_barriers">System</a>
  AMED_AARCH64_CCLASS_ST2G_64Spost_ldsttags, //!< <a href="../target/aarch64/ST2G.html#ST2G_64Spost_ldsttags">Post-index</a>
  AMED_AARCH64_CCLASS_ST2G_64Spre_ldsttags, //!< <a href="../target/aarch64/ST2G.html#ST2G_64Spre_ldsttags">Pre-index</a>
  AMED_AARCH64_CCLASS_ST2G_64Soffset_ldsttags, //!< <a href="../target/aarch64/ST2G.html#ST2G_64Soffset_ldsttags">Signed offset</a>
  AMED_AARCH64_CCLASS_STG_64Spost_ldsttags, //!< <a href="../target/aarch64/STG.html#STG_64Spost_ldsttags">Post-index</a>
  AMED_AARCH64_CCLASS_STG_64Spre_ldsttags, //!< <a href="../target/aarch64/STG.html#STG_64Spre_ldsttags">Pre-index</a>
  AMED_AARCH64_CCLASS_STG_64Soffset_ldsttags, //!< <a href="../target/aarch64/STG.html#STG_64Soffset_ldsttags">Signed offset</a>
  AMED_AARCH64_CCLASS_STGM_64bulk_ldsttags, //!< <a href="../target/aarch64/STGM.html#STGM_64bulk_ldsttags">Integer</a>
  AMED_AARCH64_CCLASS_STGP_64_ldstpair_post, //!< <a href="../target/aarch64/STGP.html#STGP_64_ldstpair_post">Post-index</a>
  AMED_AARCH64_CCLASS_STGP_64_ldstpair_pre, //!< <a href="../target/aarch64/STGP.html#STGP_64_ldstpair_pre">Pre-index</a>
  AMED_AARCH64_CCLASS_STGP_64_ldstpair_off, //!< <a href="../target/aarch64/STGP.html#STGP_64_ldstpair_off">Signed offset</a>
  AMED_AARCH64_CCLASS_STLLR_base_register, //!< <a href="../target/aarch64/STLLR.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_STLLRB_SL32_ldstexcl, //!< <a href="../target/aarch64/STLLRB.html#STLLRB_SL32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_STLLRH_SL32_ldstexcl, //!< <a href="../target/aarch64/STLLRH.html#STLLRH_SL32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_STLR_base_register, //!< <a href="../target/aarch64/STLR.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_STLRB_SL32_ldstexcl, //!< <a href="../target/aarch64/STLRB.html#STLRB_SL32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_STLRH_SL32_ldstexcl, //!< <a href="../target/aarch64/STLRH.html#STLRH_SL32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_STLUR_gen_base_plus_offset, //!< <a href="../target/aarch64/STLUR_gen.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_STLURB_32_ldapstl_unscaled, //!< <a href="../target/aarch64/STLURB.html#STLURB_32_ldapstl_unscaled">Unscaled offset</a>
  AMED_AARCH64_CCLASS_STLURH_32_ldapstl_unscaled, //!< <a href="../target/aarch64/STLURH.html#STLURH_32_ldapstl_unscaled">Unscaled offset</a>
  AMED_AARCH64_CCLASS_STLXP_base_register, //!< <a href="../target/aarch64/STLXP.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_STLXR_base_register, //!< <a href="../target/aarch64/STLXR.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_STLXRB_SR32_ldstexcl, //!< <a href="../target/aarch64/STLXRB.html#STLXRB_SR32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_STLXRH_SR32_ldstexcl, //!< <a href="../target/aarch64/STLXRH.html#STLXRH_SR32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_STNP_gen_signed_scaled_offset, //!< <a href="../target/aarch64/STNP_gen.html#signed_scaled_offset">Signed offset</a>
  AMED_AARCH64_CCLASS_STP_gen_post_indexed, //!< <a href="../target/aarch64/STP_gen.html#post_indexed">Post-index</a>
  AMED_AARCH64_CCLASS_STP_gen_pre_indexed, //!< <a href="../target/aarch64/STP_gen.html#pre_indexed">Pre-index</a>
  AMED_AARCH64_CCLASS_STP_gen_signed_scaled_offset, //!< <a href="../target/aarch64/STP_gen.html#signed_scaled_offset">Signed offset</a>
  AMED_AARCH64_CCLASS_STR_imm_gen_post_indexed, //!< <a href="../target/aarch64/STR_imm_gen.html#post_indexed">Post-index</a>
  AMED_AARCH64_CCLASS_STR_imm_gen_pre_indexed, //!< <a href="../target/aarch64/STR_imm_gen.html#pre_indexed">Pre-index</a>
  AMED_AARCH64_CCLASS_STR_imm_gen_unsigned_scaled_offset, //!< <a href="../target/aarch64/STR_imm_gen.html#unsigned_scaled_offset">Unsigned offset</a>
  AMED_AARCH64_CCLASS_STR_reg_gen_general, //!< <a href="../target/aarch64/STR_reg_gen.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STRB_32_ldst_immpost, //!< <a href="../target/aarch64/STRB_imm.html#STRB_32_ldst_immpost">Post-index</a>
  AMED_AARCH64_CCLASS_STRB_32_ldst_immpre, //!< <a href="../target/aarch64/STRB_imm.html#STRB_32_ldst_immpre">Pre-index</a>
  AMED_AARCH64_CCLASS_STRB_32_ldst_pos, //!< <a href="../target/aarch64/STRB_imm.html#STRB_32_ldst_pos">Unsigned offset</a>
  AMED_AARCH64_CCLASS_STRB_reg_32, //!< <a href="../target/aarch64/STRB_reg.html#32">32-bit</a>
  AMED_AARCH64_CCLASS_STRH_32_ldst_immpost, //!< <a href="../target/aarch64/STRH_imm.html#STRH_32_ldst_immpost">Post-index</a>
  AMED_AARCH64_CCLASS_STRH_32_ldst_immpre, //!< <a href="../target/aarch64/STRH_imm.html#STRH_32_ldst_immpre">Pre-index</a>
  AMED_AARCH64_CCLASS_STRH_32_ldst_pos, //!< <a href="../target/aarch64/STRH_imm.html#STRH_32_ldst_pos">Unsigned offset</a>
  AMED_AARCH64_CCLASS_STRH_32_ldst_regoff, //!< <a href="../target/aarch64/STRH_reg.html#STRH_32_ldst_regoff">32-bit</a>
  AMED_AARCH64_CCLASS_STTR_base_plus_offset, //!< <a href="../target/aarch64/STTR.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_STTRB_32_ldst_unpriv, //!< <a href="../target/aarch64/STTRB.html#STTRB_32_ldst_unpriv">Unscaled offset</a>
  AMED_AARCH64_CCLASS_STTRH_32_ldst_unpriv, //!< <a href="../target/aarch64/STTRH.html#STTRH_32_ldst_unpriv">Unscaled offset</a>
  AMED_AARCH64_CCLASS_STUR_gen_base_plus_offset, //!< <a href="../target/aarch64/STUR_gen.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_STURB_32_ldst_unscaled, //!< <a href="../target/aarch64/STURB.html#STURB_32_ldst_unscaled">Unscaled offset</a>
  AMED_AARCH64_CCLASS_STURH_32_ldst_unscaled, //!< <a href="../target/aarch64/STURH.html#STURH_32_ldst_unscaled">Unscaled offset</a>
  AMED_AARCH64_CCLASS_STXP_base_register, //!< <a href="../target/aarch64/STXP.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_STXR_base_register, //!< <a href="../target/aarch64/STXR.html#base_register">No offset</a>
  AMED_AARCH64_CCLASS_STXRB_SR32_ldstexcl, //!< <a href="../target/aarch64/STXRB.html#STXRB_SR32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_STXRH_SR32_ldstexcl, //!< <a href="../target/aarch64/STXRH.html#STXRH_SR32_ldstexcl">No offset</a>
  AMED_AARCH64_CCLASS_STZ2G_64Spost_ldsttags, //!< <a href="../target/aarch64/STZ2G.html#STZ2G_64Spost_ldsttags">Post-index</a>
  AMED_AARCH64_CCLASS_STZ2G_64Spre_ldsttags, //!< <a href="../target/aarch64/STZ2G.html#STZ2G_64Spre_ldsttags">Pre-index</a>
  AMED_AARCH64_CCLASS_STZ2G_64Soffset_ldsttags, //!< <a href="../target/aarch64/STZ2G.html#STZ2G_64Soffset_ldsttags">Signed offset</a>
  AMED_AARCH64_CCLASS_STZG_64Spost_ldsttags, //!< <a href="../target/aarch64/STZG.html#STZG_64Spost_ldsttags">Post-index</a>
  AMED_AARCH64_CCLASS_STZG_64Spre_ldsttags, //!< <a href="../target/aarch64/STZG.html#STZG_64Spre_ldsttags">Pre-index</a>
  AMED_AARCH64_CCLASS_STZG_64Soffset_ldsttags, //!< <a href="../target/aarch64/STZG.html#STZG_64Soffset_ldsttags">Signed offset</a>
  AMED_AARCH64_CCLASS_STZGM_64bulk_ldsttags, //!< <a href="../target/aarch64/STZGM.html#STZGM_64bulk_ldsttags">Integer</a>
  AMED_AARCH64_CCLASS_SUB_addsub_ext_no_s, //!< <a href="../target/aarch64/SUB_addsub_ext.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_SUB_addsub_imm_no_s, //!< <a href="../target/aarch64/SUB_addsub_imm.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_SUB_addsub_shift_no_s, //!< <a href="../target/aarch64/SUB_addsub_shift.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_SUBG_64_addsub_immtags, //!< <a href="../target/aarch64/SUBG.html#SUBG_64_addsub_immtags">Integer</a>
  AMED_AARCH64_CCLASS_SUBP_64S_dp_2src, //!< <a href="../target/aarch64/SUBP.html#SUBP_64S_dp_2src">Integer</a>
  AMED_AARCH64_CCLASS_SUBPS_SUBPS_64S_dp_2src, //!< <a href="../target/aarch64/SUBPS.html#SUBPS_64S_dp_2src">Integer</a>
  AMED_AARCH64_CCLASS_SUBS_addsub_ext_s, //!< <a href="../target/aarch64/SUBS_addsub_ext.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_SUBS_addsub_imm_s, //!< <a href="../target/aarch64/SUBS_addsub_imm.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_SUBS_addsub_shift_s, //!< <a href="../target/aarch64/SUBS_addsub_shift.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_SVC_EX_exception, //!< <a href="../target/aarch64/SVC.html#SVC_EX_exception">System</a>
  AMED_AARCH64_CCLASS_SWP_general, //!< <a href="../target/aarch64/SWP.html#general">Integer</a>
  AMED_AARCH64_CCLASS_SWPB_general, //!< <a href="../target/aarch64/SWPB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_SWPH_general, //!< <a href="../target/aarch64/SWPH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_SYS_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/SYS.html#SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_CCLASS_SYSL_RC_systeminstrs, //!< <a href="../target/aarch64/SYSL.html#SYSL_RC_systeminstrs">System</a>
  AMED_AARCH64_CCLASS_TBNZ_only_testbranch, //!< <a href="../target/aarch64/TBNZ.html#TBNZ_only_testbranch">14-bit signed PC-relative branch offset</a>
  AMED_AARCH64_CCLASS_TBZ_only_testbranch, //!< <a href="../target/aarch64/TBZ.html#TBZ_only_testbranch">14-bit signed PC-relative branch offset</a>
  AMED_AARCH64_CCLASS_TCANCEL_EX_exception, //!< <a href="../target/aarch64/TCANCEL.html#TCANCEL_EX_exception">System</a>
  AMED_AARCH64_CCLASS_TCOMMIT_only_barriers, //!< <a href="../target/aarch64/TCOMMIT.html#TCOMMIT_only_barriers">System</a>
  AMED_AARCH64_CCLASS_TSB_HC_hints, //!< <a href="../target/aarch64/TSB.html#TSB_HC_hints">System</a>
  AMED_AARCH64_CCLASS_TSTART_BR_systemresult, //!< <a href="../target/aarch64/TSTART.html#TSTART_BR_systemresult">System</a>
  AMED_AARCH64_CCLASS_TTEST_BR_systemresult, //!< <a href="../target/aarch64/TTEST.html#TTEST_BR_systemresult">System</a>
  AMED_AARCH64_CCLASS_UBFM_zero_fill, //!< <a href="../target/aarch64/UBFM.html#zero_fill">With zeros to left and right</a>
  AMED_AARCH64_CCLASS_UDF_only_perm_undef, //!< <a href="../target/aarch64/UDF_perm_undef.html#UDF_only_perm_undef">Integer</a>
  AMED_AARCH64_CCLASS_UDIV_general, //!< <a href="../target/aarch64/UDIV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_UMADDL_UMADDL_64WA_dp_3src, //!< <a href="../target/aarch64/UMADDL.html#UMADDL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_CCLASS_UMSUBL_UMSUBL_64WA_dp_3src, //!< <a href="../target/aarch64/UMSUBL.html#UMSUBL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_CCLASS_UMULH_64_dp_3src, //!< <a href="../target/aarch64/UMULH.html#UMULH_64_dp_3src">64-bit</a>
  AMED_AARCH64_CCLASS_WFE_HI_hints, //!< <a href="../target/aarch64/WFE.html#WFE_HI_hints">System</a>
  AMED_AARCH64_CCLASS_WFI_HI_hints, //!< <a href="../target/aarch64/WFI.html#WFI_HI_hints">System</a>
  AMED_AARCH64_CCLASS_XAFLAG_M_pstate, //!< <a href="../target/aarch64/XAFLAG.html#XAFLAG_M_pstate">System</a>
  AMED_AARCH64_CCLASS_XPAC_general, //!< <a href="../target/aarch64/XPAC.html#general">Integer</a>
  AMED_AARCH64_CCLASS_XPACLRI_HI_hints, //!< <a href="../target/aarch64/XPAC.html#XPACLRI_HI_hints">System</a>
  AMED_AARCH64_CCLASS_YIELD_HI_hints, //!< <a href="../target/aarch64/YIELD.html#YIELD_HI_hints">System</a>
  AMED_AARCH64_CCLASS_ASR_ASRV_general, //!< <a href="../target/aarch64/ASR_ASRV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_ASR_SBFM_signed_fill, //!< <a href="../target/aarch64/ASR_SBFM.html#signed_fill">With sign replication to left and zeros to right</a>
  AMED_AARCH64_CCLASS_AT_SYS_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/AT_SYS.html#SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_CCLASS_BFC_BFM_nofill, //!< <a href="../target/aarch64/BFC_BFM.html#nofill">Leaving other bits unchanged</a>
  AMED_AARCH64_CCLASS_BFI_BFM_nofill, //!< <a href="../target/aarch64/BFI_BFM.html#nofill">Leaving other bits unchanged</a>
  AMED_AARCH64_CCLASS_BFXIL_BFM_nofill, //!< <a href="../target/aarch64/BFXIL_BFM.html#nofill">Leaving other bits unchanged</a>
  AMED_AARCH64_CCLASS_CFP_SYS_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/CFP_SYS.html#SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_CCLASS_CINC_CSINC_general, //!< <a href="../target/aarch64/CINC_CSINC.html#general">Integer</a>
  AMED_AARCH64_CCLASS_CINV_CSINV_general, //!< <a href="../target/aarch64/CINV_CSINV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_CMN_ADDS_addsub_ext_s, //!< <a href="../target/aarch64/CMN_ADDS_addsub_ext.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_CMN_ADDS_addsub_imm_s, //!< <a href="../target/aarch64/CMN_ADDS_addsub_imm.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_CMN_ADDS_addsub_shift_s, //!< <a href="../target/aarch64/CMN_ADDS_addsub_shift.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_CMP_SUBS_addsub_ext_s, //!< <a href="../target/aarch64/CMP_SUBS_addsub_ext.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_CMP_SUBS_addsub_imm_s, //!< <a href="../target/aarch64/CMP_SUBS_addsub_imm.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_CMP_SUBS_addsub_shift_s, //!< <a href="../target/aarch64/CMP_SUBS_addsub_shift.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_CMPP_SUBPS_SUBPS_64S_dp_2src, //!< <a href="../target/aarch64/CMPP_SUBPS.html#SUBPS_64S_dp_2src">Integer</a>
  AMED_AARCH64_CCLASS_CNEG_CSNEG_general, //!< <a href="../target/aarch64/CNEG_CSNEG.html#general">Integer</a>
  AMED_AARCH64_CCLASS_CPP_SYS_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/CPP_SYS.html#SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_CCLASS_CSET_CSINC_general, //!< <a href="../target/aarch64/CSET_CSINC.html#general">Integer</a>
  AMED_AARCH64_CCLASS_CSETM_CSINV_general, //!< <a href="../target/aarch64/CSETM_CSINV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_DC_SYS_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/DC_SYS.html#SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_CCLASS_DFB_DSB_DSB_BO_barriers, //!< <a href="../target/aarch64/DFB_DSB.html#DSB_BO_barriers">System</a>
  AMED_AARCH64_CCLASS_DVP_SYS_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/DVP_SYS.html#SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_CCLASS_IC_SYS_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/IC_SYS.html#SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_CCLASS_LSL_LSLV_general, //!< <a href="../target/aarch64/LSL_LSLV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LSL_UBFM_zero_fill, //!< <a href="../target/aarch64/LSL_UBFM.html#zero_fill">With zeros to left and right</a>
  AMED_AARCH64_CCLASS_LSR_LSRV_general, //!< <a href="../target/aarch64/LSR_LSRV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_LSR_UBFM_zero_fill, //!< <a href="../target/aarch64/LSR_UBFM.html#zero_fill">With zeros to left and right</a>
  AMED_AARCH64_CCLASS_MNEG_MSUB_general, //!< <a href="../target/aarch64/MNEG_MSUB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_MOV_ADD_addsub_imm_no_s, //!< <a href="../target/aarch64/MOV_ADD_addsub_imm.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_MOV_MOVN_imm18_packed, //!< <a href="../target/aarch64/MOV_MOVN.html#imm18_packed">Immediate packed into 16-bit value and 2-bit shift</a>
  AMED_AARCH64_CCLASS_MOV_MOVZ_imm18_packed, //!< <a href="../target/aarch64/MOV_MOVZ.html#imm18_packed">Immediate packed into 16-bit value and 2-bit shift</a>
  AMED_AARCH64_CCLASS_MOV_ORR_log_imm_no_s, //!< <a href="../target/aarch64/MOV_ORR_log_imm.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_MOV_ORR_log_shift_no_s, //!< <a href="../target/aarch64/MOV_ORR_log_shift.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_MUL_MADD_general, //!< <a href="../target/aarch64/MUL_MADD.html#general">Integer</a>
  AMED_AARCH64_CCLASS_MVN_ORN_log_shift_no_s, //!< <a href="../target/aarch64/MVN_ORN_log_shift.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_NEG_SUB_addsub_shift_no_s, //!< <a href="../target/aarch64/NEG_SUB_addsub_shift.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_NEGS_SUBS_addsub_shift_s, //!< <a href="../target/aarch64/NEGS_SUBS_addsub_shift.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_NGC_SBC_no_s, //!< <a href="../target/aarch64/NGC_SBC.html#no_s">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_NGCS_SBCS_s, //!< <a href="../target/aarch64/NGCS_SBCS.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_REV64_REV_general, //!< <a href="../target/aarch64/REV64_REV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_ROR_EXTR_general, //!< <a href="../target/aarch64/ROR_EXTR.html#general">Integer</a>
  AMED_AARCH64_CCLASS_ROR_RORV_general, //!< <a href="../target/aarch64/ROR_RORV.html#general">Integer</a>
  AMED_AARCH64_CCLASS_SBFIZ_SBFM_signed_fill, //!< <a href="../target/aarch64/SBFIZ_SBFM.html#signed_fill">With sign replication to left and zeros to right</a>
  AMED_AARCH64_CCLASS_SBFX_SBFM_signed_fill, //!< <a href="../target/aarch64/SBFX_SBFM.html#signed_fill">With sign replication to left and zeros to right</a>
  AMED_AARCH64_CCLASS_SMNEGL_SMSUBL_SMSUBL_64WA_dp_3src, //!< <a href="../target/aarch64/SMNEGL_SMSUBL.html#SMSUBL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_CCLASS_SMULL_SMADDL_SMADDL_64WA_dp_3src, //!< <a href="../target/aarch64/SMULL_SMADDL.html#SMADDL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_CCLASS_STADD_LDADD_general, //!< <a href="../target/aarch64/STADD_LDADD.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STADDB_LDADDB_general, //!< <a href="../target/aarch64/STADDB_LDADDB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STADDH_LDADDH_general, //!< <a href="../target/aarch64/STADDH_LDADDH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STCLR_LDCLR_general, //!< <a href="../target/aarch64/STCLR_LDCLR.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STCLRB_LDCLRB_general, //!< <a href="../target/aarch64/STCLRB_LDCLRB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STCLRH_LDCLRH_general, //!< <a href="../target/aarch64/STCLRH_LDCLRH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STEOR_LDEOR_general, //!< <a href="../target/aarch64/STEOR_LDEOR.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STEORB_LDEORB_general, //!< <a href="../target/aarch64/STEORB_LDEORB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STEORH_LDEORH_general, //!< <a href="../target/aarch64/STEORH_LDEORH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STSET_LDSET_general, //!< <a href="../target/aarch64/STSET_LDSET.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STSETB_LDSETB_general, //!< <a href="../target/aarch64/STSETB_LDSETB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STSETH_LDSETH_general, //!< <a href="../target/aarch64/STSETH_LDSETH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STSMAX_LDSMAX_general, //!< <a href="../target/aarch64/STSMAX_LDSMAX.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STSMAXB_LDSMAXB_general, //!< <a href="../target/aarch64/STSMAXB_LDSMAXB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STSMAXH_LDSMAXH_general, //!< <a href="../target/aarch64/STSMAXH_LDSMAXH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STSMIN_LDSMIN_general, //!< <a href="../target/aarch64/STSMIN_LDSMIN.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STSMINB_LDSMINB_general, //!< <a href="../target/aarch64/STSMINB_LDSMINB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STSMINH_LDSMINH_general, //!< <a href="../target/aarch64/STSMINH_LDSMINH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STUMAX_LDUMAX_general, //!< <a href="../target/aarch64/STUMAX_LDUMAX.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STUMAXB_LDUMAXB_general, //!< <a href="../target/aarch64/STUMAXB_LDUMAXB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STUMAXH_LDUMAXH_general, //!< <a href="../target/aarch64/STUMAXH_LDUMAXH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STUMIN_LDUMIN_general, //!< <a href="../target/aarch64/STUMIN_LDUMIN.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STUMINB_LDUMINB_general, //!< <a href="../target/aarch64/STUMINB_LDUMINB.html#general">Integer</a>
  AMED_AARCH64_CCLASS_STUMINH_LDUMINH_general, //!< <a href="../target/aarch64/STUMINH_LDUMINH.html#general">Integer</a>
  AMED_AARCH64_CCLASS_SXTB_SBFM_signed_fill, //!< <a href="../target/aarch64/SXTB_SBFM.html#signed_fill">With sign replication to left and zeros to right</a>
  AMED_AARCH64_CCLASS_SXTH_SBFM_signed_fill, //!< <a href="../target/aarch64/SXTH_SBFM.html#signed_fill">With sign replication to left and zeros to right</a>
  AMED_AARCH64_CCLASS_SXTW_SBFM_signed_fill, //!< <a href="../target/aarch64/SXTW_SBFM.html#signed_fill">With sign replication to left and zeros to right</a>
  AMED_AARCH64_CCLASS_TLBI_SYS_SYS_CR_systeminstrs, //!< <a href="../target/aarch64/TLBI_SYS.html#SYS_CR_systeminstrs">System</a>
  AMED_AARCH64_CCLASS_TST_ANDS_log_imm_s, //!< <a href="../target/aarch64/TST_ANDS_log_imm.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_TST_ANDS_log_shift_s, //!< <a href="../target/aarch64/TST_ANDS_log_shift.html#s">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_UBFIZ_UBFM_zero_fill, //!< <a href="../target/aarch64/UBFIZ_UBFM.html#zero_fill">With zeros to left and right</a>
  AMED_AARCH64_CCLASS_UBFX_UBFM_zero_fill, //!< <a href="../target/aarch64/UBFX_UBFM.html#zero_fill">With zeros to left and right</a>
  AMED_AARCH64_CCLASS_UMNEGL_UMSUBL_UMSUBL_64WA_dp_3src, //!< <a href="../target/aarch64/UMNEGL_UMSUBL.html#UMSUBL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_CCLASS_UMULL_UMADDL_UMADDL_64WA_dp_3src, //!< <a href="../target/aarch64/UMULL_UMADDL.html#UMADDL_64WA_dp_3src">64-bit</a>
  AMED_AARCH64_CCLASS_UXTB_UBFM_zero_fill, //!< <a href="../target/aarch64/UXTB_UBFM.html#zero_fill">With zeros to left and right</a>
  AMED_AARCH64_CCLASS_UXTH_UBFM_zero_fill, //!< <a href="../target/aarch64/UXTH_UBFM.html#zero_fill">With zeros to left and right</a>
  AMED_AARCH64_CCLASS_ABS_asisdmisc_R, //!< <a href="../target/aarch64/ABS_advsimd.html#ABS_asisdmisc_R">Scalar</a>
  AMED_AARCH64_CCLASS_ABS_asimdmisc_R, //!< <a href="../target/aarch64/ABS_advsimd.html#ABS_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_ADD_asisdsame_only, //!< <a href="../target/aarch64/ADD_advsimd.html#ADD_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_ADD_asimdsame_only, //!< <a href="../target/aarch64/ADD_advsimd.html#ADD_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_ADDHN_asimddiff_N, //!< <a href="../target/aarch64/ADDHN_advsimd.html#ADDHN_asimddiff_N">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_ADDP_asisdpair_only, //!< <a href="../target/aarch64/ADDP_advsimd_pair.html#ADDP_asisdpair_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_ADDP_asimdsame_only, //!< <a href="../target/aarch64/ADDP_advsimd_vec.html#ADDP_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_ADDV_asimdall_only, //!< <a href="../target/aarch64/ADDV_advsimd.html#ADDV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_AESD_B_cryptoaes, //!< <a href="../target/aarch64/AESD_advsimd.html#AESD_B_cryptoaes">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_AESE_B_cryptoaes, //!< <a href="../target/aarch64/AESE_advsimd.html#AESE_B_cryptoaes">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_AESIMC_B_cryptoaes, //!< <a href="../target/aarch64/AESIMC_advsimd.html#AESIMC_B_cryptoaes">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_AESMC_B_cryptoaes, //!< <a href="../target/aarch64/AESMC_advsimd.html#AESMC_B_cryptoaes">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_AND_asimdsame_only, //!< <a href="../target/aarch64/AND_advsimd.html#AND_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_BCAX_VVV16_crypto4, //!< <a href="../target/aarch64/BCAX_advsimd.html#BCAX_VVV16_crypto4">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_BFCVT_BS_floatdp1, //!< <a href="../target/aarch64/BFCVT_float.html#BFCVT_BS_floatdp1">Single-precision to BFloat16</a>
  AMED_AARCH64_CCLASS_BFCVTN_asimdmisc_4S, //!< <a href="../target/aarch64/BFCVTN_advsimd.html#BFCVTN_asimdmisc_4S">Vector single-precision and BFloat16</a>
  AMED_AARCH64_CCLASS_BFDOT_asimdelem_E, //!< <a href="../target/aarch64/BFDOT_advsimd_elt.html#BFDOT_asimdelem_E">Vector</a>
  AMED_AARCH64_CCLASS_BFDOT_asimdsame2_D, //!< <a href="../target/aarch64/BFDOT_advsimd_vec.html#BFDOT_asimdsame2_D">Vector</a>
  AMED_AARCH64_CCLASS_BFMLAL_asimdelem_F, //!< <a href="../target/aarch64/BFMLAL_advsimd_elt.html#BFMLAL_asimdelem_F">Vector</a>
  AMED_AARCH64_CCLASS_BFMLAL_asimdsame2_F_, //!< <a href="../target/aarch64/BFMLAL_advsimd_vec.html#BFMLAL_asimdsame2_F_">Vector</a>
  AMED_AARCH64_CCLASS_BFMMLA_asimdsame2_E, //!< <a href="../target/aarch64/BFMMLA_advsimd.html#BFMMLA_asimdsame2_E">Vector</a>
  AMED_AARCH64_CCLASS_BIC_advsimd_imm_shifted_immediate, //!< <a href="../target/aarch64/BIC_advsimd_imm.html#shifted_immediate">Shifted immediate</a>
  AMED_AARCH64_CCLASS_BIC_asimdsame_only, //!< <a href="../target/aarch64/BIC_advsimd_reg.html#BIC_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_BIF_asimdsame_only, //!< <a href="../target/aarch64/BIF_advsimd.html#BIF_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_BIT_asimdsame_only, //!< <a href="../target/aarch64/BIT_advsimd.html#BIT_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_BSL_asimdsame_only, //!< <a href="../target/aarch64/BSL_advsimd.html#BSL_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_CLS_asimdmisc_R, //!< <a href="../target/aarch64/CLS_advsimd.html#CLS_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_CLZ_asimdmisc_R, //!< <a href="../target/aarch64/CLZ_advsimd.html#CLZ_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_CMEQ_asisdsame_only, //!< <a href="../target/aarch64/CMEQ_advsimd_reg.html#CMEQ_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_CMEQ_asimdsame_only, //!< <a href="../target/aarch64/CMEQ_advsimd_reg.html#CMEQ_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_CMEQ_asisdmisc_Z, //!< <a href="../target/aarch64/CMEQ_advsimd_zero.html#CMEQ_asisdmisc_Z">Scalar</a>
  AMED_AARCH64_CCLASS_CMEQ_asimdmisc_Z, //!< <a href="../target/aarch64/CMEQ_advsimd_zero.html#CMEQ_asimdmisc_Z">Vector</a>
  AMED_AARCH64_CCLASS_CMGE_asisdsame_only, //!< <a href="../target/aarch64/CMGE_advsimd_reg.html#CMGE_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_CMGE_asimdsame_only, //!< <a href="../target/aarch64/CMGE_advsimd_reg.html#CMGE_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_CMGE_asisdmisc_Z, //!< <a href="../target/aarch64/CMGE_advsimd_zero.html#CMGE_asisdmisc_Z">Scalar</a>
  AMED_AARCH64_CCLASS_CMGE_asimdmisc_Z, //!< <a href="../target/aarch64/CMGE_advsimd_zero.html#CMGE_asimdmisc_Z">Vector</a>
  AMED_AARCH64_CCLASS_CMGT_asisdsame_only, //!< <a href="../target/aarch64/CMGT_advsimd_reg.html#CMGT_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_CMGT_asimdsame_only, //!< <a href="../target/aarch64/CMGT_advsimd_reg.html#CMGT_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_CMGT_asisdmisc_Z, //!< <a href="../target/aarch64/CMGT_advsimd_zero.html#CMGT_asisdmisc_Z">Scalar</a>
  AMED_AARCH64_CCLASS_CMGT_asimdmisc_Z, //!< <a href="../target/aarch64/CMGT_advsimd_zero.html#CMGT_asimdmisc_Z">Vector</a>
  AMED_AARCH64_CCLASS_CMHI_asisdsame_only, //!< <a href="../target/aarch64/CMHI_advsimd.html#CMHI_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_CMHI_asimdsame_only, //!< <a href="../target/aarch64/CMHI_advsimd.html#CMHI_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_CMHS_asisdsame_only, //!< <a href="../target/aarch64/CMHS_advsimd.html#CMHS_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_CMHS_asimdsame_only, //!< <a href="../target/aarch64/CMHS_advsimd.html#CMHS_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_CMLE_asisdmisc_Z, //!< <a href="../target/aarch64/CMLE_advsimd.html#CMLE_asisdmisc_Z">Scalar</a>
  AMED_AARCH64_CCLASS_CMLE_asimdmisc_Z, //!< <a href="../target/aarch64/CMLE_advsimd.html#CMLE_asimdmisc_Z">Vector</a>
  AMED_AARCH64_CCLASS_CMLT_asisdmisc_Z, //!< <a href="../target/aarch64/CMLT_advsimd.html#CMLT_asisdmisc_Z">Scalar</a>
  AMED_AARCH64_CCLASS_CMLT_asimdmisc_Z, //!< <a href="../target/aarch64/CMLT_advsimd.html#CMLT_asimdmisc_Z">Vector</a>
  AMED_AARCH64_CCLASS_CMTST_asisdsame_only, //!< <a href="../target/aarch64/CMTST_advsimd.html#CMTST_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_CMTST_asimdsame_only, //!< <a href="../target/aarch64/CMTST_advsimd.html#CMTST_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_CNT_asimdmisc_R, //!< <a href="../target/aarch64/CNT_advsimd.html#CNT_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_DUP_advsimd_elt_DUP_asisdone_only, //!< <a href="../target/aarch64/DUP_advsimd_elt.html#DUP_asisdone_only">Scalar</a>
  AMED_AARCH64_CCLASS_DUP_asimdins_DV_v, //!< <a href="../target/aarch64/DUP_advsimd_elt.html#DUP_asimdins_DV_v">Vector</a>
  AMED_AARCH64_CCLASS_DUP_asimdins_DR_r, //!< <a href="../target/aarch64/DUP_advsimd_gen.html#DUP_asimdins_DR_r">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_EOR3_VVV16_crypto4, //!< <a href="../target/aarch64/EOR3_advsimd.html#EOR3_VVV16_crypto4">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_EOR_asimdsame_only, //!< <a href="../target/aarch64/EOR_advsimd.html#EOR_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_EXT_asimdext_only, //!< <a href="../target/aarch64/EXT_advsimd.html#EXT_asimdext_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_FABD_asisdsamefp16_only, //!< <a href="../target/aarch64/FABD_advsimd.html#FABD_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FABD_asisdsame_only, //!< <a href="../target/aarch64/FABD_advsimd.html#FABD_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FABD_asimdsamefp16_only, //!< <a href="../target/aarch64/FABD_advsimd.html#FABD_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_CCLASS_FABD_asimdsame_only, //!< <a href="../target/aarch64/FABD_advsimd.html#FABD_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FABS_asimdmiscfp16_R, //!< <a href="../target/aarch64/FABS_advsimd.html#FABS_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_CCLASS_FABS_asimdmisc_R, //!< <a href="../target/aarch64/FABS_advsimd.html#FABS_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FABS_float_float, //!< <a href="../target/aarch64/FABS_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FACGE_asisdsamefp16_only, //!< <a href="../target/aarch64/FACGE_advsimd.html#FACGE_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FACGE_asisdsame_only, //!< <a href="../target/aarch64/FACGE_advsimd.html#FACGE_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FACGE_asimdsamefp16_only, //!< <a href="../target/aarch64/FACGE_advsimd.html#FACGE_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_CCLASS_FACGE_asimdsame_only, //!< <a href="../target/aarch64/FACGE_advsimd.html#FACGE_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FACGT_asisdsamefp16_only, //!< <a href="../target/aarch64/FACGT_advsimd.html#FACGT_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FACGT_asisdsame_only, //!< <a href="../target/aarch64/FACGT_advsimd.html#FACGT_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FACGT_asimdsamefp16_only, //!< <a href="../target/aarch64/FACGT_advsimd.html#FACGT_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_CCLASS_FACGT_asimdsame_only, //!< <a href="../target/aarch64/FACGT_advsimd.html#FACGT_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FADD_asimdsamefp16_only, //!< <a href="../target/aarch64/FADD_advsimd.html#FADD_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FADD_asimdsame_only, //!< <a href="../target/aarch64/FADD_advsimd.html#FADD_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FADD_float_float, //!< <a href="../target/aarch64/FADD_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FADDP_asisdpair_only_H, //!< <a href="../target/aarch64/FADDP_advsimd_pair.html#FADDP_asisdpair_only_H">Half-precision</a>
  AMED_AARCH64_CCLASS_FADDP_asisdpair_only_SD, //!< <a href="../target/aarch64/FADDP_advsimd_pair.html#FADDP_asisdpair_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FADDP_asimdsamefp16_only, //!< <a href="../target/aarch64/FADDP_advsimd_vec.html#FADDP_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FADDP_asimdsame_only, //!< <a href="../target/aarch64/FADDP_advsimd_vec.html#FADDP_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCADD_asimdsame2_C, //!< <a href="../target/aarch64/FCADD_advsimd_vec.html#FCADD_asimdsame2_C">Vector</a>
  AMED_AARCH64_CCLASS_FCCMP_float_float, //!< <a href="../target/aarch64/FCCMP_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCCMPE_float_float, //!< <a href="../target/aarch64/FCCMPE_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCMEQ_asisdsamefp16_only, //!< <a href="../target/aarch64/FCMEQ_advsimd_reg.html#FCMEQ_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCMEQ_asisdsame_only, //!< <a href="../target/aarch64/FCMEQ_advsimd_reg.html#FCMEQ_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMEQ_asimdsamefp16_only, //!< <a href="../target/aarch64/FCMEQ_advsimd_reg.html#FCMEQ_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCMEQ_asimdsame_only, //!< <a href="../target/aarch64/FCMEQ_advsimd_reg.html#FCMEQ_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMEQ_asisdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMEQ_advsimd_zero.html#FCMEQ_asisdmiscfp16_FZ">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCMEQ_asisdmisc_FZ, //!< <a href="../target/aarch64/FCMEQ_advsimd_zero.html#FCMEQ_asisdmisc_FZ">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMEQ_asimdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMEQ_advsimd_zero.html#FCMEQ_asimdmiscfp16_FZ">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCMEQ_asimdmisc_FZ, //!< <a href="../target/aarch64/FCMEQ_advsimd_zero.html#FCMEQ_asimdmisc_FZ">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMGE_asisdsamefp16_only, //!< <a href="../target/aarch64/FCMGE_advsimd_reg.html#FCMGE_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCMGE_asisdsame_only, //!< <a href="../target/aarch64/FCMGE_advsimd_reg.html#FCMGE_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMGE_asimdsamefp16_only, //!< <a href="../target/aarch64/FCMGE_advsimd_reg.html#FCMGE_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCMGE_asimdsame_only, //!< <a href="../target/aarch64/FCMGE_advsimd_reg.html#FCMGE_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMGE_asisdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMGE_advsimd_zero.html#FCMGE_asisdmiscfp16_FZ">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCMGE_asisdmisc_FZ, //!< <a href="../target/aarch64/FCMGE_advsimd_zero.html#FCMGE_asisdmisc_FZ">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMGE_asimdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMGE_advsimd_zero.html#FCMGE_asimdmiscfp16_FZ">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCMGE_asimdmisc_FZ, //!< <a href="../target/aarch64/FCMGE_advsimd_zero.html#FCMGE_asimdmisc_FZ">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMGT_asisdsamefp16_only, //!< <a href="../target/aarch64/FCMGT_advsimd_reg.html#FCMGT_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCMGT_asisdsame_only, //!< <a href="../target/aarch64/FCMGT_advsimd_reg.html#FCMGT_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMGT_asimdsamefp16_only, //!< <a href="../target/aarch64/FCMGT_advsimd_reg.html#FCMGT_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCMGT_asimdsame_only, //!< <a href="../target/aarch64/FCMGT_advsimd_reg.html#FCMGT_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMGT_asisdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMGT_advsimd_zero.html#FCMGT_asisdmiscfp16_FZ">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCMGT_asisdmisc_FZ, //!< <a href="../target/aarch64/FCMGT_advsimd_zero.html#FCMGT_asisdmisc_FZ">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMGT_asimdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMGT_advsimd_zero.html#FCMGT_asimdmiscfp16_FZ">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCMGT_asimdmisc_FZ, //!< <a href="../target/aarch64/FCMGT_advsimd_zero.html#FCMGT_asimdmisc_FZ">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMLA_advsimd_elt_2reg_element, //!< <a href="../target/aarch64/FCMLA_advsimd_elt.html#2reg_element">Vector</a>
  AMED_AARCH64_CCLASS_FCMLA_asimdsame2_C, //!< <a href="../target/aarch64/FCMLA_advsimd_vec.html#FCMLA_asimdsame2_C">Vector</a>
  AMED_AARCH64_CCLASS_FCMLE_asisdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMLE_advsimd.html#FCMLE_asisdmiscfp16_FZ">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCMLE_asisdmisc_FZ, //!< <a href="../target/aarch64/FCMLE_advsimd.html#FCMLE_asisdmisc_FZ">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMLE_asimdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMLE_advsimd.html#FCMLE_asimdmiscfp16_FZ">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCMLE_asimdmisc_FZ, //!< <a href="../target/aarch64/FCMLE_advsimd.html#FCMLE_asimdmisc_FZ">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMLT_asisdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMLT_advsimd.html#FCMLT_asisdmiscfp16_FZ">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCMLT_asisdmisc_FZ, //!< <a href="../target/aarch64/FCMLT_advsimd.html#FCMLT_asisdmisc_FZ">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMLT_asimdmiscfp16_FZ, //!< <a href="../target/aarch64/FCMLT_advsimd.html#FCMLT_asimdmiscfp16_FZ">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCMLT_asimdmisc_FZ, //!< <a href="../target/aarch64/FCMLT_advsimd.html#FCMLT_asimdmisc_FZ">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCMP_float_float, //!< <a href="../target/aarch64/FCMP_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCMPE_float_float, //!< <a href="../target/aarch64/FCMPE_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCSEL_float_float, //!< <a href="../target/aarch64/FCSEL_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCVT_float_float, //!< <a href="../target/aarch64/FCVT_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCVTAS_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTAS_advsimd.html#FCVTAS_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCVTAS_asisdmisc_R, //!< <a href="../target/aarch64/FCVTAS_advsimd.html#FCVTAS_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTAS_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTAS_advsimd.html#FCVTAS_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCVTAS_asimdmisc_R, //!< <a href="../target/aarch64/FCVTAS_advsimd.html#FCVTAS_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTAS_float_float, //!< <a href="../target/aarch64/FCVTAS_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCVTAU_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTAU_advsimd.html#FCVTAU_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCVTAU_asisdmisc_R, //!< <a href="../target/aarch64/FCVTAU_advsimd.html#FCVTAU_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTAU_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTAU_advsimd.html#FCVTAU_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCVTAU_asimdmisc_R, //!< <a href="../target/aarch64/FCVTAU_advsimd.html#FCVTAU_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTAU_float_float, //!< <a href="../target/aarch64/FCVTAU_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCVTL_asimdmisc_L, //!< <a href="../target/aarch64/FCVTL_advsimd.html#FCVTL_asimdmisc_L">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTMS_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTMS_advsimd.html#FCVTMS_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCVTMS_asisdmisc_R, //!< <a href="../target/aarch64/FCVTMS_advsimd.html#FCVTMS_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTMS_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTMS_advsimd.html#FCVTMS_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCVTMS_asimdmisc_R, //!< <a href="../target/aarch64/FCVTMS_advsimd.html#FCVTMS_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTMS_float_float, //!< <a href="../target/aarch64/FCVTMS_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCVTMU_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTMU_advsimd.html#FCVTMU_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCVTMU_asisdmisc_R, //!< <a href="../target/aarch64/FCVTMU_advsimd.html#FCVTMU_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTMU_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTMU_advsimd.html#FCVTMU_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCVTMU_asimdmisc_R, //!< <a href="../target/aarch64/FCVTMU_advsimd.html#FCVTMU_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTMU_float_float, //!< <a href="../target/aarch64/FCVTMU_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCVTN_asimdmisc_N, //!< <a href="../target/aarch64/FCVTN_advsimd.html#FCVTN_asimdmisc_N">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTNS_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTNS_advsimd.html#FCVTNS_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCVTNS_asisdmisc_R, //!< <a href="../target/aarch64/FCVTNS_advsimd.html#FCVTNS_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTNS_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTNS_advsimd.html#FCVTNS_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCVTNS_asimdmisc_R, //!< <a href="../target/aarch64/FCVTNS_advsimd.html#FCVTNS_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTNS_float_float, //!< <a href="../target/aarch64/FCVTNS_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCVTNU_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTNU_advsimd.html#FCVTNU_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCVTNU_asisdmisc_R, //!< <a href="../target/aarch64/FCVTNU_advsimd.html#FCVTNU_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTNU_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTNU_advsimd.html#FCVTNU_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCVTNU_asimdmisc_R, //!< <a href="../target/aarch64/FCVTNU_advsimd.html#FCVTNU_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTNU_float_float, //!< <a href="../target/aarch64/FCVTNU_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCVTPS_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTPS_advsimd.html#FCVTPS_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCVTPS_asisdmisc_R, //!< <a href="../target/aarch64/FCVTPS_advsimd.html#FCVTPS_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTPS_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTPS_advsimd.html#FCVTPS_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCVTPS_asimdmisc_R, //!< <a href="../target/aarch64/FCVTPS_advsimd.html#FCVTPS_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTPS_float_float, //!< <a href="../target/aarch64/FCVTPS_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCVTPU_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTPU_advsimd.html#FCVTPU_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCVTPU_asisdmisc_R, //!< <a href="../target/aarch64/FCVTPU_advsimd.html#FCVTPU_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTPU_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTPU_advsimd.html#FCVTPU_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCVTPU_asimdmisc_R, //!< <a href="../target/aarch64/FCVTPU_advsimd.html#FCVTPU_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTPU_float_float, //!< <a href="../target/aarch64/FCVTPU_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCVTXN_asisdmisc_N, //!< <a href="../target/aarch64/FCVTXN_advsimd.html#FCVTXN_asisdmisc_N">Scalar</a>
  AMED_AARCH64_CCLASS_FCVTXN_asimdmisc_N, //!< <a href="../target/aarch64/FCVTXN_advsimd.html#FCVTXN_asimdmisc_N">Vector</a>
  AMED_AARCH64_CCLASS_FCVTZS_asisdshf_C, //!< <a href="../target/aarch64/FCVTZS_advsimd_fix.html#FCVTZS_asisdshf_C">Scalar</a>
  AMED_AARCH64_CCLASS_FCVTZS_asimdshf_C, //!< <a href="../target/aarch64/FCVTZS_advsimd_fix.html#FCVTZS_asimdshf_C">Vector</a>
  AMED_AARCH64_CCLASS_FCVTZS_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTZS_advsimd_int.html#FCVTZS_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCVTZS_asisdmisc_R, //!< <a href="../target/aarch64/FCVTZS_advsimd_int.html#FCVTZS_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTZS_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTZS_advsimd_int.html#FCVTZS_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCVTZS_asimdmisc_R, //!< <a href="../target/aarch64/FCVTZS_advsimd_int.html#FCVTZS_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTZS_float_fix_float, //!< <a href="../target/aarch64/FCVTZS_float_fix.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCVTZS_float_int_float, //!< <a href="../target/aarch64/FCVTZS_float_int.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCVTZU_asisdshf_C, //!< <a href="../target/aarch64/FCVTZU_advsimd_fix.html#FCVTZU_asisdshf_C">Scalar</a>
  AMED_AARCH64_CCLASS_FCVTZU_asimdshf_C, //!< <a href="../target/aarch64/FCVTZU_advsimd_fix.html#FCVTZU_asimdshf_C">Vector</a>
  AMED_AARCH64_CCLASS_FCVTZU_asisdmiscfp16_R, //!< <a href="../target/aarch64/FCVTZU_advsimd_int.html#FCVTZU_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FCVTZU_asisdmisc_R, //!< <a href="../target/aarch64/FCVTZU_advsimd_int.html#FCVTZU_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTZU_asimdmiscfp16_R, //!< <a href="../target/aarch64/FCVTZU_advsimd_int.html#FCVTZU_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_FCVTZU_asimdmisc_R, //!< <a href="../target/aarch64/FCVTZU_advsimd_int.html#FCVTZU_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FCVTZU_float_fix_float, //!< <a href="../target/aarch64/FCVTZU_float_fix.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FCVTZU_float_int_float, //!< <a href="../target/aarch64/FCVTZU_float_int.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FDIV_asimdsamefp16_only, //!< <a href="../target/aarch64/FDIV_advsimd.html#FDIV_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FDIV_asimdsame_only, //!< <a href="../target/aarch64/FDIV_advsimd.html#FDIV_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FDIV_float_float, //!< <a href="../target/aarch64/FDIV_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FJCVTZS_32D_float2int, //!< <a href="../target/aarch64/FJCVTZS.html#FJCVTZS_32D_float2int">Double-precision to 32-bit</a>
  AMED_AARCH64_CCLASS_FMADD_float_float, //!< <a href="../target/aarch64/FMADD_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FMAX_asimdsamefp16_only, //!< <a href="../target/aarch64/FMAX_advsimd.html#FMAX_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FMAX_asimdsame_only, //!< <a href="../target/aarch64/FMAX_advsimd.html#FMAX_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMAX_float_float, //!< <a href="../target/aarch64/FMAX_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FMAXNM_asimdsamefp16_only, //!< <a href="../target/aarch64/FMAXNM_advsimd.html#FMAXNM_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FMAXNM_asimdsame_only, //!< <a href="../target/aarch64/FMAXNM_advsimd.html#FMAXNM_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMAXNM_float_float, //!< <a href="../target/aarch64/FMAXNM_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FMAXNMP_asisdpair_only_H, //!< <a href="../target/aarch64/FMAXNMP_advsimd_pair.html#FMAXNMP_asisdpair_only_H">Half-precision</a>
  AMED_AARCH64_CCLASS_FMAXNMP_asisdpair_only_SD, //!< <a href="../target/aarch64/FMAXNMP_advsimd_pair.html#FMAXNMP_asisdpair_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMAXNMP_asimdsamefp16_only, //!< <a href="../target/aarch64/FMAXNMP_advsimd_vec.html#FMAXNMP_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FMAXNMP_asimdsame_only, //!< <a href="../target/aarch64/FMAXNMP_advsimd_vec.html#FMAXNMP_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMAXNMV_asimdall_only_H, //!< <a href="../target/aarch64/FMAXNMV_advsimd.html#FMAXNMV_asimdall_only_H">Half-precision</a>
  AMED_AARCH64_CCLASS_FMAXNMV_asimdall_only_SD, //!< <a href="../target/aarch64/FMAXNMV_advsimd.html#FMAXNMV_asimdall_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMAXP_asisdpair_only_H, //!< <a href="../target/aarch64/FMAXP_advsimd_pair.html#FMAXP_asisdpair_only_H">Half-precision</a>
  AMED_AARCH64_CCLASS_FMAXP_asisdpair_only_SD, //!< <a href="../target/aarch64/FMAXP_advsimd_pair.html#FMAXP_asisdpair_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMAXP_asimdsamefp16_only, //!< <a href="../target/aarch64/FMAXP_advsimd_vec.html#FMAXP_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FMAXP_asimdsame_only, //!< <a href="../target/aarch64/FMAXP_advsimd_vec.html#FMAXP_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMAXV_asimdall_only_H, //!< <a href="../target/aarch64/FMAXV_advsimd.html#FMAXV_asimdall_only_H">Half-precision</a>
  AMED_AARCH64_CCLASS_FMAXV_asimdall_only_SD, //!< <a href="../target/aarch64/FMAXV_advsimd.html#FMAXV_asimdall_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMIN_asimdsamefp16_only, //!< <a href="../target/aarch64/FMIN_advsimd.html#FMIN_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FMIN_asimdsame_only, //!< <a href="../target/aarch64/FMIN_advsimd.html#FMIN_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMIN_float_float, //!< <a href="../target/aarch64/FMIN_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FMINNM_asimdsamefp16_only, //!< <a href="../target/aarch64/FMINNM_advsimd.html#FMINNM_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FMINNM_asimdsame_only, //!< <a href="../target/aarch64/FMINNM_advsimd.html#FMINNM_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMINNM_float_float, //!< <a href="../target/aarch64/FMINNM_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FMINNMP_asisdpair_only_H, //!< <a href="../target/aarch64/FMINNMP_advsimd_pair.html#FMINNMP_asisdpair_only_H">Half-precision</a>
  AMED_AARCH64_CCLASS_FMINNMP_asisdpair_only_SD, //!< <a href="../target/aarch64/FMINNMP_advsimd_pair.html#FMINNMP_asisdpair_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMINNMP_asimdsamefp16_only, //!< <a href="../target/aarch64/FMINNMP_advsimd_vec.html#FMINNMP_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FMINNMP_asimdsame_only, //!< <a href="../target/aarch64/FMINNMP_advsimd_vec.html#FMINNMP_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMINNMV_asimdall_only_H, //!< <a href="../target/aarch64/FMINNMV_advsimd.html#FMINNMV_asimdall_only_H">Half-precision</a>
  AMED_AARCH64_CCLASS_FMINNMV_asimdall_only_SD, //!< <a href="../target/aarch64/FMINNMV_advsimd.html#FMINNMV_asimdall_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMINP_asisdpair_only_H, //!< <a href="../target/aarch64/FMINP_advsimd_pair.html#FMINP_asisdpair_only_H">Half-precision</a>
  AMED_AARCH64_CCLASS_FMINP_asisdpair_only_SD, //!< <a href="../target/aarch64/FMINP_advsimd_pair.html#FMINP_asisdpair_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMINP_asimdsamefp16_only, //!< <a href="../target/aarch64/FMINP_advsimd_vec.html#FMINP_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FMINP_asimdsame_only, //!< <a href="../target/aarch64/FMINP_advsimd_vec.html#FMINP_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMINV_asimdall_only_H, //!< <a href="../target/aarch64/FMINV_advsimd.html#FMINV_asimdall_only_H">Half-precision</a>
  AMED_AARCH64_CCLASS_FMINV_asimdall_only_SD, //!< <a href="../target/aarch64/FMINV_advsimd.html#FMINV_asimdall_only_SD">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMLA_asisdelem_RH_H, //!< <a href="../target/aarch64/FMLA_advsimd_elt.html#FMLA_asisdelem_RH_H">Scalar, half-precision</a>
  AMED_AARCH64_CCLASS_FMLA_asisdelem_R_SD, //!< <a href="../target/aarch64/FMLA_advsimd_elt.html#FMLA_asisdelem_R_SD">Scalar, single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMLA_asimdelem_RH_H, //!< <a href="../target/aarch64/FMLA_advsimd_elt.html#FMLA_asimdelem_RH_H">Vector, half-precision</a>
  AMED_AARCH64_CCLASS_FMLA_asimdelem_R_SD, //!< <a href="../target/aarch64/FMLA_advsimd_elt.html#FMLA_asimdelem_R_SD">Vector, single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMLA_asimdsamefp16_only, //!< <a href="../target/aarch64/FMLA_advsimd_vec.html#FMLA_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FMLA_asimdsame_only, //!< <a href="../target/aarch64/FMLA_advsimd_vec.html#FMLA_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMLAL_asimdelem_LH, //!< <a href="../target/aarch64/FMLAL_advsimd_elt.html#FMLAL_asimdelem_LH">FMLAL</a>
  AMED_AARCH64_CCLASS_FMLAL2_asimdelem_LH, //!< <a href="../target/aarch64/FMLAL_advsimd_elt.html#FMLAL2_asimdelem_LH">FMLAL2</a>
  AMED_AARCH64_CCLASS_FMLAL_asimdsame_F, //!< <a href="../target/aarch64/FMLAL_advsimd_vec.html#FMLAL_asimdsame_F">FMLAL</a>
  AMED_AARCH64_CCLASS_FMLAL2_asimdsame_F, //!< <a href="../target/aarch64/FMLAL_advsimd_vec.html#FMLAL2_asimdsame_F">FMLAL2</a>
  AMED_AARCH64_CCLASS_FMLS_asisdelem_RH_H, //!< <a href="../target/aarch64/FMLS_advsimd_elt.html#FMLS_asisdelem_RH_H">Scalar, half-precision</a>
  AMED_AARCH64_CCLASS_FMLS_asisdelem_R_SD, //!< <a href="../target/aarch64/FMLS_advsimd_elt.html#FMLS_asisdelem_R_SD">Scalar, single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMLS_asimdelem_RH_H, //!< <a href="../target/aarch64/FMLS_advsimd_elt.html#FMLS_asimdelem_RH_H">Vector, half-precision</a>
  AMED_AARCH64_CCLASS_FMLS_asimdelem_R_SD, //!< <a href="../target/aarch64/FMLS_advsimd_elt.html#FMLS_asimdelem_R_SD">Vector, single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMLS_asimdsamefp16_only, //!< <a href="../target/aarch64/FMLS_advsimd_vec.html#FMLS_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FMLS_asimdsame_only, //!< <a href="../target/aarch64/FMLS_advsimd_vec.html#FMLS_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMLSL_asimdelem_LH, //!< <a href="../target/aarch64/FMLSL_advsimd_elt.html#FMLSL_asimdelem_LH">FMLSL</a>
  AMED_AARCH64_CCLASS_FMLSL2_asimdelem_LH, //!< <a href="../target/aarch64/FMLSL_advsimd_elt.html#FMLSL2_asimdelem_LH">FMLSL2</a>
  AMED_AARCH64_CCLASS_FMLSL_asimdsame_F, //!< <a href="../target/aarch64/FMLSL_advsimd_vec.html#FMLSL_asimdsame_F">FMLSL</a>
  AMED_AARCH64_CCLASS_FMLSL2_asimdsame_F, //!< <a href="../target/aarch64/FMLSL_advsimd_vec.html#FMLSL2_asimdsame_F">FMLSL2</a>
  AMED_AARCH64_CCLASS_FMOV_asimdimm_H_h, //!< <a href="../target/aarch64/FMOV_advsimd.html#FMOV_asimdimm_H_h">Half-precision</a>
  AMED_AARCH64_CCLASS_single_and_double, //!< <a href="../target/aarch64/FMOV_advsimd.html#single_and_double">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMOV_float_float, //!< <a href="../target/aarch64/FMOV_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FMOV_float_gen_float, //!< <a href="../target/aarch64/FMOV_float_gen.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_imm8f, //!< <a href="../target/aarch64/FMOV_float_imm.html#imm8f">Floating point constant in 8 bits</a>
  AMED_AARCH64_CCLASS_FMSUB_float_float, //!< <a href="../target/aarch64/FMSUB_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FMUL_asisdelem_RH_H, //!< <a href="../target/aarch64/FMUL_advsimd_elt.html#FMUL_asisdelem_RH_H">Scalar, half-precision</a>
  AMED_AARCH64_CCLASS_FMUL_asisdelem_R_SD, //!< <a href="../target/aarch64/FMUL_advsimd_elt.html#FMUL_asisdelem_R_SD">Scalar, single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMUL_asimdelem_RH_H, //!< <a href="../target/aarch64/FMUL_advsimd_elt.html#FMUL_asimdelem_RH_H">Vector, half-precision</a>
  AMED_AARCH64_CCLASS_FMUL_asimdelem_R_SD, //!< <a href="../target/aarch64/FMUL_advsimd_elt.html#FMUL_asimdelem_R_SD">Vector, single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMUL_asimdsamefp16_only, //!< <a href="../target/aarch64/FMUL_advsimd_vec.html#FMUL_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FMUL_asimdsame_only, //!< <a href="../target/aarch64/FMUL_advsimd_vec.html#FMUL_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMUL_float_float, //!< <a href="../target/aarch64/FMUL_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FMULX_asisdelem_RH_H, //!< <a href="../target/aarch64/FMULX_advsimd_elt.html#FMULX_asisdelem_RH_H">Scalar, half-precision</a>
  AMED_AARCH64_CCLASS_FMULX_asisdelem_R_SD, //!< <a href="../target/aarch64/FMULX_advsimd_elt.html#FMULX_asisdelem_R_SD">Scalar, single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMULX_asimdelem_RH_H, //!< <a href="../target/aarch64/FMULX_advsimd_elt.html#FMULX_asimdelem_RH_H">Vector, half-precision</a>
  AMED_AARCH64_CCLASS_FMULX_asimdelem_R_SD, //!< <a href="../target/aarch64/FMULX_advsimd_elt.html#FMULX_asimdelem_R_SD">Vector, single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMULX_asisdsamefp16_only, //!< <a href="../target/aarch64/FMULX_advsimd_vec.html#FMULX_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FMULX_asisdsame_only, //!< <a href="../target/aarch64/FMULX_advsimd_vec.html#FMULX_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FMULX_asimdsamefp16_only, //!< <a href="../target/aarch64/FMULX_advsimd_vec.html#FMULX_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_CCLASS_FMULX_asimdsame_only, //!< <a href="../target/aarch64/FMULX_advsimd_vec.html#FMULX_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FNEG_asimdmiscfp16_R, //!< <a href="../target/aarch64/FNEG_advsimd.html#FNEG_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_CCLASS_FNEG_asimdmisc_R, //!< <a href="../target/aarch64/FNEG_advsimd.html#FNEG_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FNEG_float_float, //!< <a href="../target/aarch64/FNEG_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FNMADD_float_float, //!< <a href="../target/aarch64/FNMADD_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FNMSUB_float_float, //!< <a href="../target/aarch64/FNMSUB_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FNMUL_float_float, //!< <a href="../target/aarch64/FNMUL_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FRECPE_asisdmiscfp16_R, //!< <a href="../target/aarch64/FRECPE_advsimd.html#FRECPE_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FRECPE_asisdmisc_R, //!< <a href="../target/aarch64/FRECPE_advsimd.html#FRECPE_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRECPE_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRECPE_advsimd.html#FRECPE_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_FRECPE_asimdmisc_R, //!< <a href="../target/aarch64/FRECPE_advsimd.html#FRECPE_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRECPS_asisdsamefp16_only, //!< <a href="../target/aarch64/FRECPS_advsimd.html#FRECPS_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FRECPS_asisdsame_only, //!< <a href="../target/aarch64/FRECPS_advsimd.html#FRECPS_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRECPS_asimdsamefp16_only, //!< <a href="../target/aarch64/FRECPS_advsimd.html#FRECPS_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_CCLASS_FRECPS_asimdsame_only, //!< <a href="../target/aarch64/FRECPS_advsimd.html#FRECPS_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRECPX_asisdmiscfp16_R, //!< <a href="../target/aarch64/FRECPX_advsimd.html#FRECPX_asisdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_CCLASS_FRECPX_asisdmisc_R, //!< <a href="../target/aarch64/FRECPX_advsimd.html#FRECPX_asisdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRINT32X_asimdmisc_R, //!< <a href="../target/aarch64/FRINT32X_advsimd.html#FRINT32X_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRINT32X_float_float, //!< <a href="../target/aarch64/FRINT32X_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FRINT32Z_asimdmisc_R, //!< <a href="../target/aarch64/FRINT32Z_advsimd.html#FRINT32Z_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRINT32Z_float_float, //!< <a href="../target/aarch64/FRINT32Z_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FRINT64X_asimdmisc_R, //!< <a href="../target/aarch64/FRINT64X_advsimd.html#FRINT64X_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRINT64X_float_float, //!< <a href="../target/aarch64/FRINT64X_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FRINT64Z_asimdmisc_R, //!< <a href="../target/aarch64/FRINT64Z_advsimd.html#FRINT64Z_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRINT64Z_float_float, //!< <a href="../target/aarch64/FRINT64Z_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FRINTA_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTA_advsimd.html#FRINTA_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_CCLASS_FRINTA_asimdmisc_R, //!< <a href="../target/aarch64/FRINTA_advsimd.html#FRINTA_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRINTA_float_float, //!< <a href="../target/aarch64/FRINTA_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FRINTI_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTI_advsimd.html#FRINTI_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_CCLASS_FRINTI_asimdmisc_R, //!< <a href="../target/aarch64/FRINTI_advsimd.html#FRINTI_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRINTI_float_float, //!< <a href="../target/aarch64/FRINTI_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FRINTM_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTM_advsimd.html#FRINTM_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_CCLASS_FRINTM_asimdmisc_R, //!< <a href="../target/aarch64/FRINTM_advsimd.html#FRINTM_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRINTM_float_float, //!< <a href="../target/aarch64/FRINTM_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FRINTN_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTN_advsimd.html#FRINTN_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_CCLASS_FRINTN_asimdmisc_R, //!< <a href="../target/aarch64/FRINTN_advsimd.html#FRINTN_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRINTN_float_float, //!< <a href="../target/aarch64/FRINTN_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FRINTP_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTP_advsimd.html#FRINTP_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_CCLASS_FRINTP_asimdmisc_R, //!< <a href="../target/aarch64/FRINTP_advsimd.html#FRINTP_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRINTP_float_float, //!< <a href="../target/aarch64/FRINTP_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FRINTX_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTX_advsimd.html#FRINTX_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_CCLASS_FRINTX_asimdmisc_R, //!< <a href="../target/aarch64/FRINTX_advsimd.html#FRINTX_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRINTX_float_float, //!< <a href="../target/aarch64/FRINTX_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FRINTZ_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRINTZ_advsimd.html#FRINTZ_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_CCLASS_FRINTZ_asimdmisc_R, //!< <a href="../target/aarch64/FRINTZ_advsimd.html#FRINTZ_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRINTZ_float_float, //!< <a href="../target/aarch64/FRINTZ_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FRSQRTE_asisdmiscfp16_R, //!< <a href="../target/aarch64/FRSQRTE_advsimd.html#FRSQRTE_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FRSQRTE_asisdmisc_R, //!< <a href="../target/aarch64/FRSQRTE_advsimd.html#FRSQRTE_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRSQRTE_asimdmiscfp16_R, //!< <a href="../target/aarch64/FRSQRTE_advsimd.html#FRSQRTE_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_FRSQRTE_asimdmisc_R, //!< <a href="../target/aarch64/FRSQRTE_advsimd.html#FRSQRTE_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRSQRTS_asisdsamefp16_only, //!< <a href="../target/aarch64/FRSQRTS_advsimd.html#FRSQRTS_asisdsamefp16_only">Scalar half precision</a>
  AMED_AARCH64_CCLASS_FRSQRTS_asisdsame_only, //!< <a href="../target/aarch64/FRSQRTS_advsimd.html#FRSQRTS_asisdsame_only">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FRSQRTS_asimdsamefp16_only, //!< <a href="../target/aarch64/FRSQRTS_advsimd.html#FRSQRTS_asimdsamefp16_only">Vector half precision</a>
  AMED_AARCH64_CCLASS_FRSQRTS_asimdsame_only, //!< <a href="../target/aarch64/FRSQRTS_advsimd.html#FRSQRTS_asimdsame_only">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FSQRT_asimdmiscfp16_R, //!< <a href="../target/aarch64/FSQRT_advsimd.html#FSQRT_asimdmiscfp16_R">Half-precision</a>
  AMED_AARCH64_CCLASS_FSQRT_asimdmisc_R, //!< <a href="../target/aarch64/FSQRT_advsimd.html#FSQRT_asimdmisc_R">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FSQRT_float_float, //!< <a href="../target/aarch64/FSQRT_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_FSUB_asimdsamefp16_only, //!< <a href="../target/aarch64/FSUB_advsimd.html#FSUB_asimdsamefp16_only">Half-precision</a>
  AMED_AARCH64_CCLASS_FSUB_asimdsame_only, //!< <a href="../target/aarch64/FSUB_advsimd.html#FSUB_asimdsame_only">Single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_FSUB_float_float, //!< <a href="../target/aarch64/FSUB_float.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_INS_advsimd_elt_INS_asimdins_IV_v, //!< <a href="../target/aarch64/INS_advsimd_elt.html#INS_asimdins_IV_v">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_INS_advsimd_gen_INS_asimdins_IR_r, //!< <a href="../target/aarch64/INS_advsimd_gen.html#INS_asimdins_IR_r">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_LD1_advsimd_mult_as_no_post_index, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#as_no_post_index">No offset</a>
  AMED_AARCH64_CCLASS_LD1_advsimd_mult_as_post_index, //!< <a href="../target/aarch64/LD1_advsimd_mult.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_LD1_advsimd_sngl_as_no_post_index, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#as_no_post_index">No offset</a>
  AMED_AARCH64_CCLASS_LD1_advsimd_sngl_as_post_index, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_LD1R_asisdlso_R1, //!< <a href="../target/aarch64/LD1R_advsimd.html#LD1R_asisdlso_R1">No offset</a>
  AMED_AARCH64_CCLASS_LD1R_advsimd_as_post_index, //!< <a href="../target/aarch64/LD1R_advsimd.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_LD2_asisdlse_R2, //!< <a href="../target/aarch64/LD2_advsimd_mult.html#LD2_asisdlse_R2">No offset</a>
  AMED_AARCH64_CCLASS_LD2_advsimd_mult_as_post_index, //!< <a href="../target/aarch64/LD2_advsimd_mult.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_LD2_advsimd_sngl_as_no_post_index, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#as_no_post_index">No offset</a>
  AMED_AARCH64_CCLASS_LD2_advsimd_sngl_as_post_index, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_LD2R_asisdlso_R2, //!< <a href="../target/aarch64/LD2R_advsimd.html#LD2R_asisdlso_R2">No offset</a>
  AMED_AARCH64_CCLASS_LD2R_advsimd_as_post_index, //!< <a href="../target/aarch64/LD2R_advsimd.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_LD3_asisdlse_R3, //!< <a href="../target/aarch64/LD3_advsimd_mult.html#LD3_asisdlse_R3">No offset</a>
  AMED_AARCH64_CCLASS_LD3_advsimd_mult_as_post_index, //!< <a href="../target/aarch64/LD3_advsimd_mult.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_LD3_advsimd_sngl_as_no_post_index, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#as_no_post_index">No offset</a>
  AMED_AARCH64_CCLASS_LD3_advsimd_sngl_as_post_index, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_LD3R_asisdlso_R3, //!< <a href="../target/aarch64/LD3R_advsimd.html#LD3R_asisdlso_R3">No offset</a>
  AMED_AARCH64_CCLASS_LD3R_advsimd_as_post_index, //!< <a href="../target/aarch64/LD3R_advsimd.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_LD4_asisdlse_R4, //!< <a href="../target/aarch64/LD4_advsimd_mult.html#LD4_asisdlse_R4">No offset</a>
  AMED_AARCH64_CCLASS_LD4_advsimd_mult_as_post_index, //!< <a href="../target/aarch64/LD4_advsimd_mult.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_LD4_advsimd_sngl_as_no_post_index, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#as_no_post_index">No offset</a>
  AMED_AARCH64_CCLASS_LD4_advsimd_sngl_as_post_index, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_LD4R_asisdlso_R4, //!< <a href="../target/aarch64/LD4R_advsimd.html#LD4R_asisdlso_R4">No offset</a>
  AMED_AARCH64_CCLASS_LD4R_advsimd_as_post_index, //!< <a href="../target/aarch64/LD4R_advsimd.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_LDNP_fpsimd_signed_scaled_offset, //!< <a href="../target/aarch64/LDNP_fpsimd.html#signed_scaled_offset">Signed offset</a>
  AMED_AARCH64_CCLASS_LDP_fpsimd_post_indexed, //!< <a href="../target/aarch64/LDP_fpsimd.html#post_indexed">Post-index</a>
  AMED_AARCH64_CCLASS_LDP_fpsimd_pre_indexed, //!< <a href="../target/aarch64/LDP_fpsimd.html#pre_indexed">Pre-index</a>
  AMED_AARCH64_CCLASS_LDP_fpsimd_signed_scaled_offset, //!< <a href="../target/aarch64/LDP_fpsimd.html#signed_scaled_offset">Signed offset</a>
  AMED_AARCH64_CCLASS_LDR_imm_fpsimd_post_indexed, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#post_indexed">Post-index</a>
  AMED_AARCH64_CCLASS_LDR_imm_fpsimd_pre_indexed, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#pre_indexed">Pre-index</a>
  AMED_AARCH64_CCLASS_LDR_imm_fpsimd_unsigned_scaled_offset, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html#unsigned_scaled_offset">Unsigned offset</a>
  AMED_AARCH64_CCLASS_LDR_lit_fpsimd_literal, //!< <a href="../target/aarch64/LDR_lit_fpsimd.html#literal">Literal</a>
  AMED_AARCH64_CCLASS_LDR_reg_fpsimd_fpsimd, //!< <a href="../target/aarch64/LDR_reg_fpsimd.html#fpsimd">SIMD&FP registers</a>
  AMED_AARCH64_CCLASS_LDUR_fpsimd_base_plus_offset, //!< <a href="../target/aarch64/LDUR_fpsimd.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_MLA_asimdelem_R, //!< <a href="../target/aarch64/MLA_advsimd_elt.html#MLA_asimdelem_R">Vector</a>
  AMED_AARCH64_CCLASS_MLA_asimdsame_only, //!< <a href="../target/aarch64/MLA_advsimd_vec.html#MLA_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_MLS_asimdelem_R, //!< <a href="../target/aarch64/MLS_advsimd_elt.html#MLS_asimdelem_R">Vector</a>
  AMED_AARCH64_CCLASS_MLS_asimdsame_only, //!< <a href="../target/aarch64/MLS_advsimd_vec.html#MLS_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_MOVI_advsimd_advsimd, //!< <a href="../target/aarch64/MOVI_advsimd.html#advsimd">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_MUL_asimdelem_R, //!< <a href="../target/aarch64/MUL_advsimd_elt.html#MUL_asimdelem_R">Vector</a>
  AMED_AARCH64_CCLASS_MUL_asimdsame_only, //!< <a href="../target/aarch64/MUL_advsimd_vec.html#MUL_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_MVNI_advsimd_advsimd, //!< <a href="../target/aarch64/MVNI_advsimd.html#advsimd">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_NEG_asisdmisc_R, //!< <a href="../target/aarch64/NEG_advsimd.html#NEG_asisdmisc_R">Scalar</a>
  AMED_AARCH64_CCLASS_NEG_asimdmisc_R, //!< <a href="../target/aarch64/NEG_advsimd.html#NEG_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_NOT_advsimd_NOT_asimdmisc_R, //!< <a href="../target/aarch64/NOT_advsimd.html#NOT_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_ORN_asimdsame_only, //!< <a href="../target/aarch64/ORN_advsimd.html#ORN_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_ORR_advsimd_imm_shifted_immediate, //!< <a href="../target/aarch64/ORR_advsimd_imm.html#shifted_immediate">Shifted immediate</a>
  AMED_AARCH64_CCLASS_ORR_advsimd_reg_ORR_asimdsame_only, //!< <a href="../target/aarch64/ORR_advsimd_reg.html#ORR_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_PMUL_asimdsame_only, //!< <a href="../target/aarch64/PMUL_advsimd.html#PMUL_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_PMULL_asimddiff_L, //!< <a href="../target/aarch64/PMULL_advsimd.html#PMULL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_RADDHN_asimddiff_N, //!< <a href="../target/aarch64/RADDHN_advsimd.html#RADDHN_asimddiff_N">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_RAX1_VVV2_cryptosha512_3, //!< <a href="../target/aarch64/RAX1_advsimd.html#RAX1_VVV2_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_RBIT_asimdmisc_R, //!< <a href="../target/aarch64/RBIT_advsimd.html#RBIT_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_REV16_asimdmisc_R, //!< <a href="../target/aarch64/REV16_advsimd.html#REV16_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_REV32_asimdmisc_R, //!< <a href="../target/aarch64/REV32_advsimd.html#REV32_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_REV64_asimdmisc_R, //!< <a href="../target/aarch64/REV64_advsimd.html#REV64_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_RSHRN_asimdshf_N, //!< <a href="../target/aarch64/RSHRN_advsimd.html#RSHRN_asimdshf_N">Vector</a>
  AMED_AARCH64_CCLASS_RSUBHN_asimddiff_N, //!< <a href="../target/aarch64/RSUBHN_advsimd.html#RSUBHN_asimddiff_N">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_SABA_asimdsame_only, //!< <a href="../target/aarch64/SABA_advsimd.html#SABA_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_SABAL_asimddiff_L, //!< <a href="../target/aarch64/SABAL_advsimd.html#SABAL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_SABD_asimdsame_only, //!< <a href="../target/aarch64/SABD_advsimd.html#SABD_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_SABDL_asimddiff_L, //!< <a href="../target/aarch64/SABDL_advsimd.html#SABDL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_SADALP_asimdmisc_P, //!< <a href="../target/aarch64/SADALP_advsimd.html#SADALP_asimdmisc_P">Vector</a>
  AMED_AARCH64_CCLASS_SADDL_asimddiff_L, //!< <a href="../target/aarch64/SADDL_advsimd.html#SADDL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_SADDLP_asimdmisc_P, //!< <a href="../target/aarch64/SADDLP_advsimd.html#SADDLP_asimdmisc_P">Vector</a>
  AMED_AARCH64_CCLASS_SADDLV_asimdall_only, //!< <a href="../target/aarch64/SADDLV_advsimd.html#SADDLV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SADDW_asimddiff_W, //!< <a href="../target/aarch64/SADDW_advsimd.html#SADDW_asimddiff_W">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_SCVTF_asisdshf_C, //!< <a href="../target/aarch64/SCVTF_advsimd_fix.html#SCVTF_asisdshf_C">Scalar</a>
  AMED_AARCH64_CCLASS_SCVTF_asimdshf_C, //!< <a href="../target/aarch64/SCVTF_advsimd_fix.html#SCVTF_asimdshf_C">Vector</a>
  AMED_AARCH64_CCLASS_SCVTF_asisdmiscfp16_R, //!< <a href="../target/aarch64/SCVTF_advsimd_int.html#SCVTF_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_SCVTF_asisdmisc_R, //!< <a href="../target/aarch64/SCVTF_advsimd_int.html#SCVTF_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_SCVTF_asimdmiscfp16_R, //!< <a href="../target/aarch64/SCVTF_advsimd_int.html#SCVTF_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_SCVTF_asimdmisc_R, //!< <a href="../target/aarch64/SCVTF_advsimd_int.html#SCVTF_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_SCVTF_float_fix_float, //!< <a href="../target/aarch64/SCVTF_float_fix.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_SCVTF_float_int_float, //!< <a href="../target/aarch64/SCVTF_float_int.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_SDOT_asimdelem_D, //!< <a href="../target/aarch64/SDOT_advsimd_elt.html#SDOT_asimdelem_D">Vector</a>
  AMED_AARCH64_CCLASS_SDOT_asimdsame2_D, //!< <a href="../target/aarch64/SDOT_advsimd_vec.html#SDOT_asimdsame2_D">Vector</a>
  AMED_AARCH64_CCLASS_SHA1C_QSV_cryptosha3, //!< <a href="../target/aarch64/SHA1C_advsimd.html#SHA1C_QSV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHA1H_SS_cryptosha2, //!< <a href="../target/aarch64/SHA1H_advsimd.html#SHA1H_SS_cryptosha2">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHA1M_QSV_cryptosha3, //!< <a href="../target/aarch64/SHA1M_advsimd.html#SHA1M_QSV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHA1P_QSV_cryptosha3, //!< <a href="../target/aarch64/SHA1P_advsimd.html#SHA1P_QSV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHA1SU0_VVV_cryptosha3, //!< <a href="../target/aarch64/SHA1SU0_advsimd.html#SHA1SU0_VVV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHA1SU1_VV_cryptosha2, //!< <a href="../target/aarch64/SHA1SU1_advsimd.html#SHA1SU1_VV_cryptosha2">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHA256H2_QQV_cryptosha3, //!< <a href="../target/aarch64/SHA256H2_advsimd.html#SHA256H2_QQV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHA256H_QQV_cryptosha3, //!< <a href="../target/aarch64/SHA256H_advsimd.html#SHA256H_QQV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHA256SU0_VV_cryptosha2, //!< <a href="../target/aarch64/SHA256SU0_advsimd.html#SHA256SU0_VV_cryptosha2">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHA256SU1_VVV_cryptosha3, //!< <a href="../target/aarch64/SHA256SU1_advsimd.html#SHA256SU1_VVV_cryptosha3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHA512H2_QQV_cryptosha512_3, //!< <a href="../target/aarch64/SHA512H2_advsimd.html#SHA512H2_QQV_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHA512H_QQV_cryptosha512_3, //!< <a href="../target/aarch64/SHA512H_advsimd.html#SHA512H_QQV_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHA512SU0_VV2_cryptosha512_2, //!< <a href="../target/aarch64/SHA512SU0_advsimd.html#SHA512SU0_VV2_cryptosha512_2">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHA512SU1_VVV2_cryptosha512_3, //!< <a href="../target/aarch64/SHA512SU1_advsimd.html#SHA512SU1_VVV2_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SHADD_asimdsame_only, //!< <a href="../target/aarch64/SHADD_advsimd.html#SHADD_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_SHL_asisdshf_R, //!< <a href="../target/aarch64/SHL_advsimd.html#SHL_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_SHL_asimdshf_R, //!< <a href="../target/aarch64/SHL_advsimd.html#SHL_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_SHLL_asimdmisc_S, //!< <a href="../target/aarch64/SHLL_advsimd.html#SHLL_asimdmisc_S">Vector</a>
  AMED_AARCH64_CCLASS_SHRN_asimdshf_N, //!< <a href="../target/aarch64/SHRN_advsimd.html#SHRN_asimdshf_N">Vector</a>
  AMED_AARCH64_CCLASS_SHSUB_asimdsame_only, //!< <a href="../target/aarch64/SHSUB_advsimd.html#SHSUB_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_SLI_asisdshf_R, //!< <a href="../target/aarch64/SLI_advsimd.html#SLI_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_SLI_asimdshf_R, //!< <a href="../target/aarch64/SLI_advsimd.html#SLI_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_SM3PARTW1_VVV4_cryptosha512_3, //!< <a href="../target/aarch64/SM3PARTW1_advsimd.html#SM3PARTW1_VVV4_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SM3PARTW2_VVV4_cryptosha512_3, //!< <a href="../target/aarch64/SM3PARTW2_advsimd.html#SM3PARTW2_VVV4_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SM3SS1_VVV4_crypto4, //!< <a href="../target/aarch64/SM3SS1_advsimd.html#SM3SS1_VVV4_crypto4">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SM3TT1A_VVV4_crypto3_imm2, //!< <a href="../target/aarch64/SM3TT1A_advsimd.html#SM3TT1A_VVV4_crypto3_imm2">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SM3TT1B_VVV4_crypto3_imm2, //!< <a href="../target/aarch64/SM3TT1B_advsimd.html#SM3TT1B_VVV4_crypto3_imm2">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SM3TT2A_VVV4_crypto3_imm2, //!< <a href="../target/aarch64/SM3TT2A_advsimd.html#SM3TT2A_VVV4_crypto3_imm2">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SM3TT2B_VVV_crypto3_imm2, //!< <a href="../target/aarch64/SM3TT2B_advsimd.html#SM3TT2B_VVV_crypto3_imm2">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SM4E_VV4_cryptosha512_2, //!< <a href="../target/aarch64/SM4E_advsimd.html#SM4E_VV4_cryptosha512_2">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SM4EKEY_VVV4_cryptosha512_3, //!< <a href="../target/aarch64/SM4EKEY_advsimd.html#SM4EKEY_VVV4_cryptosha512_3">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SMAX_asimdsame_only, //!< <a href="../target/aarch64/SMAX_advsimd.html#SMAX_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_SMAXP_asimdsame_only, //!< <a href="../target/aarch64/SMAXP_advsimd.html#SMAXP_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_SMAXV_asimdall_only, //!< <a href="../target/aarch64/SMAXV_advsimd.html#SMAXV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SMIN_asimdsame_only, //!< <a href="../target/aarch64/SMIN_advsimd.html#SMIN_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_SMINP_asimdsame_only, //!< <a href="../target/aarch64/SMINP_advsimd.html#SMINP_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_SMINV_asimdall_only, //!< <a href="../target/aarch64/SMINV_advsimd.html#SMINV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SMLAL_asimdelem_L, //!< <a href="../target/aarch64/SMLAL_advsimd_elt.html#SMLAL_asimdelem_L">Vector</a>
  AMED_AARCH64_CCLASS_SMLAL_asimddiff_L, //!< <a href="../target/aarch64/SMLAL_advsimd_vec.html#SMLAL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_SMLSL_asimdelem_L, //!< <a href="../target/aarch64/SMLSL_advsimd_elt.html#SMLSL_asimdelem_L">Vector</a>
  AMED_AARCH64_CCLASS_SMLSL_asimddiff_L, //!< <a href="../target/aarch64/SMLSL_advsimd_vec.html#SMLSL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_SMMLA_asimdsame2_G, //!< <a href="../target/aarch64/SMMLA_advsimd_vec.html#SMMLA_asimdsame2_G">Vector</a>
  AMED_AARCH64_CCLASS_SMOV_advsimd_advsimd, //!< <a href="../target/aarch64/SMOV_advsimd.html#advsimd">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_SMULL_asimdelem_L, //!< <a href="../target/aarch64/SMULL_advsimd_elt.html#SMULL_asimdelem_L">Vector</a>
  AMED_AARCH64_CCLASS_SMULL_asimddiff_L, //!< <a href="../target/aarch64/SMULL_advsimd_vec.html#SMULL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_SQABS_asisdmisc_R, //!< <a href="../target/aarch64/SQABS_advsimd.html#SQABS_asisdmisc_R">Scalar</a>
  AMED_AARCH64_CCLASS_SQABS_asimdmisc_R, //!< <a href="../target/aarch64/SQABS_advsimd.html#SQABS_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_SQADD_asisdsame_only, //!< <a href="../target/aarch64/SQADD_advsimd.html#SQADD_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_SQADD_asimdsame_only, //!< <a href="../target/aarch64/SQADD_advsimd.html#SQADD_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_SQDMLAL_asisdelem_L, //!< <a href="../target/aarch64/SQDMLAL_advsimd_elt.html#SQDMLAL_asisdelem_L">Scalar</a>
  AMED_AARCH64_CCLASS_SQDMLAL_asimdelem_L, //!< <a href="../target/aarch64/SQDMLAL_advsimd_elt.html#SQDMLAL_asimdelem_L">Vector</a>
  AMED_AARCH64_CCLASS_SQDMLAL_asisddiff_only, //!< <a href="../target/aarch64/SQDMLAL_advsimd_vec.html#SQDMLAL_asisddiff_only">Scalar</a>
  AMED_AARCH64_CCLASS_SQDMLAL_asimddiff_L, //!< <a href="../target/aarch64/SQDMLAL_advsimd_vec.html#SQDMLAL_asimddiff_L">Vector</a>
  AMED_AARCH64_CCLASS_SQDMLSL_asisdelem_L, //!< <a href="../target/aarch64/SQDMLSL_advsimd_elt.html#SQDMLSL_asisdelem_L">Scalar</a>
  AMED_AARCH64_CCLASS_SQDMLSL_asimdelem_L, //!< <a href="../target/aarch64/SQDMLSL_advsimd_elt.html#SQDMLSL_asimdelem_L">Vector</a>
  AMED_AARCH64_CCLASS_SQDMLSL_asisddiff_only, //!< <a href="../target/aarch64/SQDMLSL_advsimd_vec.html#SQDMLSL_asisddiff_only">Scalar</a>
  AMED_AARCH64_CCLASS_SQDMLSL_asimddiff_L, //!< <a href="../target/aarch64/SQDMLSL_advsimd_vec.html#SQDMLSL_asimddiff_L">Vector</a>
  AMED_AARCH64_CCLASS_SQDMULH_asisdelem_R, //!< <a href="../target/aarch64/SQDMULH_advsimd_elt.html#SQDMULH_asisdelem_R">Scalar</a>
  AMED_AARCH64_CCLASS_SQDMULH_asimdelem_R, //!< <a href="../target/aarch64/SQDMULH_advsimd_elt.html#SQDMULH_asimdelem_R">Vector</a>
  AMED_AARCH64_CCLASS_SQDMULH_asisdsame_only, //!< <a href="../target/aarch64/SQDMULH_advsimd_vec.html#SQDMULH_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_SQDMULH_asimdsame_only, //!< <a href="../target/aarch64/SQDMULH_advsimd_vec.html#SQDMULH_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_SQDMULL_asisdelem_L, //!< <a href="../target/aarch64/SQDMULL_advsimd_elt.html#SQDMULL_asisdelem_L">Scalar</a>
  AMED_AARCH64_CCLASS_SQDMULL_asimdelem_L, //!< <a href="../target/aarch64/SQDMULL_advsimd_elt.html#SQDMULL_asimdelem_L">Vector</a>
  AMED_AARCH64_CCLASS_SQDMULL_asisddiff_only, //!< <a href="../target/aarch64/SQDMULL_advsimd_vec.html#SQDMULL_asisddiff_only">Scalar</a>
  AMED_AARCH64_CCLASS_SQDMULL_asimddiff_L, //!< <a href="../target/aarch64/SQDMULL_advsimd_vec.html#SQDMULL_asimddiff_L">Vector</a>
  AMED_AARCH64_CCLASS_SQNEG_asisdmisc_R, //!< <a href="../target/aarch64/SQNEG_advsimd.html#SQNEG_asisdmisc_R">Scalar</a>
  AMED_AARCH64_CCLASS_SQNEG_asimdmisc_R, //!< <a href="../target/aarch64/SQNEG_advsimd.html#SQNEG_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_SQRDMLAH_asisdelem_R, //!< <a href="../target/aarch64/SQRDMLAH_advsimd_elt.html#SQRDMLAH_asisdelem_R">Scalar</a>
  AMED_AARCH64_CCLASS_SQRDMLAH_asimdelem_R, //!< <a href="../target/aarch64/SQRDMLAH_advsimd_elt.html#SQRDMLAH_asimdelem_R">Vector</a>
  AMED_AARCH64_CCLASS_SQRDMLAH_asisdsame2_only, //!< <a href="../target/aarch64/SQRDMLAH_advsimd_vec.html#SQRDMLAH_asisdsame2_only">Scalar</a>
  AMED_AARCH64_CCLASS_SQRDMLAH_asimdsame2_only, //!< <a href="../target/aarch64/SQRDMLAH_advsimd_vec.html#SQRDMLAH_asimdsame2_only">Vector</a>
  AMED_AARCH64_CCLASS_SQRDMLSH_asisdelem_R, //!< <a href="../target/aarch64/SQRDMLSH_advsimd_elt.html#SQRDMLSH_asisdelem_R">Scalar</a>
  AMED_AARCH64_CCLASS_SQRDMLSH_asimdelem_R, //!< <a href="../target/aarch64/SQRDMLSH_advsimd_elt.html#SQRDMLSH_asimdelem_R">Vector</a>
  AMED_AARCH64_CCLASS_SQRDMLSH_asisdsame2_only, //!< <a href="../target/aarch64/SQRDMLSH_advsimd_vec.html#SQRDMLSH_asisdsame2_only">Scalar</a>
  AMED_AARCH64_CCLASS_SQRDMLSH_asimdsame2_only, //!< <a href="../target/aarch64/SQRDMLSH_advsimd_vec.html#SQRDMLSH_asimdsame2_only">Vector</a>
  AMED_AARCH64_CCLASS_SQRDMULH_asisdelem_R, //!< <a href="../target/aarch64/SQRDMULH_advsimd_elt.html#SQRDMULH_asisdelem_R">Scalar</a>
  AMED_AARCH64_CCLASS_SQRDMULH_asimdelem_R, //!< <a href="../target/aarch64/SQRDMULH_advsimd_elt.html#SQRDMULH_asimdelem_R">Vector</a>
  AMED_AARCH64_CCLASS_SQRDMULH_asisdsame_only, //!< <a href="../target/aarch64/SQRDMULH_advsimd_vec.html#SQRDMULH_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_SQRDMULH_asimdsame_only, //!< <a href="../target/aarch64/SQRDMULH_advsimd_vec.html#SQRDMULH_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_SQRSHL_asisdsame_only, //!< <a href="../target/aarch64/SQRSHL_advsimd.html#SQRSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_SQRSHL_asimdsame_only, //!< <a href="../target/aarch64/SQRSHL_advsimd.html#SQRSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_SQRSHRN_asisdshf_N, //!< <a href="../target/aarch64/SQRSHRN_advsimd.html#SQRSHRN_asisdshf_N">Scalar</a>
  AMED_AARCH64_CCLASS_SQRSHRN_asimdshf_N, //!< <a href="../target/aarch64/SQRSHRN_advsimd.html#SQRSHRN_asimdshf_N">Vector</a>
  AMED_AARCH64_CCLASS_SQRSHRUN_asisdshf_N, //!< <a href="../target/aarch64/SQRSHRUN_advsimd.html#SQRSHRUN_asisdshf_N">Scalar</a>
  AMED_AARCH64_CCLASS_SQRSHRUN_asimdshf_N, //!< <a href="../target/aarch64/SQRSHRUN_advsimd.html#SQRSHRUN_asimdshf_N">Vector</a>
  AMED_AARCH64_CCLASS_SQSHL_asisdshf_R, //!< <a href="../target/aarch64/SQSHL_advsimd_imm.html#SQSHL_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_SQSHL_asimdshf_R, //!< <a href="../target/aarch64/SQSHL_advsimd_imm.html#SQSHL_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_SQSHL_asisdsame_only, //!< <a href="../target/aarch64/SQSHL_advsimd_reg.html#SQSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_SQSHL_asimdsame_only, //!< <a href="../target/aarch64/SQSHL_advsimd_reg.html#SQSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_SQSHLU_asisdshf_R, //!< <a href="../target/aarch64/SQSHLU_advsimd.html#SQSHLU_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_SQSHLU_asimdshf_R, //!< <a href="../target/aarch64/SQSHLU_advsimd.html#SQSHLU_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_SQSHRN_asisdshf_N, //!< <a href="../target/aarch64/SQSHRN_advsimd.html#SQSHRN_asisdshf_N">Scalar</a>
  AMED_AARCH64_CCLASS_SQSHRN_asimdshf_N, //!< <a href="../target/aarch64/SQSHRN_advsimd.html#SQSHRN_asimdshf_N">Vector</a>
  AMED_AARCH64_CCLASS_SQSHRUN_asisdshf_N, //!< <a href="../target/aarch64/SQSHRUN_advsimd.html#SQSHRUN_asisdshf_N">Scalar</a>
  AMED_AARCH64_CCLASS_SQSHRUN_asimdshf_N, //!< <a href="../target/aarch64/SQSHRUN_advsimd.html#SQSHRUN_asimdshf_N">Vector</a>
  AMED_AARCH64_CCLASS_SQSUB_asisdsame_only, //!< <a href="../target/aarch64/SQSUB_advsimd.html#SQSUB_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_SQSUB_asimdsame_only, //!< <a href="../target/aarch64/SQSUB_advsimd.html#SQSUB_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_SQXTN_asisdmisc_N, //!< <a href="../target/aarch64/SQXTN_advsimd.html#SQXTN_asisdmisc_N">Scalar</a>
  AMED_AARCH64_CCLASS_SQXTN_asimdmisc_N, //!< <a href="../target/aarch64/SQXTN_advsimd.html#SQXTN_asimdmisc_N">Vector</a>
  AMED_AARCH64_CCLASS_SQXTUN_asisdmisc_N, //!< <a href="../target/aarch64/SQXTUN_advsimd.html#SQXTUN_asisdmisc_N">Scalar</a>
  AMED_AARCH64_CCLASS_SQXTUN_asimdmisc_N, //!< <a href="../target/aarch64/SQXTUN_advsimd.html#SQXTUN_asimdmisc_N">Vector</a>
  AMED_AARCH64_CCLASS_SRHADD_asimdsame_only, //!< <a href="../target/aarch64/SRHADD_advsimd.html#SRHADD_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_SRI_asisdshf_R, //!< <a href="../target/aarch64/SRI_advsimd.html#SRI_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_SRI_asimdshf_R, //!< <a href="../target/aarch64/SRI_advsimd.html#SRI_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_SRSHL_asisdsame_only, //!< <a href="../target/aarch64/SRSHL_advsimd.html#SRSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_SRSHL_asimdsame_only, //!< <a href="../target/aarch64/SRSHL_advsimd.html#SRSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_SRSHR_asisdshf_R, //!< <a href="../target/aarch64/SRSHR_advsimd.html#SRSHR_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_SRSHR_asimdshf_R, //!< <a href="../target/aarch64/SRSHR_advsimd.html#SRSHR_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_SRSRA_asisdshf_R, //!< <a href="../target/aarch64/SRSRA_advsimd.html#SRSRA_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_SRSRA_asimdshf_R, //!< <a href="../target/aarch64/SRSRA_advsimd.html#SRSRA_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_SSHL_asisdsame_only, //!< <a href="../target/aarch64/SSHL_advsimd.html#SSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_SSHL_asimdsame_only, //!< <a href="../target/aarch64/SSHL_advsimd.html#SSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_SSHLL_advsimd_SSHLL_asimdshf_L, //!< <a href="../target/aarch64/SSHLL_advsimd.html#SSHLL_asimdshf_L">Vector</a>
  AMED_AARCH64_CCLASS_SSHR_asisdshf_R, //!< <a href="../target/aarch64/SSHR_advsimd.html#SSHR_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_SSHR_asimdshf_R, //!< <a href="../target/aarch64/SSHR_advsimd.html#SSHR_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_SSRA_asisdshf_R, //!< <a href="../target/aarch64/SSRA_advsimd.html#SSRA_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_SSRA_asimdshf_R, //!< <a href="../target/aarch64/SSRA_advsimd.html#SSRA_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_SSUBL_asimddiff_L, //!< <a href="../target/aarch64/SSUBL_advsimd.html#SSUBL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_SSUBW_asimddiff_W, //!< <a href="../target/aarch64/SSUBW_advsimd.html#SSUBW_asimddiff_W">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_ST1_advsimd_mult_as_no_post_index, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#as_no_post_index">No offset</a>
  AMED_AARCH64_CCLASS_ST1_advsimd_mult_as_post_index, //!< <a href="../target/aarch64/ST1_advsimd_mult.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_ST1_advsimd_sngl_as_no_post_index, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#as_no_post_index">No offset</a>
  AMED_AARCH64_CCLASS_ST1_advsimd_sngl_as_post_index, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_ST2_asisdlse_R2, //!< <a href="../target/aarch64/ST2_advsimd_mult.html#ST2_asisdlse_R2">No offset</a>
  AMED_AARCH64_CCLASS_ST2_advsimd_mult_as_post_index, //!< <a href="../target/aarch64/ST2_advsimd_mult.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_ST2_advsimd_sngl_as_no_post_index, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#as_no_post_index">No offset</a>
  AMED_AARCH64_CCLASS_ST2_advsimd_sngl_as_post_index, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_ST3_asisdlse_R3, //!< <a href="../target/aarch64/ST3_advsimd_mult.html#ST3_asisdlse_R3">No offset</a>
  AMED_AARCH64_CCLASS_ST3_advsimd_mult_as_post_index, //!< <a href="../target/aarch64/ST3_advsimd_mult.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_ST3_advsimd_sngl_as_no_post_index, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#as_no_post_index">No offset</a>
  AMED_AARCH64_CCLASS_ST3_advsimd_sngl_as_post_index, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_ST4_asisdlse_R4, //!< <a href="../target/aarch64/ST4_advsimd_mult.html#ST4_asisdlse_R4">No offset</a>
  AMED_AARCH64_CCLASS_ST4_advsimd_mult_as_post_index, //!< <a href="../target/aarch64/ST4_advsimd_mult.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_ST4_advsimd_sngl_as_no_post_index, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#as_no_post_index">No offset</a>
  AMED_AARCH64_CCLASS_ST4_advsimd_sngl_as_post_index, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html#as_post_index">Post-index</a>
  AMED_AARCH64_CCLASS_STNP_fpsimd_signed_scaled_offset, //!< <a href="../target/aarch64/STNP_fpsimd.html#signed_scaled_offset">Signed offset</a>
  AMED_AARCH64_CCLASS_STP_fpsimd_post_indexed, //!< <a href="../target/aarch64/STP_fpsimd.html#post_indexed">Post-index</a>
  AMED_AARCH64_CCLASS_STP_fpsimd_pre_indexed, //!< <a href="../target/aarch64/STP_fpsimd.html#pre_indexed">Pre-index</a>
  AMED_AARCH64_CCLASS_STP_fpsimd_signed_scaled_offset, //!< <a href="../target/aarch64/STP_fpsimd.html#signed_scaled_offset">Signed offset</a>
  AMED_AARCH64_CCLASS_STR_imm_fpsimd_post_indexed, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#post_indexed">Post-index</a>
  AMED_AARCH64_CCLASS_STR_imm_fpsimd_pre_indexed, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#pre_indexed">Pre-index</a>
  AMED_AARCH64_CCLASS_STR_imm_fpsimd_unsigned_scaled_offset, //!< <a href="../target/aarch64/STR_imm_fpsimd.html#unsigned_scaled_offset">Unsigned offset</a>
  AMED_AARCH64_CCLASS_STR_reg_fpsimd_fpsimd, //!< <a href="../target/aarch64/STR_reg_fpsimd.html#fpsimd">SIMD&FP registers</a>
  AMED_AARCH64_CCLASS_STUR_fpsimd_base_plus_offset, //!< <a href="../target/aarch64/STUR_fpsimd.html#base_plus_offset">Unscaled offset</a>
  AMED_AARCH64_CCLASS_SUB_asisdsame_only, //!< <a href="../target/aarch64/SUB_advsimd.html#SUB_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_SUB_asimdsame_only, //!< <a href="../target/aarch64/SUB_advsimd.html#SUB_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_SUBHN_asimddiff_N, //!< <a href="../target/aarch64/SUBHN_advsimd.html#SUBHN_asimddiff_N">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_SUDOT_asimdelem_D, //!< <a href="../target/aarch64/SUDOT_advsimd_elt.html#SUDOT_asimdelem_D">Vector</a>
  AMED_AARCH64_CCLASS_SUQADD_asisdmisc_R, //!< <a href="../target/aarch64/SUQADD_advsimd.html#SUQADD_asisdmisc_R">Scalar</a>
  AMED_AARCH64_CCLASS_SUQADD_asimdmisc_R, //!< <a href="../target/aarch64/SUQADD_advsimd.html#SUQADD_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_TBL_advsimd_advsimd, //!< <a href="../target/aarch64/TBL_advsimd.html#advsimd">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_TBX_advsimd_advsimd, //!< <a href="../target/aarch64/TBX_advsimd.html#advsimd">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_TRN1_asimdperm_only, //!< <a href="../target/aarch64/TRN1_advsimd.html#TRN1_asimdperm_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_TRN2_asimdperm_only, //!< <a href="../target/aarch64/TRN2_advsimd.html#TRN2_asimdperm_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_UABA_asimdsame_only, //!< <a href="../target/aarch64/UABA_advsimd.html#UABA_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_UABAL_asimddiff_L, //!< <a href="../target/aarch64/UABAL_advsimd.html#UABAL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_UABD_asimdsame_only, //!< <a href="../target/aarch64/UABD_advsimd.html#UABD_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_UABDL_asimddiff_L, //!< <a href="../target/aarch64/UABDL_advsimd.html#UABDL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_UADALP_asimdmisc_P, //!< <a href="../target/aarch64/UADALP_advsimd.html#UADALP_asimdmisc_P">Vector</a>
  AMED_AARCH64_CCLASS_UADDL_asimddiff_L, //!< <a href="../target/aarch64/UADDL_advsimd.html#UADDL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_UADDLP_asimdmisc_P, //!< <a href="../target/aarch64/UADDLP_advsimd.html#UADDLP_asimdmisc_P">Vector</a>
  AMED_AARCH64_CCLASS_UADDLV_asimdall_only, //!< <a href="../target/aarch64/UADDLV_advsimd.html#UADDLV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_UADDW_asimddiff_W, //!< <a href="../target/aarch64/UADDW_advsimd.html#UADDW_asimddiff_W">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_UCVTF_asisdshf_C, //!< <a href="../target/aarch64/UCVTF_advsimd_fix.html#UCVTF_asisdshf_C">Scalar</a>
  AMED_AARCH64_CCLASS_UCVTF_asimdshf_C, //!< <a href="../target/aarch64/UCVTF_advsimd_fix.html#UCVTF_asimdshf_C">Vector</a>
  AMED_AARCH64_CCLASS_UCVTF_asisdmiscfp16_R, //!< <a href="../target/aarch64/UCVTF_advsimd_int.html#UCVTF_asisdmiscfp16_R">Scalar half precision</a>
  AMED_AARCH64_CCLASS_UCVTF_asisdmisc_R, //!< <a href="../target/aarch64/UCVTF_advsimd_int.html#UCVTF_asisdmisc_R">Scalar single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_UCVTF_asimdmiscfp16_R, //!< <a href="../target/aarch64/UCVTF_advsimd_int.html#UCVTF_asimdmiscfp16_R">Vector half precision</a>
  AMED_AARCH64_CCLASS_UCVTF_asimdmisc_R, //!< <a href="../target/aarch64/UCVTF_advsimd_int.html#UCVTF_asimdmisc_R">Vector single-precision and double-precision</a>
  AMED_AARCH64_CCLASS_UCVTF_float_fix_float, //!< <a href="../target/aarch64/UCVTF_float_fix.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_UCVTF_float_int_float, //!< <a href="../target/aarch64/UCVTF_float_int.html#float">Floating-point</a>
  AMED_AARCH64_CCLASS_UDOT_asimdelem_D, //!< <a href="../target/aarch64/UDOT_advsimd_elt.html#UDOT_asimdelem_D">Vector</a>
  AMED_AARCH64_CCLASS_UDOT_asimdsame2_D, //!< <a href="../target/aarch64/UDOT_advsimd_vec.html#UDOT_asimdsame2_D">Vector</a>
  AMED_AARCH64_CCLASS_UHADD_asimdsame_only, //!< <a href="../target/aarch64/UHADD_advsimd.html#UHADD_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_UHSUB_asimdsame_only, //!< <a href="../target/aarch64/UHSUB_advsimd.html#UHSUB_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_UMAX_asimdsame_only, //!< <a href="../target/aarch64/UMAX_advsimd.html#UMAX_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_UMAXP_asimdsame_only, //!< <a href="../target/aarch64/UMAXP_advsimd.html#UMAXP_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_UMAXV_asimdall_only, //!< <a href="../target/aarch64/UMAXV_advsimd.html#UMAXV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_UMIN_asimdsame_only, //!< <a href="../target/aarch64/UMIN_advsimd.html#UMIN_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_UMINP_asimdsame_only, //!< <a href="../target/aarch64/UMINP_advsimd.html#UMINP_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_UMINV_asimdall_only, //!< <a href="../target/aarch64/UMINV_advsimd.html#UMINV_asimdall_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_UMLAL_asimdelem_L, //!< <a href="../target/aarch64/UMLAL_advsimd_elt.html#UMLAL_asimdelem_L">Vector</a>
  AMED_AARCH64_CCLASS_UMLAL_asimddiff_L, //!< <a href="../target/aarch64/UMLAL_advsimd_vec.html#UMLAL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_UMLSL_asimdelem_L, //!< <a href="../target/aarch64/UMLSL_advsimd_elt.html#UMLSL_asimdelem_L">Vector</a>
  AMED_AARCH64_CCLASS_UMLSL_asimddiff_L, //!< <a href="../target/aarch64/UMLSL_advsimd_vec.html#UMLSL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_UMMLA_asimdsame2_G, //!< <a href="../target/aarch64/UMMLA_advsimd_vec.html#UMMLA_asimdsame2_G">Vector</a>
  AMED_AARCH64_CCLASS_UMOV_advsimd_advsimd, //!< <a href="../target/aarch64/UMOV_advsimd.html#advsimd">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_UMULL_asimdelem_L, //!< <a href="../target/aarch64/UMULL_advsimd_elt.html#UMULL_asimdelem_L">Vector</a>
  AMED_AARCH64_CCLASS_UMULL_asimddiff_L, //!< <a href="../target/aarch64/UMULL_advsimd_vec.html#UMULL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_UQADD_asisdsame_only, //!< <a href="../target/aarch64/UQADD_advsimd.html#UQADD_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_UQADD_asimdsame_only, //!< <a href="../target/aarch64/UQADD_advsimd.html#UQADD_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_UQRSHL_asisdsame_only, //!< <a href="../target/aarch64/UQRSHL_advsimd.html#UQRSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_UQRSHL_asimdsame_only, //!< <a href="../target/aarch64/UQRSHL_advsimd.html#UQRSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_UQRSHRN_asisdshf_N, //!< <a href="../target/aarch64/UQRSHRN_advsimd.html#UQRSHRN_asisdshf_N">Scalar</a>
  AMED_AARCH64_CCLASS_UQRSHRN_asimdshf_N, //!< <a href="../target/aarch64/UQRSHRN_advsimd.html#UQRSHRN_asimdshf_N">Vector</a>
  AMED_AARCH64_CCLASS_UQSHL_asisdshf_R, //!< <a href="../target/aarch64/UQSHL_advsimd_imm.html#UQSHL_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_UQSHL_asimdshf_R, //!< <a href="../target/aarch64/UQSHL_advsimd_imm.html#UQSHL_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_UQSHL_asisdsame_only, //!< <a href="../target/aarch64/UQSHL_advsimd_reg.html#UQSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_UQSHL_asimdsame_only, //!< <a href="../target/aarch64/UQSHL_advsimd_reg.html#UQSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_UQSHRN_asisdshf_N, //!< <a href="../target/aarch64/UQSHRN_advsimd.html#UQSHRN_asisdshf_N">Scalar</a>
  AMED_AARCH64_CCLASS_UQSHRN_asimdshf_N, //!< <a href="../target/aarch64/UQSHRN_advsimd.html#UQSHRN_asimdshf_N">Vector</a>
  AMED_AARCH64_CCLASS_UQSUB_asisdsame_only, //!< <a href="../target/aarch64/UQSUB_advsimd.html#UQSUB_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_UQSUB_asimdsame_only, //!< <a href="../target/aarch64/UQSUB_advsimd.html#UQSUB_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_UQXTN_asisdmisc_N, //!< <a href="../target/aarch64/UQXTN_advsimd.html#UQXTN_asisdmisc_N">Scalar</a>
  AMED_AARCH64_CCLASS_UQXTN_asimdmisc_N, //!< <a href="../target/aarch64/UQXTN_advsimd.html#UQXTN_asimdmisc_N">Vector</a>
  AMED_AARCH64_CCLASS_URECPE_asimdmisc_R, //!< <a href="../target/aarch64/URECPE_advsimd.html#URECPE_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_URHADD_asimdsame_only, //!< <a href="../target/aarch64/URHADD_advsimd.html#URHADD_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_URSHL_asisdsame_only, //!< <a href="../target/aarch64/URSHL_advsimd.html#URSHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_URSHL_asimdsame_only, //!< <a href="../target/aarch64/URSHL_advsimd.html#URSHL_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_URSHR_asisdshf_R, //!< <a href="../target/aarch64/URSHR_advsimd.html#URSHR_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_URSHR_asimdshf_R, //!< <a href="../target/aarch64/URSHR_advsimd.html#URSHR_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_URSQRTE_asimdmisc_R, //!< <a href="../target/aarch64/URSQRTE_advsimd.html#URSQRTE_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_URSRA_asisdshf_R, //!< <a href="../target/aarch64/URSRA_advsimd.html#URSRA_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_URSRA_asimdshf_R, //!< <a href="../target/aarch64/URSRA_advsimd.html#URSRA_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_USDOT_asimdelem_D, //!< <a href="../target/aarch64/USDOT_advsimd_elt.html#USDOT_asimdelem_D">Vector</a>
  AMED_AARCH64_CCLASS_USDOT_asimdsame2_D, //!< <a href="../target/aarch64/USDOT_advsimd_vec.html#USDOT_asimdsame2_D">Vector</a>
  AMED_AARCH64_CCLASS_USHL_asisdsame_only, //!< <a href="../target/aarch64/USHL_advsimd.html#USHL_asisdsame_only">Scalar</a>
  AMED_AARCH64_CCLASS_USHL_asimdsame_only, //!< <a href="../target/aarch64/USHL_advsimd.html#USHL_asimdsame_only">Vector</a>
  AMED_AARCH64_CCLASS_USHLL_advsimd_USHLL_asimdshf_L, //!< <a href="../target/aarch64/USHLL_advsimd.html#USHLL_asimdshf_L">Vector</a>
  AMED_AARCH64_CCLASS_USHR_asisdshf_R, //!< <a href="../target/aarch64/USHR_advsimd.html#USHR_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_USHR_asimdshf_R, //!< <a href="../target/aarch64/USHR_advsimd.html#USHR_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_USMMLA_asimdsame2_G, //!< <a href="../target/aarch64/USMMLA_advsimd_vec.html#USMMLA_asimdsame2_G">Vector</a>
  AMED_AARCH64_CCLASS_USQADD_asisdmisc_R, //!< <a href="../target/aarch64/USQADD_advsimd.html#USQADD_asisdmisc_R">Scalar</a>
  AMED_AARCH64_CCLASS_USQADD_asimdmisc_R, //!< <a href="../target/aarch64/USQADD_advsimd.html#USQADD_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_USRA_asisdshf_R, //!< <a href="../target/aarch64/USRA_advsimd.html#USRA_asisdshf_R">Scalar</a>
  AMED_AARCH64_CCLASS_USRA_asimdshf_R, //!< <a href="../target/aarch64/USRA_advsimd.html#USRA_asimdshf_R">Vector</a>
  AMED_AARCH64_CCLASS_USUBL_asimddiff_L, //!< <a href="../target/aarch64/USUBL_advsimd.html#USUBL_asimddiff_L">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_USUBW_asimddiff_W, //!< <a href="../target/aarch64/USUBW_advsimd.html#USUBW_asimddiff_W">Three registers, not all the same type</a>
  AMED_AARCH64_CCLASS_UZP1_asimdperm_only, //!< <a href="../target/aarch64/UZP1_advsimd.html#UZP1_asimdperm_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_UZP2_asimdperm_only, //!< <a href="../target/aarch64/UZP2_advsimd.html#UZP2_asimdperm_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_XAR_VVV2_crypto3_imm6, //!< <a href="../target/aarch64/XAR_advsimd.html#XAR_VVV2_crypto3_imm6">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_XTN_asimdmisc_N, //!< <a href="../target/aarch64/XTN_advsimd.html#XTN_asimdmisc_N">Vector</a>
  AMED_AARCH64_CCLASS_ZIP1_asimdperm_only, //!< <a href="../target/aarch64/ZIP1_advsimd.html#ZIP1_asimdperm_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_ZIP2_asimdperm_only, //!< <a href="../target/aarch64/ZIP2_advsimd.html#ZIP2_asimdperm_only">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_MOV_DUP_advsimd_elt_DUP_asisdone_only, //!< <a href="../target/aarch64/MOV_DUP_advsimd_elt.html#DUP_asisdone_only">Scalar</a>
  AMED_AARCH64_CCLASS_MOV_INS_advsimd_elt_INS_asimdins_IV_v, //!< <a href="../target/aarch64/MOV_INS_advsimd_elt.html#INS_asimdins_IV_v">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_MOV_INS_advsimd_gen_INS_asimdins_IR_r, //!< <a href="../target/aarch64/MOV_INS_advsimd_gen.html#INS_asimdins_IR_r">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_MOV_ORR_advsimd_reg_ORR_asimdsame_only, //!< <a href="../target/aarch64/MOV_ORR_advsimd_reg.html#ORR_asimdsame_only">Three registers of the same type</a>
  AMED_AARCH64_CCLASS_MOV_UMOV_advsimd_advsimd, //!< <a href="../target/aarch64/MOV_UMOV_advsimd.html#advsimd">Advanced SIMD</a>
  AMED_AARCH64_CCLASS_MVN_NOT_advsimd_NOT_asimdmisc_R, //!< <a href="../target/aarch64/MVN_NOT_advsimd.html#NOT_asimdmisc_R">Vector</a>
  AMED_AARCH64_CCLASS_SXTL_SSHLL_advsimd_SSHLL_asimdshf_L, //!< <a href="../target/aarch64/SXTL_SSHLL_advsimd.html#SSHLL_asimdshf_L">Vector</a>
  AMED_AARCH64_CCLASS_UXTL_USHLL_advsimd_USHLL_asimdshf_L, //!< <a href="../target/aarch64/UXTL_USHLL_advsimd.html#USHLL_asimdshf_L">Vector</a>
  AMED_AARCH64_CCLASS_abs_z_p_z_, //!< <a href="../target/aarch64/abs_z_p_z.html#abs_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_adclb_z_zzz_, //!< <a href="../target/aarch64/adclb_z_zzz.html#adclb_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_adclt_z_zzz_, //!< <a href="../target/aarch64/adclt_z_zzz.html#adclt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_add_z_p_zz_, //!< <a href="../target/aarch64/add_z_p_zz.html#add_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_add_z_zi_, //!< <a href="../target/aarch64/add_z_zi.html#add_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_add_z_zz_, //!< <a href="../target/aarch64/add_z_zz.html#add_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_addhnb_z_zz_, //!< <a href="../target/aarch64/addhnb_z_zz.html#addhnb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_addhnt_z_zz_, //!< <a href="../target/aarch64/addhnt_z_zz.html#addhnt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_addp_z_p_zz_, //!< <a href="../target/aarch64/addp_z_p_zz.html#addp_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_addpl_r_ri_, //!< <a href="../target/aarch64/addpl_r_ri.html#addpl_r_ri_">SVE</a>
  AMED_AARCH64_CCLASS_addvl_r_ri_, //!< <a href="../target/aarch64/addvl_r_ri.html#addvl_r_ri_">SVE</a>
  AMED_AARCH64_CCLASS_adr_z_az_sd_same_scaled, //!< <a href="../target/aarch64/adr_z_az.html#adr_z_az_sd_same_scaled">Packed offsets</a>
  AMED_AARCH64_CCLASS_adr_z_az_d_s32_scaled, //!< <a href="../target/aarch64/adr_z_az.html#adr_z_az_d_s32_scaled">Unpacked 32-bit signed offsets</a>
  AMED_AARCH64_CCLASS_adr_z_az_d_u32_scaled, //!< <a href="../target/aarch64/adr_z_az.html#adr_z_az_d_u32_scaled">Unpacked 32-bit unsigned offsets</a>
  AMED_AARCH64_CCLASS_aesd_z_zz_, //!< <a href="../target/aarch64/aesd_z_zz.html#aesd_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_aese_z_zz_, //!< <a href="../target/aarch64/aese_z_zz.html#aese_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_aesimc_z_z_, //!< <a href="../target/aarch64/aesimc_z_z.html#aesimc_z_z_">SVE2</a>
  AMED_AARCH64_CCLASS_aesmc_z_z_, //!< <a href="../target/aarch64/aesmc_z_z.html#aesmc_z_z_">SVE2</a>
  AMED_AARCH64_CCLASS_and_p_p_pp_and_p_p_pp_z, //!< <a href="../target/aarch64/and_p_p_pp.html#and_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_and_p_p_pp_ands_p_p_pp_z, //!< <a href="../target/aarch64/and_p_p_pp.html#ands_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_and_z_p_zz_, //!< <a href="../target/aarch64/and_z_p_zz.html#and_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_and_z_zi_and_z_zi_, //!< <a href="../target/aarch64/and_z_zi.html#and_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_and_z_zz_, //!< <a href="../target/aarch64/and_z_zz.html#and_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_andv_r_p_z_, //!< <a href="../target/aarch64/andv_r_p_z.html#andv_r_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_asr_z_p_zi_, //!< <a href="../target/aarch64/asr_z_p_zi.html#asr_z_p_zi_">SVE</a>
  AMED_AARCH64_CCLASS_asr_z_p_zw_, //!< <a href="../target/aarch64/asr_z_p_zw.html#asr_z_p_zw_">SVE</a>
  AMED_AARCH64_CCLASS_asr_z_p_zz_, //!< <a href="../target/aarch64/asr_z_p_zz.html#asr_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_asr_z_zi_, //!< <a href="../target/aarch64/asr_z_zi.html#asr_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_asr_z_zw_, //!< <a href="../target/aarch64/asr_z_zw.html#asr_z_zw_">SVE</a>
  AMED_AARCH64_CCLASS_asrd_z_p_zi_, //!< <a href="../target/aarch64/asrd_z_p_zi.html#asrd_z_p_zi_">SVE</a>
  AMED_AARCH64_CCLASS_asrr_z_p_zz_, //!< <a href="../target/aarch64/asrr_z_p_zz.html#asrr_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_bcax_z_zzz_, //!< <a href="../target/aarch64/bcax_z_zzz.html#bcax_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_bdep_z_zz_, //!< <a href="../target/aarch64/bdep_z_zz.html#bdep_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_bext_z_zz_, //!< <a href="../target/aarch64/bext_z_zz.html#bext_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_bfcvt_z_p_z_s2bf, //!< <a href="../target/aarch64/bfcvt_z_p_z.html#bfcvt_z_p_z_s2bf">SVE</a>
  AMED_AARCH64_CCLASS_bfcvtnt_z_p_z_s2bf, //!< <a href="../target/aarch64/bfcvtnt_z_p_z.html#bfcvtnt_z_p_z_s2bf">SVE</a>
  AMED_AARCH64_CCLASS_bfdot_z_zzz_, //!< <a href="../target/aarch64/bfdot_z_zzz.html#bfdot_z_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_bfdot_z_zzzi_, //!< <a href="../target/aarch64/bfdot_z_zzzi.html#bfdot_z_zzzi_">SVE</a>
  AMED_AARCH64_CCLASS_bfmlalb_z_zzz_, //!< <a href="../target/aarch64/bfmlalb_z_zzz.html#bfmlalb_z_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_bfmlalb_z_zzzi_, //!< <a href="../target/aarch64/bfmlalb_z_zzzi.html#bfmlalb_z_zzzi_">SVE</a>
  AMED_AARCH64_CCLASS_bfmlalt_z_zzz_, //!< <a href="../target/aarch64/bfmlalt_z_zzz.html#bfmlalt_z_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_bfmlalt_z_zzzi_, //!< <a href="../target/aarch64/bfmlalt_z_zzzi.html#bfmlalt_z_zzzi_">SVE</a>
  AMED_AARCH64_CCLASS_bfmmla_z_zzz_, //!< <a href="../target/aarch64/bfmmla_z_zzz.html#bfmmla_z_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_bgrp_z_zz_, //!< <a href="../target/aarch64/bgrp_z_zz.html#bgrp_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_bic_p_p_pp_z, //!< <a href="../target/aarch64/bic_p_p_pp.html#bic_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_bics_p_p_pp_z, //!< <a href="../target/aarch64/bic_p_p_pp.html#bics_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_bic_z_p_zz_, //!< <a href="../target/aarch64/bic_z_p_zz.html#bic_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_bic_z_zz_, //!< <a href="../target/aarch64/bic_z_zz.html#bic_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_brka_p_p_p_, //!< <a href="../target/aarch64/brka_p_p_p.html#brka_p_p_p_">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_brkas_p_p_p_z, //!< <a href="../target/aarch64/brka_p_p_p.html#brkas_p_p_p_z">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_brkb_p_p_p_, //!< <a href="../target/aarch64/brkb_p_p_p.html#brkb_p_p_p_">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_brkbs_p_p_p_z, //!< <a href="../target/aarch64/brkb_p_p_p.html#brkbs_p_p_p_z">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_brkn_p_p_pp_, //!< <a href="../target/aarch64/brkn_p_p_pp.html#brkn_p_p_pp_">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_brkns_p_p_pp_, //!< <a href="../target/aarch64/brkn_p_p_pp.html#brkns_p_p_pp_">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_brkpa_p_p_pp_, //!< <a href="../target/aarch64/brkpa_p_p_pp.html#brkpa_p_p_pp_">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_brkpas_p_p_pp_, //!< <a href="../target/aarch64/brkpa_p_p_pp.html#brkpas_p_p_pp_">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_brkpb_p_p_pp_, //!< <a href="../target/aarch64/brkpb_p_p_pp.html#brkpb_p_p_pp_">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_brkpbs_p_p_pp_, //!< <a href="../target/aarch64/brkpb_p_p_pp.html#brkpbs_p_p_pp_">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_bsl1n_z_zzz_, //!< <a href="../target/aarch64/bsl1n_z_zzz.html#bsl1n_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_bsl2n_z_zzz_, //!< <a href="../target/aarch64/bsl2n_z_zzz.html#bsl2n_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_bsl_z_zzz_, //!< <a href="../target/aarch64/bsl_z_zzz.html#bsl_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_cadd_z_zz_, //!< <a href="../target/aarch64/cadd_z_zz.html#cadd_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_cdot_z_zzz_, //!< <a href="../target/aarch64/cdot_z_zzz.html#cdot_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_cdot_z_zzzi_s, //!< <a href="../target/aarch64/cdot_z_zzzi.html#cdot_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_cdot_z_zzzi_d, //!< <a href="../target/aarch64/cdot_z_zzzi.html#cdot_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_clasta_r_p_z_, //!< <a href="../target/aarch64/clasta_r_p_z.html#clasta_r_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_clasta_v_p_z_, //!< <a href="../target/aarch64/clasta_v_p_z.html#clasta_v_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_clasta_z_p_zz_, //!< <a href="../target/aarch64/clasta_z_p_zz.html#clasta_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_clastb_r_p_z_, //!< <a href="../target/aarch64/clastb_r_p_z.html#clastb_r_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_clastb_v_p_z_, //!< <a href="../target/aarch64/clastb_v_p_z.html#clastb_v_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_clastb_z_p_zz_, //!< <a href="../target/aarch64/clastb_z_p_zz.html#clastb_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_cls_z_p_z_, //!< <a href="../target/aarch64/cls_z_p_z.html#cls_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_clz_z_p_z_, //!< <a href="../target/aarch64/clz_z_p_z.html#clz_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_cmla_z_zzz_, //!< <a href="../target/aarch64/cmla_z_zzz.html#cmla_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_cmla_z_zzzi_h, //!< <a href="../target/aarch64/cmla_z_zzzi.html#cmla_z_zzzi_h">16-bit</a>
  AMED_AARCH64_CCLASS_cmla_z_zzzi_s, //!< <a href="../target/aarch64/cmla_z_zzzi.html#cmla_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_cmpeq_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmpeq_p_p_zi_">Equal</a>
  AMED_AARCH64_CCLASS_cmpgt_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmpgt_p_p_zi_">Greater than</a>
  AMED_AARCH64_CCLASS_cmpge_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmpge_p_p_zi_">Greater than or equal</a>
  AMED_AARCH64_CCLASS_cmphi_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmphi_p_p_zi_">Higher</a>
  AMED_AARCH64_CCLASS_cmphs_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmphs_p_p_zi_">Higher or same</a>
  AMED_AARCH64_CCLASS_cmplt_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmplt_p_p_zi_">Less than</a>
  AMED_AARCH64_CCLASS_cmple_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmple_p_p_zi_">Less than or equal</a>
  AMED_AARCH64_CCLASS_cmplo_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmplo_p_p_zi_">Lower</a>
  AMED_AARCH64_CCLASS_cmpls_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmpls_p_p_zi_">Lower or same</a>
  AMED_AARCH64_CCLASS_cmpne_p_p_zi_, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html#cmpne_p_p_zi_">Not equal</a>
  AMED_AARCH64_CCLASS_cmpeq_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmpeq_p_p_zw_">Equal</a>
  AMED_AARCH64_CCLASS_cmpgt_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmpgt_p_p_zw_">Greater than</a>
  AMED_AARCH64_CCLASS_cmpge_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmpge_p_p_zw_">Greater than or equal</a>
  AMED_AARCH64_CCLASS_cmphi_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmphi_p_p_zw_">Higher</a>
  AMED_AARCH64_CCLASS_cmphs_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmphs_p_p_zw_">Higher or same</a>
  AMED_AARCH64_CCLASS_cmplt_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmplt_p_p_zw_">Less than</a>
  AMED_AARCH64_CCLASS_cmple_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmple_p_p_zw_">Less than or equal</a>
  AMED_AARCH64_CCLASS_cmplo_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmplo_p_p_zw_">Lower</a>
  AMED_AARCH64_CCLASS_cmpls_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmpls_p_p_zw_">Lower or same</a>
  AMED_AARCH64_CCLASS_cmpne_p_p_zw_, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html#cmpne_p_p_zw_">Not equal</a>
  AMED_AARCH64_CCLASS_cmpeq_p_p_zz_, //!< <a href="../target/aarch64/cmpeq_p_p_zz.html#cmpeq_p_p_zz_">Equal</a>
  AMED_AARCH64_CCLASS_cmpeq_p_p_zz_cmpgt_p_p_zz_, //!< <a href="../target/aarch64/cmpeq_p_p_zz.html#cmpgt_p_p_zz_">Greater than</a>
  AMED_AARCH64_CCLASS_cmpeq_p_p_zz_cmpge_p_p_zz_, //!< <a href="../target/aarch64/cmpeq_p_p_zz.html#cmpge_p_p_zz_">Greater than or equal</a>
  AMED_AARCH64_CCLASS_cmpeq_p_p_zz_cmphi_p_p_zz_, //!< <a href="../target/aarch64/cmpeq_p_p_zz.html#cmphi_p_p_zz_">Higher</a>
  AMED_AARCH64_CCLASS_cmpeq_p_p_zz_cmphs_p_p_zz_, //!< <a href="../target/aarch64/cmpeq_p_p_zz.html#cmphs_p_p_zz_">Higher or same</a>
  AMED_AARCH64_CCLASS_cmpne_p_p_zz_, //!< <a href="../target/aarch64/cmpeq_p_p_zz.html#cmpne_p_p_zz_">Not equal</a>
  AMED_AARCH64_CCLASS_cnot_z_p_z_, //!< <a href="../target/aarch64/cnot_z_p_z.html#cnot_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_cnt_z_p_z_, //!< <a href="../target/aarch64/cnt_z_p_z.html#cnt_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_cntb_r_s_, //!< <a href="../target/aarch64/cntb_r_s.html#cntb_r_s_">Byte</a>
  AMED_AARCH64_CCLASS_cntd_r_s_, //!< <a href="../target/aarch64/cntb_r_s.html#cntd_r_s_">Doubleword</a>
  AMED_AARCH64_CCLASS_cnth_r_s_, //!< <a href="../target/aarch64/cntb_r_s.html#cnth_r_s_">Halfword</a>
  AMED_AARCH64_CCLASS_cntw_r_s_, //!< <a href="../target/aarch64/cntb_r_s.html#cntw_r_s_">Word</a>
  AMED_AARCH64_CCLASS_cntp_r_p_p_, //!< <a href="../target/aarch64/cntp_r_p_p.html#cntp_r_p_p_">SVE</a>
  AMED_AARCH64_CCLASS_compact_z_p_z_, //!< <a href="../target/aarch64/compact_z_p_z.html#compact_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_cpy_z_o_i_cpy_z_o_i_, //!< <a href="../target/aarch64/cpy_z_o_i.html#cpy_z_o_i_">SVE</a>
  AMED_AARCH64_CCLASS_cpy_z_p_i_cpy_z_p_i_, //!< <a href="../target/aarch64/cpy_z_p_i.html#cpy_z_p_i_">SVE</a>
  AMED_AARCH64_CCLASS_cpy_z_p_r_cpy_z_p_r_, //!< <a href="../target/aarch64/cpy_z_p_r.html#cpy_z_p_r_">SVE</a>
  AMED_AARCH64_CCLASS_cpy_z_p_v_cpy_z_p_v_, //!< <a href="../target/aarch64/cpy_z_p_v.html#cpy_z_p_v_">SVE</a>
  AMED_AARCH64_CCLASS_ctermeq_rr_, //!< <a href="../target/aarch64/ctermeq_rr.html#ctermeq_rr_">Equal</a>
  AMED_AARCH64_CCLASS_ctermne_rr_, //!< <a href="../target/aarch64/ctermeq_rr.html#ctermne_rr_">Not equal</a>
  AMED_AARCH64_CCLASS_decb_r_rs_, //!< <a href="../target/aarch64/decb_r_rs.html#decb_r_rs_">Byte</a>
  AMED_AARCH64_CCLASS_decd_r_rs_, //!< <a href="../target/aarch64/decb_r_rs.html#decd_r_rs_">Doubleword</a>
  AMED_AARCH64_CCLASS_dech_r_rs_, //!< <a href="../target/aarch64/decb_r_rs.html#dech_r_rs_">Halfword</a>
  AMED_AARCH64_CCLASS_decw_r_rs_, //!< <a href="../target/aarch64/decb_r_rs.html#decw_r_rs_">Word</a>
  AMED_AARCH64_CCLASS_decd_z_zs_, //!< <a href="../target/aarch64/decd_z_zs.html#decd_z_zs_">Doubleword</a>
  AMED_AARCH64_CCLASS_dech_z_zs_, //!< <a href="../target/aarch64/decd_z_zs.html#dech_z_zs_">Halfword</a>
  AMED_AARCH64_CCLASS_decw_z_zs_, //!< <a href="../target/aarch64/decd_z_zs.html#decw_z_zs_">Word</a>
  AMED_AARCH64_CCLASS_decp_r_p_r_, //!< <a href="../target/aarch64/decp_r_p_r.html#decp_r_p_r_">SVE</a>
  AMED_AARCH64_CCLASS_decp_z_p_z_, //!< <a href="../target/aarch64/decp_z_p_z.html#decp_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_dup_z_i_dup_z_i_, //!< <a href="../target/aarch64/dup_z_i.html#dup_z_i_">SVE</a>
  AMED_AARCH64_CCLASS_dup_z_r_dup_z_r_, //!< <a href="../target/aarch64/dup_z_r.html#dup_z_r_">SVE</a>
  AMED_AARCH64_CCLASS_dup_z_zi_dup_z_zi_, //!< <a href="../target/aarch64/dup_z_zi.html#dup_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_dupm_z_i_dupm_z_i_, //!< <a href="../target/aarch64/dupm_z_i.html#dupm_z_i_">SVE</a>
  AMED_AARCH64_CCLASS_eor3_z_zzz_, //!< <a href="../target/aarch64/eor3_z_zzz.html#eor3_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_eor_p_p_pp_eor_p_p_pp_z, //!< <a href="../target/aarch64/eor_p_p_pp.html#eor_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_eor_p_p_pp_eors_p_p_pp_z, //!< <a href="../target/aarch64/eor_p_p_pp.html#eors_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_eor_z_p_zz_, //!< <a href="../target/aarch64/eor_z_p_zz.html#eor_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_eor_z_zi_eor_z_zi_, //!< <a href="../target/aarch64/eor_z_zi.html#eor_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_eor_z_zz_, //!< <a href="../target/aarch64/eor_z_zz.html#eor_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_eorbt_z_zz_, //!< <a href="../target/aarch64/eorbt_z_zz.html#eorbt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_eortb_z_zz_, //!< <a href="../target/aarch64/eortb_z_zz.html#eortb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_eorv_r_p_z_, //!< <a href="../target/aarch64/eorv_r_p_z.html#eorv_r_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_ext_z_zi_con, //!< <a href="../target/aarch64/ext_z_zi.html#ext_z_zi_con">Constructive</a>
  AMED_AARCH64_CCLASS_ext_z_zi_des, //!< <a href="../target/aarch64/ext_z_zi.html#ext_z_zi_des">Destructive</a>
  AMED_AARCH64_CCLASS_fabd_z_p_zz_, //!< <a href="../target/aarch64/fabd_z_p_zz.html#fabd_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fabs_z_p_z_, //!< <a href="../target/aarch64/fabs_z_p_z.html#fabs_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_facge_p_p_zz_facgt_p_p_zz_, //!< <a href="../target/aarch64/facge_p_p_zz.html#facgt_p_p_zz_">Greater than</a>
  AMED_AARCH64_CCLASS_facge_p_p_zz_facge_p_p_zz_, //!< <a href="../target/aarch64/facge_p_p_zz.html#facge_p_p_zz_">Greater than or equal</a>
  AMED_AARCH64_CCLASS_fadd_z_p_zs_, //!< <a href="../target/aarch64/fadd_z_p_zs.html#fadd_z_p_zs_">SVE</a>
  AMED_AARCH64_CCLASS_fadd_z_p_zz_, //!< <a href="../target/aarch64/fadd_z_p_zz.html#fadd_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fadd_z_zz_, //!< <a href="../target/aarch64/fadd_z_zz.html#fadd_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fadda_v_p_z_, //!< <a href="../target/aarch64/fadda_v_p_z.html#fadda_v_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_faddp_z_p_zz_, //!< <a href="../target/aarch64/faddp_z_p_zz.html#faddp_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_faddv_v_p_z_, //!< <a href="../target/aarch64/faddv_v_p_z.html#faddv_v_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_fcadd_z_p_zz_, //!< <a href="../target/aarch64/fcadd_z_p_zz.html#fcadd_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fcmeq_p_p_z0_, //!< <a href="../target/aarch64/fcmeq_p_p_z0.html#fcmeq_p_p_z0_">Equal</a>
  AMED_AARCH64_CCLASS_fcmgt_p_p_z0_, //!< <a href="../target/aarch64/fcmeq_p_p_z0.html#fcmgt_p_p_z0_">Greater than</a>
  AMED_AARCH64_CCLASS_fcmge_p_p_z0_, //!< <a href="../target/aarch64/fcmeq_p_p_z0.html#fcmge_p_p_z0_">Greater than or equal</a>
  AMED_AARCH64_CCLASS_fcmlt_p_p_z0_, //!< <a href="../target/aarch64/fcmeq_p_p_z0.html#fcmlt_p_p_z0_">Less than</a>
  AMED_AARCH64_CCLASS_fcmle_p_p_z0_, //!< <a href="../target/aarch64/fcmeq_p_p_z0.html#fcmle_p_p_z0_">Less than or equal</a>
  AMED_AARCH64_CCLASS_fcmne_p_p_z0_, //!< <a href="../target/aarch64/fcmeq_p_p_z0.html#fcmne_p_p_z0_">Not equal</a>
  AMED_AARCH64_CCLASS_fcmeq_p_p_zz_, //!< <a href="../target/aarch64/fcmeq_p_p_zz.html#fcmeq_p_p_zz_">Equal</a>
  AMED_AARCH64_CCLASS_fcmeq_p_p_zz_fcmgt_p_p_zz_, //!< <a href="../target/aarch64/fcmeq_p_p_zz.html#fcmgt_p_p_zz_">Greater than</a>
  AMED_AARCH64_CCLASS_fcmeq_p_p_zz_fcmge_p_p_zz_, //!< <a href="../target/aarch64/fcmeq_p_p_zz.html#fcmge_p_p_zz_">Greater than or equal</a>
  AMED_AARCH64_CCLASS_fcmne_p_p_zz_, //!< <a href="../target/aarch64/fcmeq_p_p_zz.html#fcmne_p_p_zz_">Not equal</a>
  AMED_AARCH64_CCLASS_fcmuo_p_p_zz_, //!< <a href="../target/aarch64/fcmeq_p_p_zz.html#fcmuo_p_p_zz_">Unordered</a>
  AMED_AARCH64_CCLASS_fcmla_z_p_zzz_, //!< <a href="../target/aarch64/fcmla_z_p_zzz.html#fcmla_z_p_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_fcmla_z_zzzi_h, //!< <a href="../target/aarch64/fcmla_z_zzzi.html#fcmla_z_zzzi_h">Half-precision</a>
  AMED_AARCH64_CCLASS_fcmla_z_zzzi_s, //!< <a href="../target/aarch64/fcmla_z_zzzi.html#fcmla_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_CCLASS_fcpy_z_p_i_fcpy_z_p_i_, //!< <a href="../target/aarch64/fcpy_z_p_i.html#fcpy_z_p_i_">SVE</a>
  AMED_AARCH64_CCLASS_fcvt_z_p_z_h2s, //!< <a href="../target/aarch64/fcvt_z_p_z.html#fcvt_z_p_z_h2s">Half-precision to single-precision</a>
  AMED_AARCH64_CCLASS_fcvt_z_p_z_h2d, //!< <a href="../target/aarch64/fcvt_z_p_z.html#fcvt_z_p_z_h2d">Half-precision to double-precision</a>
  AMED_AARCH64_CCLASS_fcvt_z_p_z_s2h, //!< <a href="../target/aarch64/fcvt_z_p_z.html#fcvt_z_p_z_s2h">Single-precision to half-precision</a>
  AMED_AARCH64_CCLASS_fcvt_z_p_z_s2d, //!< <a href="../target/aarch64/fcvt_z_p_z.html#fcvt_z_p_z_s2d">Single-precision to double-precision</a>
  AMED_AARCH64_CCLASS_fcvt_z_p_z_d2h, //!< <a href="../target/aarch64/fcvt_z_p_z.html#fcvt_z_p_z_d2h">Double-precision to half-precision</a>
  AMED_AARCH64_CCLASS_fcvt_z_p_z_d2s, //!< <a href="../target/aarch64/fcvt_z_p_z.html#fcvt_z_p_z_d2s">Double-precision to single-precision</a>
  AMED_AARCH64_CCLASS_fcvtlt_z_p_z_h2s, //!< <a href="../target/aarch64/fcvtlt_z_p_z.html#fcvtlt_z_p_z_h2s">Half-precision to single-precision</a>
  AMED_AARCH64_CCLASS_fcvtlt_z_p_z_s2d, //!< <a href="../target/aarch64/fcvtlt_z_p_z.html#fcvtlt_z_p_z_s2d">Single-precision to double-precision</a>
  AMED_AARCH64_CCLASS_fcvtnt_z_p_z_s2h, //!< <a href="../target/aarch64/fcvtnt_z_p_z.html#fcvtnt_z_p_z_s2h">Single-precision to half-precision</a>
  AMED_AARCH64_CCLASS_fcvtnt_z_p_z_d2s, //!< <a href="../target/aarch64/fcvtnt_z_p_z.html#fcvtnt_z_p_z_d2s">Double-precision to single-precision</a>
  AMED_AARCH64_CCLASS_fcvtx_z_p_z_d2s, //!< <a href="../target/aarch64/fcvtx_z_p_z.html#fcvtx_z_p_z_d2s">Double-precision to single-precision</a>
  AMED_AARCH64_CCLASS_fcvtxnt_z_p_z_d2s, //!< <a href="../target/aarch64/fcvtxnt_z_p_z.html#fcvtxnt_z_p_z_d2s">Double-precision to single-precision</a>
  AMED_AARCH64_CCLASS_fcvtzs_z_p_z_fp162h, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_fp162h">Half-precision to 16-bit</a>
  AMED_AARCH64_CCLASS_fcvtzs_z_p_z_fp162w, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_fp162w">Half-precision to 32-bit</a>
  AMED_AARCH64_CCLASS_fcvtzs_z_p_z_fp162x, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_fp162x">Half-precision to 64-bit</a>
  AMED_AARCH64_CCLASS_fcvtzs_z_p_z_s2w, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_s2w">Single-precision to 32-bit</a>
  AMED_AARCH64_CCLASS_fcvtzs_z_p_z_s2x, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_s2x">Single-precision to 64-bit</a>
  AMED_AARCH64_CCLASS_fcvtzs_z_p_z_d2w, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_d2w">Double-precision to 32-bit</a>
  AMED_AARCH64_CCLASS_fcvtzs_z_p_z_d2x, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html#fcvtzs_z_p_z_d2x">Double-precision to 64-bit</a>
  AMED_AARCH64_CCLASS_fcvtzu_z_p_z_fp162h, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_fp162h">Half-precision to 16-bit</a>
  AMED_AARCH64_CCLASS_fcvtzu_z_p_z_fp162w, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_fp162w">Half-precision to 32-bit</a>
  AMED_AARCH64_CCLASS_fcvtzu_z_p_z_fp162x, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_fp162x">Half-precision to 64-bit</a>
  AMED_AARCH64_CCLASS_fcvtzu_z_p_z_s2w, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_s2w">Single-precision to 32-bit</a>
  AMED_AARCH64_CCLASS_fcvtzu_z_p_z_s2x, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_s2x">Single-precision to 64-bit</a>
  AMED_AARCH64_CCLASS_fcvtzu_z_p_z_d2w, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_d2w">Double-precision to 32-bit</a>
  AMED_AARCH64_CCLASS_fcvtzu_z_p_z_d2x, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html#fcvtzu_z_p_z_d2x">Double-precision to 64-bit</a>
  AMED_AARCH64_CCLASS_fdiv_z_p_zz_, //!< <a href="../target/aarch64/fdiv_z_p_zz.html#fdiv_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fdivr_z_p_zz_, //!< <a href="../target/aarch64/fdivr_z_p_zz.html#fdivr_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fdup_z_i_fdup_z_i_, //!< <a href="../target/aarch64/fdup_z_i.html#fdup_z_i_">SVE</a>
  AMED_AARCH64_CCLASS_fexpa_z_z_, //!< <a href="../target/aarch64/fexpa_z_z.html#fexpa_z_z_">SVE</a>
  AMED_AARCH64_CCLASS_flogb_z_p_z_, //!< <a href="../target/aarch64/flogb_z_p_z.html#flogb_z_p_z_">SVE2</a>
  AMED_AARCH64_CCLASS_fmad_z_p_zzz_, //!< <a href="../target/aarch64/fmad_z_p_zzz.html#fmad_z_p_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_fmax_z_p_zs_, //!< <a href="../target/aarch64/fmax_z_p_zs.html#fmax_z_p_zs_">SVE</a>
  AMED_AARCH64_CCLASS_fmax_z_p_zz_, //!< <a href="../target/aarch64/fmax_z_p_zz.html#fmax_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fmaxnm_z_p_zs_, //!< <a href="../target/aarch64/fmaxnm_z_p_zs.html#fmaxnm_z_p_zs_">SVE</a>
  AMED_AARCH64_CCLASS_fmaxnm_z_p_zz_, //!< <a href="../target/aarch64/fmaxnm_z_p_zz.html#fmaxnm_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fmaxnmp_z_p_zz_, //!< <a href="../target/aarch64/fmaxnmp_z_p_zz.html#fmaxnmp_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_fmaxnmv_v_p_z_, //!< <a href="../target/aarch64/fmaxnmv_v_p_z.html#fmaxnmv_v_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_fmaxp_z_p_zz_, //!< <a href="../target/aarch64/fmaxp_z_p_zz.html#fmaxp_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_fmaxv_v_p_z_, //!< <a href="../target/aarch64/fmaxv_v_p_z.html#fmaxv_v_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_fmin_z_p_zs_, //!< <a href="../target/aarch64/fmin_z_p_zs.html#fmin_z_p_zs_">SVE</a>
  AMED_AARCH64_CCLASS_fmin_z_p_zz_, //!< <a href="../target/aarch64/fmin_z_p_zz.html#fmin_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fminnm_z_p_zs_, //!< <a href="../target/aarch64/fminnm_z_p_zs.html#fminnm_z_p_zs_">SVE</a>
  AMED_AARCH64_CCLASS_fminnm_z_p_zz_, //!< <a href="../target/aarch64/fminnm_z_p_zz.html#fminnm_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fminnmp_z_p_zz_, //!< <a href="../target/aarch64/fminnmp_z_p_zz.html#fminnmp_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_fminnmv_v_p_z_, //!< <a href="../target/aarch64/fminnmv_v_p_z.html#fminnmv_v_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_fminp_z_p_zz_, //!< <a href="../target/aarch64/fminp_z_p_zz.html#fminp_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_fminv_v_p_z_, //!< <a href="../target/aarch64/fminv_v_p_z.html#fminv_v_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_fmla_z_p_zzz_, //!< <a href="../target/aarch64/fmla_z_p_zzz.html#fmla_z_p_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_fmla_z_zzzi_h, //!< <a href="../target/aarch64/fmla_z_zzzi.html#fmla_z_zzzi_h">Half-precision</a>
  AMED_AARCH64_CCLASS_fmla_z_zzzi_s, //!< <a href="../target/aarch64/fmla_z_zzzi.html#fmla_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_CCLASS_fmla_z_zzzi_d, //!< <a href="../target/aarch64/fmla_z_zzzi.html#fmla_z_zzzi_d">Double-precision</a>
  AMED_AARCH64_CCLASS_fmlalb_z_zzz_, //!< <a href="../target/aarch64/fmlalb_z_zzz.html#fmlalb_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_fmlalb_z_zzzi_s, //!< <a href="../target/aarch64/fmlalb_z_zzzi.html#fmlalb_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_CCLASS_fmlalt_z_zzz_, //!< <a href="../target/aarch64/fmlalt_z_zzz.html#fmlalt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_fmlalt_z_zzzi_s, //!< <a href="../target/aarch64/fmlalt_z_zzzi.html#fmlalt_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_CCLASS_fmls_z_p_zzz_, //!< <a href="../target/aarch64/fmls_z_p_zzz.html#fmls_z_p_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_fmls_z_zzzi_h, //!< <a href="../target/aarch64/fmls_z_zzzi.html#fmls_z_zzzi_h">Half-precision</a>
  AMED_AARCH64_CCLASS_fmls_z_zzzi_s, //!< <a href="../target/aarch64/fmls_z_zzzi.html#fmls_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_CCLASS_fmls_z_zzzi_d, //!< <a href="../target/aarch64/fmls_z_zzzi.html#fmls_z_zzzi_d">Double-precision</a>
  AMED_AARCH64_CCLASS_fmlslb_z_zzz_, //!< <a href="../target/aarch64/fmlslb_z_zzz.html#fmlslb_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_fmlslb_z_zzzi_s, //!< <a href="../target/aarch64/fmlslb_z_zzzi.html#fmlslb_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_CCLASS_fmlslt_z_zzz_, //!< <a href="../target/aarch64/fmlslt_z_zzz.html#fmlslt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_fmlslt_z_zzzi_s, //!< <a href="../target/aarch64/fmlslt_z_zzzi.html#fmlslt_z_zzzi_s">Single-precision</a>
  AMED_AARCH64_CCLASS_fmmla_z_zzz_s, //!< <a href="../target/aarch64/fmmla_z_zzz.html#fmmla_z_zzz_s">32-bit element</a>
  AMED_AARCH64_CCLASS_fmmla_z_zzz_d, //!< <a href="../target/aarch64/fmmla_z_zzz.html#fmmla_z_zzz_d">64-bit element</a>
  AMED_AARCH64_CCLASS_fmsb_z_p_zzz_, //!< <a href="../target/aarch64/fmsb_z_p_zzz.html#fmsb_z_p_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_fmul_z_p_zs_, //!< <a href="../target/aarch64/fmul_z_p_zs.html#fmul_z_p_zs_">SVE</a>
  AMED_AARCH64_CCLASS_fmul_z_p_zz_, //!< <a href="../target/aarch64/fmul_z_p_zz.html#fmul_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fmul_z_zz_, //!< <a href="../target/aarch64/fmul_z_zz.html#fmul_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fmul_z_zzi_h, //!< <a href="../target/aarch64/fmul_z_zzi.html#fmul_z_zzi_h">Half-precision</a>
  AMED_AARCH64_CCLASS_fmul_z_zzi_s, //!< <a href="../target/aarch64/fmul_z_zzi.html#fmul_z_zzi_s">Single-precision</a>
  AMED_AARCH64_CCLASS_fmul_z_zzi_d, //!< <a href="../target/aarch64/fmul_z_zzi.html#fmul_z_zzi_d">Double-precision</a>
  AMED_AARCH64_CCLASS_fmulx_z_p_zz_, //!< <a href="../target/aarch64/fmulx_z_p_zz.html#fmulx_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fneg_z_p_z_, //!< <a href="../target/aarch64/fneg_z_p_z.html#fneg_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_fnmad_z_p_zzz_, //!< <a href="../target/aarch64/fnmad_z_p_zzz.html#fnmad_z_p_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_fnmla_z_p_zzz_, //!< <a href="../target/aarch64/fnmla_z_p_zzz.html#fnmla_z_p_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_fnmls_z_p_zzz_, //!< <a href="../target/aarch64/fnmls_z_p_zzz.html#fnmls_z_p_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_fnmsb_z_p_zzz_, //!< <a href="../target/aarch64/fnmsb_z_p_zzz.html#fnmsb_z_p_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_frecpe_z_z_, //!< <a href="../target/aarch64/frecpe_z_z.html#frecpe_z_z_">SVE</a>
  AMED_AARCH64_CCLASS_frecps_z_zz_, //!< <a href="../target/aarch64/frecps_z_zz.html#frecps_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_frecpx_z_p_z_, //!< <a href="../target/aarch64/frecpx_z_p_z.html#frecpx_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_frinti_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frinti_z_p_z_">Current mode</a>
  AMED_AARCH64_CCLASS_frintx_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frintx_z_p_z_">Current mode signalling inexact</a>
  AMED_AARCH64_CCLASS_frinta_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frinta_z_p_z_">Nearest with ties to away</a>
  AMED_AARCH64_CCLASS_frintn_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frintn_z_p_z_">Nearest with ties to even</a>
  AMED_AARCH64_CCLASS_frintz_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frintz_z_p_z_">Toward zero</a>
  AMED_AARCH64_CCLASS_frintm_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frintm_z_p_z_">Toward minus infinity</a>
  AMED_AARCH64_CCLASS_frintp_z_p_z_, //!< <a href="../target/aarch64/frinta_z_p_z.html#frintp_z_p_z_">Toward plus infinity</a>
  AMED_AARCH64_CCLASS_frsqrte_z_z_, //!< <a href="../target/aarch64/frsqrte_z_z.html#frsqrte_z_z_">SVE</a>
  AMED_AARCH64_CCLASS_frsqrts_z_zz_, //!< <a href="../target/aarch64/frsqrts_z_zz.html#frsqrts_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fscale_z_p_zz_, //!< <a href="../target/aarch64/fscale_z_p_zz.html#fscale_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fsqrt_z_p_z_, //!< <a href="../target/aarch64/fsqrt_z_p_z.html#fsqrt_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_fsub_z_p_zs_, //!< <a href="../target/aarch64/fsub_z_p_zs.html#fsub_z_p_zs_">SVE</a>
  AMED_AARCH64_CCLASS_fsub_z_p_zz_, //!< <a href="../target/aarch64/fsub_z_p_zz.html#fsub_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fsub_z_zz_, //!< <a href="../target/aarch64/fsub_z_zz.html#fsub_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_fsubr_z_p_zs_, //!< <a href="../target/aarch64/fsubr_z_p_zs.html#fsubr_z_p_zs_">SVE</a>
  AMED_AARCH64_CCLASS_fsubr_z_p_zz_, //!< <a href="../target/aarch64/fsubr_z_p_zz.html#fsubr_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_ftmad_z_zzi_, //!< <a href="../target/aarch64/ftmad_z_zzi.html#ftmad_z_zzi_">SVE</a>
  AMED_AARCH64_CCLASS_ftsmul_z_zz_, //!< <a href="../target/aarch64/ftsmul_z_zz.html#ftsmul_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_ftssel_z_zz_, //!< <a href="../target/aarch64/ftssel_z_zz.html#ftssel_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_histcnt_z_p_zz_, //!< <a href="../target/aarch64/histcnt_z_p_zz.html#histcnt_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_histseg_z_zz_, //!< <a href="../target/aarch64/histseg_z_zz.html#histseg_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_incb_r_rs_, //!< <a href="../target/aarch64/incb_r_rs.html#incb_r_rs_">Byte</a>
  AMED_AARCH64_CCLASS_incd_r_rs_, //!< <a href="../target/aarch64/incb_r_rs.html#incd_r_rs_">Doubleword</a>
  AMED_AARCH64_CCLASS_inch_r_rs_, //!< <a href="../target/aarch64/incb_r_rs.html#inch_r_rs_">Halfword</a>
  AMED_AARCH64_CCLASS_incw_r_rs_, //!< <a href="../target/aarch64/incb_r_rs.html#incw_r_rs_">Word</a>
  AMED_AARCH64_CCLASS_incd_z_zs_, //!< <a href="../target/aarch64/incd_z_zs.html#incd_z_zs_">Doubleword</a>
  AMED_AARCH64_CCLASS_inch_z_zs_, //!< <a href="../target/aarch64/incd_z_zs.html#inch_z_zs_">Halfword</a>
  AMED_AARCH64_CCLASS_incw_z_zs_, //!< <a href="../target/aarch64/incd_z_zs.html#incw_z_zs_">Word</a>
  AMED_AARCH64_CCLASS_incp_r_p_r_, //!< <a href="../target/aarch64/incp_r_p_r.html#incp_r_p_r_">SVE</a>
  AMED_AARCH64_CCLASS_incp_z_p_z_, //!< <a href="../target/aarch64/incp_z_p_z.html#incp_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_index_z_ii_, //!< <a href="../target/aarch64/index_z_ii.html#index_z_ii_">SVE</a>
  AMED_AARCH64_CCLASS_index_z_ir_, //!< <a href="../target/aarch64/index_z_ir.html#index_z_ir_">SVE</a>
  AMED_AARCH64_CCLASS_index_z_ri_, //!< <a href="../target/aarch64/index_z_ri.html#index_z_ri_">SVE</a>
  AMED_AARCH64_CCLASS_index_z_rr_, //!< <a href="../target/aarch64/index_z_rr.html#index_z_rr_">SVE</a>
  AMED_AARCH64_CCLASS_insr_z_r_, //!< <a href="../target/aarch64/insr_z_r.html#insr_z_r_">SVE</a>
  AMED_AARCH64_CCLASS_insr_z_v_, //!< <a href="../target/aarch64/insr_z_v.html#insr_z_v_">SVE</a>
  AMED_AARCH64_CCLASS_lasta_r_p_z_, //!< <a href="../target/aarch64/lasta_r_p_z.html#lasta_r_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_lasta_v_p_z_, //!< <a href="../target/aarch64/lasta_v_p_z.html#lasta_v_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_lastb_r_p_z_, //!< <a href="../target/aarch64/lastb_r_p_z.html#lastb_r_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_lastb_v_p_z_, //!< <a href="../target/aarch64/lastb_v_p_z.html#lastb_v_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_ld1b_z_p_ai_s, //!< <a href="../target/aarch64/ld1b_z_p_ai.html#ld1b_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1b_z_p_ai_d, //!< <a href="../target/aarch64/ld1b_z_p_ai.html#ld1b_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1b_z_p_bi_u8, //!< <a href="../target/aarch64/ld1b_z_p_bi.html#ld1b_z_p_bi_u8">8-bit element</a>
  AMED_AARCH64_CCLASS_ld1b_z_p_bi_u16, //!< <a href="../target/aarch64/ld1b_z_p_bi.html#ld1b_z_p_bi_u16">16-bit element</a>
  AMED_AARCH64_CCLASS_ld1b_z_p_bi_u32, //!< <a href="../target/aarch64/ld1b_z_p_bi.html#ld1b_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1b_z_p_bi_u64, //!< <a href="../target/aarch64/ld1b_z_p_bi.html#ld1b_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1b_z_p_br_u8, //!< <a href="../target/aarch64/ld1b_z_p_br.html#ld1b_z_p_br_u8">8-bit element</a>
  AMED_AARCH64_CCLASS_ld1b_z_p_br_u16, //!< <a href="../target/aarch64/ld1b_z_p_br.html#ld1b_z_p_br_u16">16-bit element</a>
  AMED_AARCH64_CCLASS_ld1b_z_p_br_u32, //!< <a href="../target/aarch64/ld1b_z_p_br.html#ld1b_z_p_br_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1b_z_p_br_u64, //!< <a href="../target/aarch64/ld1b_z_p_br.html#ld1b_z_p_br_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1b_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1b_z_p_bz.html#ld1b_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1b_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ld1b_z_p_bz.html#ld1b_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1b_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1b_z_p_bz.html#ld1b_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1d_z_p_ai_d, //!< <a href="../target/aarch64/ld1d_z_p_ai.html#ld1d_z_p_ai_d">SVE</a>
  AMED_AARCH64_CCLASS_ld1d_z_p_bi_u64, //!< <a href="../target/aarch64/ld1d_z_p_bi.html#ld1d_z_p_bi_u64">SVE</a>
  AMED_AARCH64_CCLASS_ld1d_z_p_br_u64, //!< <a href="../target/aarch64/ld1d_z_p_br.html#ld1d_z_p_br_u64">SVE</a>
  AMED_AARCH64_CCLASS_ld1d_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ld1d_z_p_bz.html#ld1d_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_ld1d_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1d_z_p_bz.html#ld1d_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1d_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ld1d_z_p_bz.html#ld1d_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ld1d_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1d_z_p_bz.html#ld1d_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_ai_s, //!< <a href="../target/aarch64/ld1h_z_p_ai.html#ld1h_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_ai_d, //!< <a href="../target/aarch64/ld1h_z_p_ai.html#ld1h_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_bi_u16, //!< <a href="../target/aarch64/ld1h_z_p_bi.html#ld1h_z_p_bi_u16">16-bit element</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_bi_u32, //!< <a href="../target/aarch64/ld1h_z_p_bi.html#ld1h_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_bi_u64, //!< <a href="../target/aarch64/ld1h_z_p_bi.html#ld1h_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_br_u16, //!< <a href="../target/aarch64/ld1h_z_p_br.html#ld1h_z_p_br_u16">16-bit element</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_br_u32, //!< <a href="../target/aarch64/ld1h_z_p_br.html#ld1h_z_p_br_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_br_u64, //!< <a href="../target/aarch64/ld1h_z_p_br.html#ld1h_z_p_br_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/ld1h_z_p_bz.html#ld1h_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ld1h_z_p_bz.html#ld1h_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1h_z_p_bz.html#ld1h_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ld1h_z_p_bz.html#ld1h_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ld1h_z_p_bz.html#ld1h_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ld1h_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1h_z_p_bz.html#ld1h_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1rb_z_p_bi_u8, //!< <a href="../target/aarch64/ld1rb_z_p_bi.html#ld1rb_z_p_bi_u8">8-bit element</a>
  AMED_AARCH64_CCLASS_ld1rb_z_p_bi_u16, //!< <a href="../target/aarch64/ld1rb_z_p_bi.html#ld1rb_z_p_bi_u16">16-bit element</a>
  AMED_AARCH64_CCLASS_ld1rb_z_p_bi_u32, //!< <a href="../target/aarch64/ld1rb_z_p_bi.html#ld1rb_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1rb_z_p_bi_u64, //!< <a href="../target/aarch64/ld1rb_z_p_bi.html#ld1rb_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1rd_z_p_bi_u64, //!< <a href="../target/aarch64/ld1rd_z_p_bi.html#ld1rd_z_p_bi_u64">SVE</a>
  AMED_AARCH64_CCLASS_ld1rh_z_p_bi_u16, //!< <a href="../target/aarch64/ld1rh_z_p_bi.html#ld1rh_z_p_bi_u16">16-bit element</a>
  AMED_AARCH64_CCLASS_ld1rh_z_p_bi_u32, //!< <a href="../target/aarch64/ld1rh_z_p_bi.html#ld1rh_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1rh_z_p_bi_u64, //!< <a href="../target/aarch64/ld1rh_z_p_bi.html#ld1rh_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1rob_z_p_bi_u8, //!< <a href="../target/aarch64/ld1rob_z_p_bi.html#ld1rob_z_p_bi_u8">SVE</a>
  AMED_AARCH64_CCLASS_ld1rob_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1rob_z_p_br.html#ld1rob_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld1rod_z_p_bi_u64, //!< <a href="../target/aarch64/ld1rod_z_p_bi.html#ld1rod_z_p_bi_u64">SVE</a>
  AMED_AARCH64_CCLASS_ld1rod_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1rod_z_p_br.html#ld1rod_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld1roh_z_p_bi_u16, //!< <a href="../target/aarch64/ld1roh_z_p_bi.html#ld1roh_z_p_bi_u16">SVE</a>
  AMED_AARCH64_CCLASS_ld1roh_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1roh_z_p_br.html#ld1roh_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld1row_z_p_bi_u32, //!< <a href="../target/aarch64/ld1row_z_p_bi.html#ld1row_z_p_bi_u32">SVE</a>
  AMED_AARCH64_CCLASS_ld1row_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1row_z_p_br.html#ld1row_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld1rqb_z_p_bi_u8, //!< <a href="../target/aarch64/ld1rqb_z_p_bi.html#ld1rqb_z_p_bi_u8">SVE</a>
  AMED_AARCH64_CCLASS_ld1rqb_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1rqb_z_p_br.html#ld1rqb_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld1rqd_z_p_bi_u64, //!< <a href="../target/aarch64/ld1rqd_z_p_bi.html#ld1rqd_z_p_bi_u64">SVE</a>
  AMED_AARCH64_CCLASS_ld1rqd_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1rqd_z_p_br.html#ld1rqd_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld1rqh_z_p_bi_u16, //!< <a href="../target/aarch64/ld1rqh_z_p_bi.html#ld1rqh_z_p_bi_u16">SVE</a>
  AMED_AARCH64_CCLASS_ld1rqh_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1rqh_z_p_br.html#ld1rqh_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld1rqw_z_p_bi_u32, //!< <a href="../target/aarch64/ld1rqw_z_p_bi.html#ld1rqw_z_p_bi_u32">SVE</a>
  AMED_AARCH64_CCLASS_ld1rqw_z_p_br_contiguous, //!< <a href="../target/aarch64/ld1rqw_z_p_br.html#ld1rqw_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld1rsb_z_p_bi_s16, //!< <a href="../target/aarch64/ld1rsb_z_p_bi.html#ld1rsb_z_p_bi_s16">16-bit element</a>
  AMED_AARCH64_CCLASS_ld1rsb_z_p_bi_s32, //!< <a href="../target/aarch64/ld1rsb_z_p_bi.html#ld1rsb_z_p_bi_s32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1rsb_z_p_bi_s64, //!< <a href="../target/aarch64/ld1rsb_z_p_bi.html#ld1rsb_z_p_bi_s64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1rsh_z_p_bi_s32, //!< <a href="../target/aarch64/ld1rsh_z_p_bi.html#ld1rsh_z_p_bi_s32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1rsh_z_p_bi_s64, //!< <a href="../target/aarch64/ld1rsh_z_p_bi.html#ld1rsh_z_p_bi_s64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1rsw_z_p_bi_s64, //!< <a href="../target/aarch64/ld1rsw_z_p_bi.html#ld1rsw_z_p_bi_s64">SVE</a>
  AMED_AARCH64_CCLASS_ld1rw_z_p_bi_u32, //!< <a href="../target/aarch64/ld1rw_z_p_bi.html#ld1rw_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1rw_z_p_bi_u64, //!< <a href="../target/aarch64/ld1rw_z_p_bi.html#ld1rw_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1sb_z_p_ai_s, //!< <a href="../target/aarch64/ld1sb_z_p_ai.html#ld1sb_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1sb_z_p_ai_d, //!< <a href="../target/aarch64/ld1sb_z_p_ai.html#ld1sb_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1sb_z_p_bi_s16, //!< <a href="../target/aarch64/ld1sb_z_p_bi.html#ld1sb_z_p_bi_s16">16-bit element</a>
  AMED_AARCH64_CCLASS_ld1sb_z_p_bi_s32, //!< <a href="../target/aarch64/ld1sb_z_p_bi.html#ld1sb_z_p_bi_s32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1sb_z_p_bi_s64, //!< <a href="../target/aarch64/ld1sb_z_p_bi.html#ld1sb_z_p_bi_s64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1sb_z_p_br_s16, //!< <a href="../target/aarch64/ld1sb_z_p_br.html#ld1sb_z_p_br_s16">16-bit element</a>
  AMED_AARCH64_CCLASS_ld1sb_z_p_br_s32, //!< <a href="../target/aarch64/ld1sb_z_p_br.html#ld1sb_z_p_br_s32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1sb_z_p_br_s64, //!< <a href="../target/aarch64/ld1sb_z_p_br.html#ld1sb_z_p_br_s64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1sb_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1sb_z_p_bz.html#ld1sb_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1sb_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ld1sb_z_p_bz.html#ld1sb_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1sb_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1sb_z_p_bz.html#ld1sb_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1sh_z_p_ai_s, //!< <a href="../target/aarch64/ld1sh_z_p_ai.html#ld1sh_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1sh_z_p_ai_d, //!< <a href="../target/aarch64/ld1sh_z_p_ai.html#ld1sh_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1sh_z_p_bi_s32, //!< <a href="../target/aarch64/ld1sh_z_p_bi.html#ld1sh_z_p_bi_s32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1sh_z_p_bi_s64, //!< <a href="../target/aarch64/ld1sh_z_p_bi.html#ld1sh_z_p_bi_s64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1sh_z_p_br_s32, //!< <a href="../target/aarch64/ld1sh_z_p_br.html#ld1sh_z_p_br_s32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1sh_z_p_br_s64, //!< <a href="../target/aarch64/ld1sh_z_p_br.html#ld1sh_z_p_br_s64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1sh_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/ld1sh_z_p_bz.html#ld1sh_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ld1sh_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ld1sh_z_p_bz.html#ld1sh_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_ld1sh_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1sh_z_p_bz.html#ld1sh_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1sh_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ld1sh_z_p_bz.html#ld1sh_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1sh_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ld1sh_z_p_bz.html#ld1sh_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ld1sh_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1sh_z_p_bz.html#ld1sh_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1sw_z_p_ai_d, //!< <a href="../target/aarch64/ld1sw_z_p_ai.html#ld1sw_z_p_ai_d">SVE</a>
  AMED_AARCH64_CCLASS_ld1sw_z_p_bi_s64, //!< <a href="../target/aarch64/ld1sw_z_p_bi.html#ld1sw_z_p_bi_s64">SVE</a>
  AMED_AARCH64_CCLASS_ld1sw_z_p_br_s64, //!< <a href="../target/aarch64/ld1sw_z_p_br.html#ld1sw_z_p_br_s64">SVE</a>
  AMED_AARCH64_CCLASS_ld1sw_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ld1sw_z_p_bz.html#ld1sw_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_ld1sw_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1sw_z_p_bz.html#ld1sw_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1sw_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ld1sw_z_p_bz.html#ld1sw_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ld1sw_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1sw_z_p_bz.html#ld1sw_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1w_z_p_ai_s, //!< <a href="../target/aarch64/ld1w_z_p_ai.html#ld1w_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1w_z_p_ai_d, //!< <a href="../target/aarch64/ld1w_z_p_ai.html#ld1w_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1w_z_p_bi_u32, //!< <a href="../target/aarch64/ld1w_z_p_bi.html#ld1w_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1w_z_p_bi_u64, //!< <a href="../target/aarch64/ld1w_z_p_bi.html#ld1w_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1w_z_p_br_u32, //!< <a href="../target/aarch64/ld1w_z_p_br.html#ld1w_z_p_br_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ld1w_z_p_br_u64, //!< <a href="../target/aarch64/ld1w_z_p_br.html#ld1w_z_p_br_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ld1w_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/ld1w_z_p_bz.html#ld1w_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ld1w_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ld1w_z_p_bz.html#ld1w_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_ld1w_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ld1w_z_p_bz.html#ld1w_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1w_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ld1w_z_p_bz.html#ld1w_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ld1w_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ld1w_z_p_bz.html#ld1w_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ld1w_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ld1w_z_p_bz.html#ld1w_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ld2b_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld2b_z_p_bi.html#ld2b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld2b_z_p_br_contiguous, //!< <a href="../target/aarch64/ld2b_z_p_br.html#ld2b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld2d_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld2d_z_p_bi.html#ld2d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld2d_z_p_br_contiguous, //!< <a href="../target/aarch64/ld2d_z_p_br.html#ld2d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld2h_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld2h_z_p_bi.html#ld2h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld2h_z_p_br_contiguous, //!< <a href="../target/aarch64/ld2h_z_p_br.html#ld2h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld2w_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld2w_z_p_bi.html#ld2w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld2w_z_p_br_contiguous, //!< <a href="../target/aarch64/ld2w_z_p_br.html#ld2w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld3b_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld3b_z_p_bi.html#ld3b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld3b_z_p_br_contiguous, //!< <a href="../target/aarch64/ld3b_z_p_br.html#ld3b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld3d_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld3d_z_p_bi.html#ld3d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld3d_z_p_br_contiguous, //!< <a href="../target/aarch64/ld3d_z_p_br.html#ld3d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld3h_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld3h_z_p_bi.html#ld3h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld3h_z_p_br_contiguous, //!< <a href="../target/aarch64/ld3h_z_p_br.html#ld3h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld3w_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld3w_z_p_bi.html#ld3w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld3w_z_p_br_contiguous, //!< <a href="../target/aarch64/ld3w_z_p_br.html#ld3w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld4b_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld4b_z_p_bi.html#ld4b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld4b_z_p_br_contiguous, //!< <a href="../target/aarch64/ld4b_z_p_br.html#ld4b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld4d_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld4d_z_p_bi.html#ld4d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld4d_z_p_br_contiguous, //!< <a href="../target/aarch64/ld4d_z_p_br.html#ld4d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld4h_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld4h_z_p_bi.html#ld4h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld4h_z_p_br_contiguous, //!< <a href="../target/aarch64/ld4h_z_p_br.html#ld4h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld4w_z_p_bi_contiguous, //!< <a href="../target/aarch64/ld4w_z_p_bi.html#ld4w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ld4w_z_p_br_contiguous, //!< <a href="../target/aarch64/ld4w_z_p_br.html#ld4w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ldff1b_z_p_ai_s, //!< <a href="../target/aarch64/ldff1b_z_p_ai.html#ldff1b_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_ldff1b_z_p_ai_d, //!< <a href="../target/aarch64/ldff1b_z_p_ai.html#ldff1b_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_ldff1b_z_p_br_u8, //!< <a href="../target/aarch64/ldff1b_z_p_br.html#ldff1b_z_p_br_u8">8-bit element</a>
  AMED_AARCH64_CCLASS_ldff1b_z_p_br_u16, //!< <a href="../target/aarch64/ldff1b_z_p_br.html#ldff1b_z_p_br_u16">16-bit element</a>
  AMED_AARCH64_CCLASS_ldff1b_z_p_br_u32, //!< <a href="../target/aarch64/ldff1b_z_p_br.html#ldff1b_z_p_br_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ldff1b_z_p_br_u64, //!< <a href="../target/aarch64/ldff1b_z_p_br.html#ldff1b_z_p_br_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ldff1b_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1b_z_p_bz.html#ldff1b_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1b_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ldff1b_z_p_bz.html#ldff1b_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1b_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1b_z_p_bz.html#ldff1b_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1d_z_p_ai_d, //!< <a href="../target/aarch64/ldff1d_z_p_ai.html#ldff1d_z_p_ai_d">SVE</a>
  AMED_AARCH64_CCLASS_ldff1d_z_p_br_u64, //!< <a href="../target/aarch64/ldff1d_z_p_br.html#ldff1d_z_p_br_u64">SVE</a>
  AMED_AARCH64_CCLASS_ldff1d_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ldff1d_z_p_bz.html#ldff1d_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_ldff1d_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1d_z_p_bz.html#ldff1d_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1d_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ldff1d_z_p_bz.html#ldff1d_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ldff1d_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1d_z_p_bz.html#ldff1d_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1h_z_p_ai_s, //!< <a href="../target/aarch64/ldff1h_z_p_ai.html#ldff1h_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_ldff1h_z_p_ai_d, //!< <a href="../target/aarch64/ldff1h_z_p_ai.html#ldff1h_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_ldff1h_z_p_br_u16, //!< <a href="../target/aarch64/ldff1h_z_p_br.html#ldff1h_z_p_br_u16">16-bit element</a>
  AMED_AARCH64_CCLASS_ldff1h_z_p_br_u32, //!< <a href="../target/aarch64/ldff1h_z_p_br.html#ldff1h_z_p_br_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ldff1h_z_p_br_u64, //!< <a href="../target/aarch64/ldff1h_z_p_br.html#ldff1h_z_p_br_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ldff1h_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/ldff1h_z_p_bz.html#ldff1h_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ldff1h_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ldff1h_z_p_bz.html#ldff1h_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_ldff1h_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1h_z_p_bz.html#ldff1h_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1h_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ldff1h_z_p_bz.html#ldff1h_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1h_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ldff1h_z_p_bz.html#ldff1h_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ldff1h_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1h_z_p_bz.html#ldff1h_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1sb_z_p_ai_s, //!< <a href="../target/aarch64/ldff1sb_z_p_ai.html#ldff1sb_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_ldff1sb_z_p_ai_d, //!< <a href="../target/aarch64/ldff1sb_z_p_ai.html#ldff1sb_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_ldff1sb_z_p_br_s16, //!< <a href="../target/aarch64/ldff1sb_z_p_br.html#ldff1sb_z_p_br_s16">16-bit element</a>
  AMED_AARCH64_CCLASS_ldff1sb_z_p_br_s32, //!< <a href="../target/aarch64/ldff1sb_z_p_br.html#ldff1sb_z_p_br_s32">32-bit element</a>
  AMED_AARCH64_CCLASS_ldff1sb_z_p_br_s64, //!< <a href="../target/aarch64/ldff1sb_z_p_br.html#ldff1sb_z_p_br_s64">64-bit element</a>
  AMED_AARCH64_CCLASS_ldff1sb_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1sb_z_p_bz.html#ldff1sb_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1sb_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ldff1sb_z_p_bz.html#ldff1sb_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1sb_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1sb_z_p_bz.html#ldff1sb_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1sh_z_p_ai_s, //!< <a href="../target/aarch64/ldff1sh_z_p_ai.html#ldff1sh_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_ldff1sh_z_p_ai_d, //!< <a href="../target/aarch64/ldff1sh_z_p_ai.html#ldff1sh_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_ldff1sh_z_p_br_s32, //!< <a href="../target/aarch64/ldff1sh_z_p_br.html#ldff1sh_z_p_br_s32">32-bit element</a>
  AMED_AARCH64_CCLASS_ldff1sh_z_p_br_s64, //!< <a href="../target/aarch64/ldff1sh_z_p_br.html#ldff1sh_z_p_br_s64">64-bit element</a>
  AMED_AARCH64_CCLASS_ldff1sh_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/ldff1sh_z_p_bz.html#ldff1sh_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ldff1sh_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ldff1sh_z_p_bz.html#ldff1sh_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_ldff1sh_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1sh_z_p_bz.html#ldff1sh_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1sh_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ldff1sh_z_p_bz.html#ldff1sh_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1sh_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ldff1sh_z_p_bz.html#ldff1sh_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ldff1sh_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1sh_z_p_bz.html#ldff1sh_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1sw_z_p_ai_d, //!< <a href="../target/aarch64/ldff1sw_z_p_ai.html#ldff1sw_z_p_ai_d">SVE</a>
  AMED_AARCH64_CCLASS_ldff1sw_z_p_br_s64, //!< <a href="../target/aarch64/ldff1sw_z_p_br.html#ldff1sw_z_p_br_s64">SVE</a>
  AMED_AARCH64_CCLASS_ldff1sw_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ldff1sw_z_p_bz.html#ldff1sw_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_ldff1sw_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1sw_z_p_bz.html#ldff1sw_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1sw_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ldff1sw_z_p_bz.html#ldff1sw_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ldff1sw_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1sw_z_p_bz.html#ldff1sw_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1w_z_p_ai_s, //!< <a href="../target/aarch64/ldff1w_z_p_ai.html#ldff1w_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_ldff1w_z_p_ai_d, //!< <a href="../target/aarch64/ldff1w_z_p_ai.html#ldff1w_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_ldff1w_z_p_br_u32, //!< <a href="../target/aarch64/ldff1w_z_p_br.html#ldff1w_z_p_br_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ldff1w_z_p_br_u64, //!< <a href="../target/aarch64/ldff1w_z_p_br.html#ldff1w_z_p_br_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ldff1w_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/ldff1w_z_p_bz.html#ldff1w_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ldff1w_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/ldff1w_z_p_bz.html#ldff1w_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_ldff1w_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/ldff1w_z_p_bz.html#ldff1w_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1w_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/ldff1w_z_p_bz.html#ldff1w_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldff1w_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/ldff1w_z_p_bz.html#ldff1w_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ldff1w_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/ldff1w_z_p_bz.html#ldff1w_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldnf1b_z_p_bi_u8, //!< <a href="../target/aarch64/ldnf1b_z_p_bi.html#ldnf1b_z_p_bi_u8">8-bit element</a>
  AMED_AARCH64_CCLASS_ldnf1b_z_p_bi_u16, //!< <a href="../target/aarch64/ldnf1b_z_p_bi.html#ldnf1b_z_p_bi_u16">16-bit element</a>
  AMED_AARCH64_CCLASS_ldnf1b_z_p_bi_u32, //!< <a href="../target/aarch64/ldnf1b_z_p_bi.html#ldnf1b_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ldnf1b_z_p_bi_u64, //!< <a href="../target/aarch64/ldnf1b_z_p_bi.html#ldnf1b_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ldnf1d_z_p_bi_u64, //!< <a href="../target/aarch64/ldnf1d_z_p_bi.html#ldnf1d_z_p_bi_u64">SVE</a>
  AMED_AARCH64_CCLASS_ldnf1h_z_p_bi_u16, //!< <a href="../target/aarch64/ldnf1h_z_p_bi.html#ldnf1h_z_p_bi_u16">16-bit element</a>
  AMED_AARCH64_CCLASS_ldnf1h_z_p_bi_u32, //!< <a href="../target/aarch64/ldnf1h_z_p_bi.html#ldnf1h_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ldnf1h_z_p_bi_u64, //!< <a href="../target/aarch64/ldnf1h_z_p_bi.html#ldnf1h_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ldnf1sb_z_p_bi_s16, //!< <a href="../target/aarch64/ldnf1sb_z_p_bi.html#ldnf1sb_z_p_bi_s16">16-bit element</a>
  AMED_AARCH64_CCLASS_ldnf1sb_z_p_bi_s32, //!< <a href="../target/aarch64/ldnf1sb_z_p_bi.html#ldnf1sb_z_p_bi_s32">32-bit element</a>
  AMED_AARCH64_CCLASS_ldnf1sb_z_p_bi_s64, //!< <a href="../target/aarch64/ldnf1sb_z_p_bi.html#ldnf1sb_z_p_bi_s64">64-bit element</a>
  AMED_AARCH64_CCLASS_ldnf1sh_z_p_bi_s32, //!< <a href="../target/aarch64/ldnf1sh_z_p_bi.html#ldnf1sh_z_p_bi_s32">32-bit element</a>
  AMED_AARCH64_CCLASS_ldnf1sh_z_p_bi_s64, //!< <a href="../target/aarch64/ldnf1sh_z_p_bi.html#ldnf1sh_z_p_bi_s64">64-bit element</a>
  AMED_AARCH64_CCLASS_ldnf1sw_z_p_bi_s64, //!< <a href="../target/aarch64/ldnf1sw_z_p_bi.html#ldnf1sw_z_p_bi_s64">SVE</a>
  AMED_AARCH64_CCLASS_ldnf1w_z_p_bi_u32, //!< <a href="../target/aarch64/ldnf1w_z_p_bi.html#ldnf1w_z_p_bi_u32">32-bit element</a>
  AMED_AARCH64_CCLASS_ldnf1w_z_p_bi_u64, //!< <a href="../target/aarch64/ldnf1w_z_p_bi.html#ldnf1w_z_p_bi_u64">64-bit element</a>
  AMED_AARCH64_CCLASS_ldnt1b_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/ldnt1b_z_p_ar.html#ldnt1b_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldnt1b_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1b_z_p_ar.html#ldnt1b_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldnt1b_z_p_bi_contiguous, //!< <a href="../target/aarch64/ldnt1b_z_p_bi.html#ldnt1b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ldnt1b_z_p_br_contiguous, //!< <a href="../target/aarch64/ldnt1b_z_p_br.html#ldnt1b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ldnt1d_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1d_z_p_ar.html#ldnt1d_z_p_ar_d_64_unscaled">SVE2</a>
  AMED_AARCH64_CCLASS_ldnt1d_z_p_bi_contiguous, //!< <a href="../target/aarch64/ldnt1d_z_p_bi.html#ldnt1d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ldnt1d_z_p_br_contiguous, //!< <a href="../target/aarch64/ldnt1d_z_p_br.html#ldnt1d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ldnt1h_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/ldnt1h_z_p_ar.html#ldnt1h_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldnt1h_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1h_z_p_ar.html#ldnt1h_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldnt1h_z_p_bi_contiguous, //!< <a href="../target/aarch64/ldnt1h_z_p_bi.html#ldnt1h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ldnt1h_z_p_br_contiguous, //!< <a href="../target/aarch64/ldnt1h_z_p_br.html#ldnt1h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ldnt1sb_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/ldnt1sb_z_p_ar.html#ldnt1sb_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldnt1sb_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1sb_z_p_ar.html#ldnt1sb_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldnt1sh_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/ldnt1sh_z_p_ar.html#ldnt1sh_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldnt1sh_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1sh_z_p_ar.html#ldnt1sh_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldnt1sw_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1sw_z_p_ar.html#ldnt1sw_z_p_ar_d_64_unscaled">SVE2</a>
  AMED_AARCH64_CCLASS_ldnt1w_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/ldnt1w_z_p_ar.html#ldnt1w_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldnt1w_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/ldnt1w_z_p_ar.html#ldnt1w_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_ldnt1w_z_p_bi_contiguous, //!< <a href="../target/aarch64/ldnt1w_z_p_bi.html#ldnt1w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ldnt1w_z_p_br_contiguous, //!< <a href="../target/aarch64/ldnt1w_z_p_br.html#ldnt1w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_ldr_p_bi_, //!< <a href="../target/aarch64/ldr_p_bi.html#ldr_p_bi_">SVE</a>
  AMED_AARCH64_CCLASS_ldr_z_bi_, //!< <a href="../target/aarch64/ldr_z_bi.html#ldr_z_bi_">SVE</a>
  AMED_AARCH64_CCLASS_lsl_z_p_zi_, //!< <a href="../target/aarch64/lsl_z_p_zi.html#lsl_z_p_zi_">SVE</a>
  AMED_AARCH64_CCLASS_lsl_z_p_zw_, //!< <a href="../target/aarch64/lsl_z_p_zw.html#lsl_z_p_zw_">SVE</a>
  AMED_AARCH64_CCLASS_lsl_z_p_zz_, //!< <a href="../target/aarch64/lsl_z_p_zz.html#lsl_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_lsl_z_zi_, //!< <a href="../target/aarch64/lsl_z_zi.html#lsl_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_lsl_z_zw_, //!< <a href="../target/aarch64/lsl_z_zw.html#lsl_z_zw_">SVE</a>
  AMED_AARCH64_CCLASS_lslr_z_p_zz_, //!< <a href="../target/aarch64/lslr_z_p_zz.html#lslr_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_lsr_z_p_zi_, //!< <a href="../target/aarch64/lsr_z_p_zi.html#lsr_z_p_zi_">SVE</a>
  AMED_AARCH64_CCLASS_lsr_z_p_zw_, //!< <a href="../target/aarch64/lsr_z_p_zw.html#lsr_z_p_zw_">SVE</a>
  AMED_AARCH64_CCLASS_lsr_z_p_zz_, //!< <a href="../target/aarch64/lsr_z_p_zz.html#lsr_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_lsr_z_zi_, //!< <a href="../target/aarch64/lsr_z_zi.html#lsr_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_lsr_z_zw_, //!< <a href="../target/aarch64/lsr_z_zw.html#lsr_z_zw_">SVE</a>
  AMED_AARCH64_CCLASS_lsrr_z_p_zz_, //!< <a href="../target/aarch64/lsrr_z_p_zz.html#lsrr_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_mad_z_p_zzz_, //!< <a href="../target/aarch64/mad_z_p_zzz.html#mad_z_p_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_match_p_p_zz_, //!< <a href="../target/aarch64/match_p_p_zz.html#match_p_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_mla_z_p_zzz_, //!< <a href="../target/aarch64/mla_z_p_zzz.html#mla_z_p_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_mla_z_zzzi_h, //!< <a href="../target/aarch64/mla_z_zzzi.html#mla_z_zzzi_h">16-bit</a>
  AMED_AARCH64_CCLASS_mla_z_zzzi_s, //!< <a href="../target/aarch64/mla_z_zzzi.html#mla_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_mla_z_zzzi_d, //!< <a href="../target/aarch64/mla_z_zzzi.html#mla_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_mls_z_p_zzz_, //!< <a href="../target/aarch64/mls_z_p_zzz.html#mls_z_p_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_mls_z_zzzi_h, //!< <a href="../target/aarch64/mls_z_zzzi.html#mls_z_zzzi_h">16-bit</a>
  AMED_AARCH64_CCLASS_mls_z_zzzi_s, //!< <a href="../target/aarch64/mls_z_zzzi.html#mls_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_mls_z_zzzi_d, //!< <a href="../target/aarch64/mls_z_zzzi.html#mls_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_movprfx_z_p_z_, //!< <a href="../target/aarch64/movprfx_z_p_z.html#movprfx_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_movprfx_z_z_, //!< <a href="../target/aarch64/movprfx_z_z.html#movprfx_z_z_">SVE</a>
  AMED_AARCH64_CCLASS_msb_z_p_zzz_, //!< <a href="../target/aarch64/msb_z_p_zzz.html#msb_z_p_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_mul_z_p_zz_, //!< <a href="../target/aarch64/mul_z_p_zz.html#mul_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_mul_z_zi_, //!< <a href="../target/aarch64/mul_z_zi.html#mul_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_mul_z_zz_, //!< <a href="../target/aarch64/mul_z_zz.html#mul_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_mul_z_zzi_h, //!< <a href="../target/aarch64/mul_z_zzi.html#mul_z_zzi_h">16-bit</a>
  AMED_AARCH64_CCLASS_mul_z_zzi_s, //!< <a href="../target/aarch64/mul_z_zzi.html#mul_z_zzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_mul_z_zzi_d, //!< <a href="../target/aarch64/mul_z_zzi.html#mul_z_zzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_nand_p_p_pp_z, //!< <a href="../target/aarch64/nand_p_p_pp.html#nand_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_nands_p_p_pp_z, //!< <a href="../target/aarch64/nand_p_p_pp.html#nands_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_nbsl_z_zzz_, //!< <a href="../target/aarch64/nbsl_z_zzz.html#nbsl_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_neg_z_p_z_, //!< <a href="../target/aarch64/neg_z_p_z.html#neg_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_nmatch_p_p_zz_, //!< <a href="../target/aarch64/nmatch_p_p_zz.html#nmatch_p_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_nor_p_p_pp_z, //!< <a href="../target/aarch64/nor_p_p_pp.html#nor_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_nors_p_p_pp_z, //!< <a href="../target/aarch64/nor_p_p_pp.html#nors_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_not_z_p_z_, //!< <a href="../target/aarch64/not_z_p_z.html#not_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_orn_p_p_pp_z, //!< <a href="../target/aarch64/orn_p_p_pp.html#orn_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_orns_p_p_pp_z, //!< <a href="../target/aarch64/orn_p_p_pp.html#orns_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_orr_p_p_pp_orr_p_p_pp_z, //!< <a href="../target/aarch64/orr_p_p_pp.html#orr_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_orr_p_p_pp_orrs_p_p_pp_z, //!< <a href="../target/aarch64/orr_p_p_pp.html#orrs_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_orr_z_p_zz_, //!< <a href="../target/aarch64/orr_z_p_zz.html#orr_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_orr_z_zi_orr_z_zi_, //!< <a href="../target/aarch64/orr_z_zi.html#orr_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_orr_z_zz_orr_z_zz_, //!< <a href="../target/aarch64/orr_z_zz.html#orr_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_orv_r_p_z_, //!< <a href="../target/aarch64/orv_r_p_z.html#orv_r_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_pfalse_p_, //!< <a href="../target/aarch64/pfalse_p.html#pfalse_p_">SVE</a>
  AMED_AARCH64_CCLASS_pfirst_p_p_p_, //!< <a href="../target/aarch64/pfirst_p_p_p.html#pfirst_p_p_p_">SVE</a>
  AMED_AARCH64_CCLASS_pmul_z_zz_, //!< <a href="../target/aarch64/pmul_z_zz.html#pmul_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_pmullb_z_zz_, //!< <a href="../target/aarch64/pmullb_z_zz.html#pmullb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_pmullt_z_zz_, //!< <a href="../target/aarch64/pmullt_z_zz.html#pmullt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_pnext_p_p_p_, //!< <a href="../target/aarch64/pnext_p_p_p.html#pnext_p_p_p_">SVE</a>
  AMED_AARCH64_CCLASS_prfb_i_p_ai_s, //!< <a href="../target/aarch64/prfb_i_p_ai.html#prfb_i_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_prfb_i_p_ai_d, //!< <a href="../target/aarch64/prfb_i_p_ai.html#prfb_i_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_prfb_i_p_bi_s, //!< <a href="../target/aarch64/prfb_i_p_bi.html#prfb_i_p_bi_s">SVE</a>
  AMED_AARCH64_CCLASS_prfb_i_p_br_s, //!< <a href="../target/aarch64/prfb_i_p_br.html#prfb_i_p_br_s">SVE</a>
  AMED_AARCH64_CCLASS_prfb_i_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/prfb_i_p_bz.html#prfb_i_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_CCLASS_prfb_i_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/prfb_i_p_bz.html#prfb_i_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_prfb_i_p_bz_d_64_scaled, //!< <a href="../target/aarch64/prfb_i_p_bz.html#prfb_i_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_prfd_i_p_ai_s, //!< <a href="../target/aarch64/prfd_i_p_ai.html#prfd_i_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_prfd_i_p_ai_d, //!< <a href="../target/aarch64/prfd_i_p_ai.html#prfd_i_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_prfd_i_p_bi_s, //!< <a href="../target/aarch64/prfd_i_p_bi.html#prfd_i_p_bi_s">SVE</a>
  AMED_AARCH64_CCLASS_prfd_i_p_br_s, //!< <a href="../target/aarch64/prfd_i_p_br.html#prfd_i_p_br_s">SVE</a>
  AMED_AARCH64_CCLASS_prfd_i_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/prfd_i_p_bz.html#prfd_i_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_CCLASS_prfd_i_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/prfd_i_p_bz.html#prfd_i_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_prfd_i_p_bz_d_64_scaled, //!< <a href="../target/aarch64/prfd_i_p_bz.html#prfd_i_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_prfh_i_p_ai_s, //!< <a href="../target/aarch64/prfh_i_p_ai.html#prfh_i_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_prfh_i_p_ai_d, //!< <a href="../target/aarch64/prfh_i_p_ai.html#prfh_i_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_prfh_i_p_bi_s, //!< <a href="../target/aarch64/prfh_i_p_bi.html#prfh_i_p_bi_s">SVE</a>
  AMED_AARCH64_CCLASS_prfh_i_p_br_s, //!< <a href="../target/aarch64/prfh_i_p_br.html#prfh_i_p_br_s">SVE</a>
  AMED_AARCH64_CCLASS_prfh_i_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/prfh_i_p_bz.html#prfh_i_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_CCLASS_prfh_i_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/prfh_i_p_bz.html#prfh_i_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_prfh_i_p_bz_d_64_scaled, //!< <a href="../target/aarch64/prfh_i_p_bz.html#prfh_i_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_prfw_i_p_ai_s, //!< <a href="../target/aarch64/prfw_i_p_ai.html#prfw_i_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_prfw_i_p_ai_d, //!< <a href="../target/aarch64/prfw_i_p_ai.html#prfw_i_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_prfw_i_p_bi_s, //!< <a href="../target/aarch64/prfw_i_p_bi.html#prfw_i_p_bi_s">SVE</a>
  AMED_AARCH64_CCLASS_prfw_i_p_br_s, //!< <a href="../target/aarch64/prfw_i_p_br.html#prfw_i_p_br_s">SVE</a>
  AMED_AARCH64_CCLASS_prfw_i_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/prfw_i_p_bz.html#prfw_i_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_CCLASS_prfw_i_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/prfw_i_p_bz.html#prfw_i_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_prfw_i_p_bz_d_64_scaled, //!< <a href="../target/aarch64/prfw_i_p_bz.html#prfw_i_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_ptest_p_p_, //!< <a href="../target/aarch64/ptest_p_p.html#ptest_p_p_">SVE</a>
  AMED_AARCH64_CCLASS_ptrue_p_s_, //!< <a href="../target/aarch64/ptrue_p_s.html#ptrue_p_s_">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_ptrues_p_s_, //!< <a href="../target/aarch64/ptrue_p_s.html#ptrues_p_s_">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_punpkhi_p_p_, //!< <a href="../target/aarch64/punpkhi_p_p.html#punpkhi_p_p_">High half</a>
  AMED_AARCH64_CCLASS_punpklo_p_p_, //!< <a href="../target/aarch64/punpkhi_p_p.html#punpklo_p_p_">Low half</a>
  AMED_AARCH64_CCLASS_raddhnb_z_zz_, //!< <a href="../target/aarch64/raddhnb_z_zz.html#raddhnb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_raddhnt_z_zz_, //!< <a href="../target/aarch64/raddhnt_z_zz.html#raddhnt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_rax1_z_zz_, //!< <a href="../target/aarch64/rax1_z_zz.html#rax1_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_rbit_z_p_z_, //!< <a href="../target/aarch64/rbit_z_p_z.html#rbit_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_rdffr_p_f_, //!< <a href="../target/aarch64/rdffr_p_f.html#rdffr_p_f_">SVE</a>
  AMED_AARCH64_CCLASS_rdffr_p_p_f_, //!< <a href="../target/aarch64/rdffr_p_p_f.html#rdffr_p_p_f_">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_rdffrs_p_p_f_, //!< <a href="../target/aarch64/rdffr_p_p_f.html#rdffrs_p_p_f_">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_rdvl_r_i_, //!< <a href="../target/aarch64/rdvl_r_i.html#rdvl_r_i_">SVE</a>
  AMED_AARCH64_CCLASS_rev_p_p_, //!< <a href="../target/aarch64/rev_p_p.html#rev_p_p_">SVE</a>
  AMED_AARCH64_CCLASS_rev_z_z_, //!< <a href="../target/aarch64/rev_z_z.html#rev_z_z_">SVE</a>
  AMED_AARCH64_CCLASS_revb_z_z_, //!< <a href="../target/aarch64/revb_z_z.html#revb_z_z_">Byte</a>
  AMED_AARCH64_CCLASS_revh_z_z_, //!< <a href="../target/aarch64/revb_z_z.html#revh_z_z_">Halfword</a>
  AMED_AARCH64_CCLASS_revw_z_z_, //!< <a href="../target/aarch64/revb_z_z.html#revw_z_z_">Word</a>
  AMED_AARCH64_CCLASS_rshrnb_z_zi_, //!< <a href="../target/aarch64/rshrnb_z_zi.html#rshrnb_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_rshrnt_z_zi_, //!< <a href="../target/aarch64/rshrnt_z_zi.html#rshrnt_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_rsubhnb_z_zz_, //!< <a href="../target/aarch64/rsubhnb_z_zz.html#rsubhnb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_rsubhnt_z_zz_, //!< <a href="../target/aarch64/rsubhnt_z_zz.html#rsubhnt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_saba_z_zzz_, //!< <a href="../target/aarch64/saba_z_zzz.html#saba_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_sabalb_z_zzz_, //!< <a href="../target/aarch64/sabalb_z_zzz.html#sabalb_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_sabalt_z_zzz_, //!< <a href="../target/aarch64/sabalt_z_zzz.html#sabalt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_sabd_z_p_zz_, //!< <a href="../target/aarch64/sabd_z_p_zz.html#sabd_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_sabdlb_z_zz_, //!< <a href="../target/aarch64/sabdlb_z_zz.html#sabdlb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sabdlt_z_zz_, //!< <a href="../target/aarch64/sabdlt_z_zz.html#sabdlt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sadalp_z_p_z_, //!< <a href="../target/aarch64/sadalp_z_p_z.html#sadalp_z_p_z_">SVE2</a>
  AMED_AARCH64_CCLASS_saddlb_z_zz_, //!< <a href="../target/aarch64/saddlb_z_zz.html#saddlb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_saddlbt_z_zz_, //!< <a href="../target/aarch64/saddlbt_z_zz.html#saddlbt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_saddlt_z_zz_, //!< <a href="../target/aarch64/saddlt_z_zz.html#saddlt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_saddv_r_p_z_, //!< <a href="../target/aarch64/saddv_r_p_z.html#saddv_r_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_saddwb_z_zz_, //!< <a href="../target/aarch64/saddwb_z_zz.html#saddwb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_saddwt_z_zz_, //!< <a href="../target/aarch64/saddwt_z_zz.html#saddwt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sbclb_z_zzz_, //!< <a href="../target/aarch64/sbclb_z_zzz.html#sbclb_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_sbclt_z_zzz_, //!< <a href="../target/aarch64/sbclt_z_zzz.html#sbclt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_scvtf_z_p_z_h2fp16, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_h2fp16">16-bit to half-precision</a>
  AMED_AARCH64_CCLASS_scvtf_z_p_z_w2fp16, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_w2fp16">32-bit to half-precision</a>
  AMED_AARCH64_CCLASS_scvtf_z_p_z_w2s, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_w2s">32-bit to single-precision</a>
  AMED_AARCH64_CCLASS_scvtf_z_p_z_w2d, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_w2d">32-bit to double-precision</a>
  AMED_AARCH64_CCLASS_scvtf_z_p_z_x2fp16, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_x2fp16">64-bit to half-precision</a>
  AMED_AARCH64_CCLASS_scvtf_z_p_z_x2s, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_x2s">64-bit to single-precision</a>
  AMED_AARCH64_CCLASS_scvtf_z_p_z_x2d, //!< <a href="../target/aarch64/scvtf_z_p_z.html#scvtf_z_p_z_x2d">64-bit to double-precision</a>
  AMED_AARCH64_CCLASS_sdiv_z_p_zz_, //!< <a href="../target/aarch64/sdiv_z_p_zz.html#sdiv_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_sdivr_z_p_zz_, //!< <a href="../target/aarch64/sdivr_z_p_zz.html#sdivr_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_sdot_z_zzz_, //!< <a href="../target/aarch64/sdot_z_zzz.html#sdot_z_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_sdot_z_zzzi_s, //!< <a href="../target/aarch64/sdot_z_zzzi.html#sdot_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_sdot_z_zzzi_d, //!< <a href="../target/aarch64/sdot_z_zzzi.html#sdot_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_sel_p_p_pp_sel_p_p_pp_, //!< <a href="../target/aarch64/sel_p_p_pp.html#sel_p_p_pp_">SVE</a>
  AMED_AARCH64_CCLASS_sel_z_p_zz_sel_z_p_zz_, //!< <a href="../target/aarch64/sel_z_p_zz.html#sel_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_setffr_f_, //!< <a href="../target/aarch64/setffr_f.html#setffr_f_">SVE</a>
  AMED_AARCH64_CCLASS_shadd_z_p_zz_, //!< <a href="../target/aarch64/shadd_z_p_zz.html#shadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_shrnb_z_zi_, //!< <a href="../target/aarch64/shrnb_z_zi.html#shrnb_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_shrnt_z_zi_, //!< <a href="../target/aarch64/shrnt_z_zi.html#shrnt_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_shsub_z_p_zz_, //!< <a href="../target/aarch64/shsub_z_p_zz.html#shsub_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_shsubr_z_p_zz_, //!< <a href="../target/aarch64/shsubr_z_p_zz.html#shsubr_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sli_z_zzi_, //!< <a href="../target/aarch64/sli_z_zzi.html#sli_z_zzi_">SVE2</a>
  AMED_AARCH64_CCLASS_sm4e_z_zz_, //!< <a href="../target/aarch64/sm4e_z_zz.html#sm4e_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sm4ekey_z_zz_, //!< <a href="../target/aarch64/sm4ekey_z_zz.html#sm4ekey_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_smax_z_p_zz_, //!< <a href="../target/aarch64/smax_z_p_zz.html#smax_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_smax_z_zi_, //!< <a href="../target/aarch64/smax_z_zi.html#smax_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_smaxp_z_p_zz_, //!< <a href="../target/aarch64/smaxp_z_p_zz.html#smaxp_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_smaxv_r_p_z_, //!< <a href="../target/aarch64/smaxv_r_p_z.html#smaxv_r_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_smin_z_p_zz_, //!< <a href="../target/aarch64/smin_z_p_zz.html#smin_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_smin_z_zi_, //!< <a href="../target/aarch64/smin_z_zi.html#smin_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_sminp_z_p_zz_, //!< <a href="../target/aarch64/sminp_z_p_zz.html#sminp_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sminv_r_p_z_, //!< <a href="../target/aarch64/sminv_r_p_z.html#sminv_r_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_smlalb_z_zzz_, //!< <a href="../target/aarch64/smlalb_z_zzz.html#smlalb_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_smlalb_z_zzzi_s, //!< <a href="../target/aarch64/smlalb_z_zzzi.html#smlalb_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_smlalb_z_zzzi_d, //!< <a href="../target/aarch64/smlalb_z_zzzi.html#smlalb_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_smlalt_z_zzz_, //!< <a href="../target/aarch64/smlalt_z_zzz.html#smlalt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_smlalt_z_zzzi_s, //!< <a href="../target/aarch64/smlalt_z_zzzi.html#smlalt_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_smlalt_z_zzzi_d, //!< <a href="../target/aarch64/smlalt_z_zzzi.html#smlalt_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_smlslb_z_zzz_, //!< <a href="../target/aarch64/smlslb_z_zzz.html#smlslb_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_smlslb_z_zzzi_s, //!< <a href="../target/aarch64/smlslb_z_zzzi.html#smlslb_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_smlslb_z_zzzi_d, //!< <a href="../target/aarch64/smlslb_z_zzzi.html#smlslb_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_smlslt_z_zzz_, //!< <a href="../target/aarch64/smlslt_z_zzz.html#smlslt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_smlslt_z_zzzi_s, //!< <a href="../target/aarch64/smlslt_z_zzzi.html#smlslt_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_smlslt_z_zzzi_d, //!< <a href="../target/aarch64/smlslt_z_zzzi.html#smlslt_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_smmla_z_zzz_, //!< <a href="../target/aarch64/smmla_z_zzz.html#smmla_z_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_smulh_z_p_zz_, //!< <a href="../target/aarch64/smulh_z_p_zz.html#smulh_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_smulh_z_zz_, //!< <a href="../target/aarch64/smulh_z_zz.html#smulh_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_smullb_z_zz_, //!< <a href="../target/aarch64/smullb_z_zz.html#smullb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_smullb_z_zzi_s, //!< <a href="../target/aarch64/smullb_z_zzi.html#smullb_z_zzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_smullb_z_zzi_d, //!< <a href="../target/aarch64/smullb_z_zzi.html#smullb_z_zzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_smullt_z_zz_, //!< <a href="../target/aarch64/smullt_z_zz.html#smullt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_smullt_z_zzi_s, //!< <a href="../target/aarch64/smullt_z_zzi.html#smullt_z_zzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_smullt_z_zzi_d, //!< <a href="../target/aarch64/smullt_z_zzi.html#smullt_z_zzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_splice_z_p_zz_con, //!< <a href="../target/aarch64/splice_z_p_zz.html#splice_z_p_zz_con">Constructive</a>
  AMED_AARCH64_CCLASS_splice_z_p_zz_des, //!< <a href="../target/aarch64/splice_z_p_zz.html#splice_z_p_zz_des">Destructive</a>
  AMED_AARCH64_CCLASS_sqabs_z_p_z_, //!< <a href="../target/aarch64/sqabs_z_p_z.html#sqabs_z_p_z_">SVE2</a>
  AMED_AARCH64_CCLASS_sqadd_z_p_zz_, //!< <a href="../target/aarch64/sqadd_z_p_zz.html#sqadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqadd_z_zi_, //!< <a href="../target/aarch64/sqadd_z_zi.html#sqadd_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_sqadd_z_zz_, //!< <a href="../target/aarch64/sqadd_z_zz.html#sqadd_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_sqcadd_z_zz_, //!< <a href="../target/aarch64/sqcadd_z_zz.html#sqcadd_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqdecb_r_rs_sx, //!< <a href="../target/aarch64/sqdecb_r_rs.html#sqdecb_r_rs_sx">32-bit</a>
  AMED_AARCH64_CCLASS_sqdecb_r_rs_x, //!< <a href="../target/aarch64/sqdecb_r_rs.html#sqdecb_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_sqdecd_r_rs_sx, //!< <a href="../target/aarch64/sqdecd_r_rs.html#sqdecd_r_rs_sx">32-bit</a>
  AMED_AARCH64_CCLASS_sqdecd_r_rs_x, //!< <a href="../target/aarch64/sqdecd_r_rs.html#sqdecd_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_sqdecd_z_zs_, //!< <a href="../target/aarch64/sqdecd_z_zs.html#sqdecd_z_zs_">SVE</a>
  AMED_AARCH64_CCLASS_sqdech_r_rs_sx, //!< <a href="../target/aarch64/sqdech_r_rs.html#sqdech_r_rs_sx">32-bit</a>
  AMED_AARCH64_CCLASS_sqdech_r_rs_x, //!< <a href="../target/aarch64/sqdech_r_rs.html#sqdech_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_sqdech_z_zs_, //!< <a href="../target/aarch64/sqdech_z_zs.html#sqdech_z_zs_">SVE</a>
  AMED_AARCH64_CCLASS_sqdecp_r_p_r_sx, //!< <a href="../target/aarch64/sqdecp_r_p_r.html#sqdecp_r_p_r_sx">32-bit</a>
  AMED_AARCH64_CCLASS_sqdecp_r_p_r_x, //!< <a href="../target/aarch64/sqdecp_r_p_r.html#sqdecp_r_p_r_x">64-bit</a>
  AMED_AARCH64_CCLASS_sqdecp_z_p_z_, //!< <a href="../target/aarch64/sqdecp_z_p_z.html#sqdecp_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_sqdecw_r_rs_sx, //!< <a href="../target/aarch64/sqdecw_r_rs.html#sqdecw_r_rs_sx">32-bit</a>
  AMED_AARCH64_CCLASS_sqdecw_r_rs_x, //!< <a href="../target/aarch64/sqdecw_r_rs.html#sqdecw_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_sqdecw_z_zs_, //!< <a href="../target/aarch64/sqdecw_z_zs.html#sqdecw_z_zs_">SVE</a>
  AMED_AARCH64_CCLASS_sqdmlalb_z_zzz_, //!< <a href="../target/aarch64/sqdmlalb_z_zzz.html#sqdmlalb_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqdmlalb_z_zzzi_s, //!< <a href="../target/aarch64/sqdmlalb_z_zzzi.html#sqdmlalb_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_sqdmlalb_z_zzzi_d, //!< <a href="../target/aarch64/sqdmlalb_z_zzzi.html#sqdmlalb_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_sqdmlalbt_z_zzz_, //!< <a href="../target/aarch64/sqdmlalbt_z_zzz.html#sqdmlalbt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqdmlalt_z_zzz_, //!< <a href="../target/aarch64/sqdmlalt_z_zzz.html#sqdmlalt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqdmlalt_z_zzzi_s, //!< <a href="../target/aarch64/sqdmlalt_z_zzzi.html#sqdmlalt_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_sqdmlalt_z_zzzi_d, //!< <a href="../target/aarch64/sqdmlalt_z_zzzi.html#sqdmlalt_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_sqdmlslb_z_zzz_, //!< <a href="../target/aarch64/sqdmlslb_z_zzz.html#sqdmlslb_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqdmlslb_z_zzzi_s, //!< <a href="../target/aarch64/sqdmlslb_z_zzzi.html#sqdmlslb_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_sqdmlslb_z_zzzi_d, //!< <a href="../target/aarch64/sqdmlslb_z_zzzi.html#sqdmlslb_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_sqdmlslbt_z_zzz_, //!< <a href="../target/aarch64/sqdmlslbt_z_zzz.html#sqdmlslbt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqdmlslt_z_zzz_, //!< <a href="../target/aarch64/sqdmlslt_z_zzz.html#sqdmlslt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqdmlslt_z_zzzi_s, //!< <a href="../target/aarch64/sqdmlslt_z_zzzi.html#sqdmlslt_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_sqdmlslt_z_zzzi_d, //!< <a href="../target/aarch64/sqdmlslt_z_zzzi.html#sqdmlslt_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_sqdmulh_z_zz_, //!< <a href="../target/aarch64/sqdmulh_z_zz.html#sqdmulh_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqdmulh_z_zzi_h, //!< <a href="../target/aarch64/sqdmulh_z_zzi.html#sqdmulh_z_zzi_h">16-bit</a>
  AMED_AARCH64_CCLASS_sqdmulh_z_zzi_s, //!< <a href="../target/aarch64/sqdmulh_z_zzi.html#sqdmulh_z_zzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_sqdmulh_z_zzi_d, //!< <a href="../target/aarch64/sqdmulh_z_zzi.html#sqdmulh_z_zzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_sqdmullb_z_zz_, //!< <a href="../target/aarch64/sqdmullb_z_zz.html#sqdmullb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqdmullb_z_zzi_s, //!< <a href="../target/aarch64/sqdmullb_z_zzi.html#sqdmullb_z_zzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_sqdmullb_z_zzi_d, //!< <a href="../target/aarch64/sqdmullb_z_zzi.html#sqdmullb_z_zzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_sqdmullt_z_zz_, //!< <a href="../target/aarch64/sqdmullt_z_zz.html#sqdmullt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqdmullt_z_zzi_s, //!< <a href="../target/aarch64/sqdmullt_z_zzi.html#sqdmullt_z_zzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_sqdmullt_z_zzi_d, //!< <a href="../target/aarch64/sqdmullt_z_zzi.html#sqdmullt_z_zzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_sqincb_r_rs_sx, //!< <a href="../target/aarch64/sqincb_r_rs.html#sqincb_r_rs_sx">32-bit</a>
  AMED_AARCH64_CCLASS_sqincb_r_rs_x, //!< <a href="../target/aarch64/sqincb_r_rs.html#sqincb_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_sqincd_r_rs_sx, //!< <a href="../target/aarch64/sqincd_r_rs.html#sqincd_r_rs_sx">32-bit</a>
  AMED_AARCH64_CCLASS_sqincd_r_rs_x, //!< <a href="../target/aarch64/sqincd_r_rs.html#sqincd_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_sqincd_z_zs_, //!< <a href="../target/aarch64/sqincd_z_zs.html#sqincd_z_zs_">SVE</a>
  AMED_AARCH64_CCLASS_sqinch_r_rs_sx, //!< <a href="../target/aarch64/sqinch_r_rs.html#sqinch_r_rs_sx">32-bit</a>
  AMED_AARCH64_CCLASS_sqinch_r_rs_x, //!< <a href="../target/aarch64/sqinch_r_rs.html#sqinch_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_sqinch_z_zs_, //!< <a href="../target/aarch64/sqinch_z_zs.html#sqinch_z_zs_">SVE</a>
  AMED_AARCH64_CCLASS_sqincp_r_p_r_sx, //!< <a href="../target/aarch64/sqincp_r_p_r.html#sqincp_r_p_r_sx">32-bit</a>
  AMED_AARCH64_CCLASS_sqincp_r_p_r_x, //!< <a href="../target/aarch64/sqincp_r_p_r.html#sqincp_r_p_r_x">64-bit</a>
  AMED_AARCH64_CCLASS_sqincp_z_p_z_, //!< <a href="../target/aarch64/sqincp_z_p_z.html#sqincp_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_sqincw_r_rs_sx, //!< <a href="../target/aarch64/sqincw_r_rs.html#sqincw_r_rs_sx">32-bit</a>
  AMED_AARCH64_CCLASS_sqincw_r_rs_x, //!< <a href="../target/aarch64/sqincw_r_rs.html#sqincw_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_sqincw_z_zs_, //!< <a href="../target/aarch64/sqincw_z_zs.html#sqincw_z_zs_">SVE</a>
  AMED_AARCH64_CCLASS_sqneg_z_p_z_, //!< <a href="../target/aarch64/sqneg_z_p_z.html#sqneg_z_p_z_">SVE2</a>
  AMED_AARCH64_CCLASS_sqrdcmlah_z_zzz_, //!< <a href="../target/aarch64/sqrdcmlah_z_zzz.html#sqrdcmlah_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqrdcmlah_z_zzzi_h, //!< <a href="../target/aarch64/sqrdcmlah_z_zzzi.html#sqrdcmlah_z_zzzi_h">16-bit</a>
  AMED_AARCH64_CCLASS_sqrdcmlah_z_zzzi_s, //!< <a href="../target/aarch64/sqrdcmlah_z_zzzi.html#sqrdcmlah_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_sqrdmlah_z_zzz_, //!< <a href="../target/aarch64/sqrdmlah_z_zzz.html#sqrdmlah_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqrdmlah_z_zzzi_h, //!< <a href="../target/aarch64/sqrdmlah_z_zzzi.html#sqrdmlah_z_zzzi_h">16-bit</a>
  AMED_AARCH64_CCLASS_sqrdmlah_z_zzzi_s, //!< <a href="../target/aarch64/sqrdmlah_z_zzzi.html#sqrdmlah_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_sqrdmlah_z_zzzi_d, //!< <a href="../target/aarch64/sqrdmlah_z_zzzi.html#sqrdmlah_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_sqrdmlsh_z_zzz_, //!< <a href="../target/aarch64/sqrdmlsh_z_zzz.html#sqrdmlsh_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqrdmlsh_z_zzzi_h, //!< <a href="../target/aarch64/sqrdmlsh_z_zzzi.html#sqrdmlsh_z_zzzi_h">16-bit</a>
  AMED_AARCH64_CCLASS_sqrdmlsh_z_zzzi_s, //!< <a href="../target/aarch64/sqrdmlsh_z_zzzi.html#sqrdmlsh_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_sqrdmlsh_z_zzzi_d, //!< <a href="../target/aarch64/sqrdmlsh_z_zzzi.html#sqrdmlsh_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_sqrdmulh_z_zz_, //!< <a href="../target/aarch64/sqrdmulh_z_zz.html#sqrdmulh_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqrdmulh_z_zzi_h, //!< <a href="../target/aarch64/sqrdmulh_z_zzi.html#sqrdmulh_z_zzi_h">16-bit</a>
  AMED_AARCH64_CCLASS_sqrdmulh_z_zzi_s, //!< <a href="../target/aarch64/sqrdmulh_z_zzi.html#sqrdmulh_z_zzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_sqrdmulh_z_zzi_d, //!< <a href="../target/aarch64/sqrdmulh_z_zzi.html#sqrdmulh_z_zzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_sqrshl_z_p_zz_, //!< <a href="../target/aarch64/sqrshl_z_p_zz.html#sqrshl_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqrshlr_z_p_zz_, //!< <a href="../target/aarch64/sqrshlr_z_p_zz.html#sqrshlr_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqrshrnb_z_zi_, //!< <a href="../target/aarch64/sqrshrnb_z_zi.html#sqrshrnb_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_sqrshrnt_z_zi_, //!< <a href="../target/aarch64/sqrshrnt_z_zi.html#sqrshrnt_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_sqrshrunb_z_zi_, //!< <a href="../target/aarch64/sqrshrunb_z_zi.html#sqrshrunb_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_sqrshrunt_z_zi_, //!< <a href="../target/aarch64/sqrshrunt_z_zi.html#sqrshrunt_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_sqshl_z_p_zi_, //!< <a href="../target/aarch64/sqshl_z_p_zi.html#sqshl_z_p_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_sqshl_z_p_zz_, //!< <a href="../target/aarch64/sqshl_z_p_zz.html#sqshl_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqshlr_z_p_zz_, //!< <a href="../target/aarch64/sqshlr_z_p_zz.html#sqshlr_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqshlu_z_p_zi_, //!< <a href="../target/aarch64/sqshlu_z_p_zi.html#sqshlu_z_p_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_sqshrnb_z_zi_, //!< <a href="../target/aarch64/sqshrnb_z_zi.html#sqshrnb_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_sqshrnt_z_zi_, //!< <a href="../target/aarch64/sqshrnt_z_zi.html#sqshrnt_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_sqshrunb_z_zi_, //!< <a href="../target/aarch64/sqshrunb_z_zi.html#sqshrunb_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_sqshrunt_z_zi_, //!< <a href="../target/aarch64/sqshrunt_z_zi.html#sqshrunt_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_sqsub_z_p_zz_, //!< <a href="../target/aarch64/sqsub_z_p_zz.html#sqsub_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqsub_z_zi_, //!< <a href="../target/aarch64/sqsub_z_zi.html#sqsub_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_sqsub_z_zz_, //!< <a href="../target/aarch64/sqsub_z_zz.html#sqsub_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_sqsubr_z_p_zz_, //!< <a href="../target/aarch64/sqsubr_z_p_zz.html#sqsubr_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqxtnb_z_zz_, //!< <a href="../target/aarch64/sqxtnb_z_zz.html#sqxtnb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqxtnt_z_zz_, //!< <a href="../target/aarch64/sqxtnt_z_zz.html#sqxtnt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqxtunb_z_zz_, //!< <a href="../target/aarch64/sqxtunb_z_zz.html#sqxtunb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sqxtunt_z_zz_, //!< <a href="../target/aarch64/sqxtunt_z_zz.html#sqxtunt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_srhadd_z_p_zz_, //!< <a href="../target/aarch64/srhadd_z_p_zz.html#srhadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sri_z_zzi_, //!< <a href="../target/aarch64/sri_z_zzi.html#sri_z_zzi_">SVE2</a>
  AMED_AARCH64_CCLASS_srshl_z_p_zz_, //!< <a href="../target/aarch64/srshl_z_p_zz.html#srshl_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_srshlr_z_p_zz_, //!< <a href="../target/aarch64/srshlr_z_p_zz.html#srshlr_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_srshr_z_p_zi_, //!< <a href="../target/aarch64/srshr_z_p_zi.html#srshr_z_p_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_srsra_z_zi_, //!< <a href="../target/aarch64/srsra_z_zi.html#srsra_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_sshllb_z_zi_, //!< <a href="../target/aarch64/sshllb_z_zi.html#sshllb_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_sshllt_z_zi_, //!< <a href="../target/aarch64/sshllt_z_zi.html#sshllt_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_ssra_z_zi_, //!< <a href="../target/aarch64/ssra_z_zi.html#ssra_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_ssublb_z_zz_, //!< <a href="../target/aarch64/ssublb_z_zz.html#ssublb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_ssublbt_z_zz_, //!< <a href="../target/aarch64/ssublbt_z_zz.html#ssublbt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_ssublt_z_zz_, //!< <a href="../target/aarch64/ssublt_z_zz.html#ssublt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_ssubltb_z_zz_, //!< <a href="../target/aarch64/ssubltb_z_zz.html#ssubltb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_ssubwb_z_zz_, //!< <a href="../target/aarch64/ssubwb_z_zz.html#ssubwb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_ssubwt_z_zz_, //!< <a href="../target/aarch64/ssubwt_z_zz.html#ssubwt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_st1b_z_p_ai_s, //!< <a href="../target/aarch64/st1b_z_p_ai.html#st1b_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_st1b_z_p_ai_d, //!< <a href="../target/aarch64/st1b_z_p_ai.html#st1b_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_st1b_z_p_bi_, //!< <a href="../target/aarch64/st1b_z_p_bi.html#st1b_z_p_bi_">SVE</a>
  AMED_AARCH64_CCLASS_st1b_z_p_br_, //!< <a href="../target/aarch64/st1b_z_p_br.html#st1b_z_p_br_">SVE</a>
  AMED_AARCH64_CCLASS_st1b_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/st1b_z_p_bz.html#st1b_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_st1b_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/st1b_z_p_bz.html#st1b_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_st1b_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/st1b_z_p_bz.html#st1b_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_st1d_z_p_ai_d, //!< <a href="../target/aarch64/st1d_z_p_ai.html#st1d_z_p_ai_d">SVE</a>
  AMED_AARCH64_CCLASS_st1d_z_p_bi_, //!< <a href="../target/aarch64/st1d_z_p_bi.html#st1d_z_p_bi_">SVE</a>
  AMED_AARCH64_CCLASS_st1d_z_p_br_, //!< <a href="../target/aarch64/st1d_z_p_br.html#st1d_z_p_br_">SVE</a>
  AMED_AARCH64_CCLASS_st1d_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/st1d_z_p_bz.html#st1d_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_st1d_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/st1d_z_p_bz.html#st1d_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_st1d_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/st1d_z_p_bz.html#st1d_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_st1d_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/st1d_z_p_bz.html#st1d_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_st1h_z_p_ai_s, //!< <a href="../target/aarch64/st1h_z_p_ai.html#st1h_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_st1h_z_p_ai_d, //!< <a href="../target/aarch64/st1h_z_p_ai.html#st1h_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_st1h_z_p_bi_, //!< <a href="../target/aarch64/st1h_z_p_bi.html#st1h_z_p_bi_">SVE</a>
  AMED_AARCH64_CCLASS_st1h_z_p_br_, //!< <a href="../target/aarch64/st1h_z_p_br.html#st1h_z_p_br_">SVE</a>
  AMED_AARCH64_CCLASS_st1h_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/st1h_z_p_bz.html#st1h_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_CCLASS_st1h_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/st1h_z_p_bz.html#st1h_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_st1h_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/st1h_z_p_bz.html#st1h_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_st1h_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/st1h_z_p_bz.html#st1h_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_st1h_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/st1h_z_p_bz.html#st1h_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_st1h_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/st1h_z_p_bz.html#st1h_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_st1w_z_p_ai_s, //!< <a href="../target/aarch64/st1w_z_p_ai.html#st1w_z_p_ai_s">32-bit element</a>
  AMED_AARCH64_CCLASS_st1w_z_p_ai_d, //!< <a href="../target/aarch64/st1w_z_p_ai.html#st1w_z_p_ai_d">64-bit element</a>
  AMED_AARCH64_CCLASS_st1w_z_p_bi_, //!< <a href="../target/aarch64/st1w_z_p_bi.html#st1w_z_p_bi_">SVE</a>
  AMED_AARCH64_CCLASS_st1w_z_p_br_, //!< <a href="../target/aarch64/st1w_z_p_br.html#st1w_z_p_br_">SVE</a>
  AMED_AARCH64_CCLASS_st1w_z_p_bz_s_x32_scaled, //!< <a href="../target/aarch64/st1w_z_p_bz.html#st1w_z_p_bz_s_x32_scaled">32-bit scaled offset</a>
  AMED_AARCH64_CCLASS_st1w_z_p_bz_d_x32_scaled, //!< <a href="../target/aarch64/st1w_z_p_bz.html#st1w_z_p_bz_d_x32_scaled">32-bit unpacked scaled offset</a>
  AMED_AARCH64_CCLASS_st1w_z_p_bz_d_x32_unscaled, //!< <a href="../target/aarch64/st1w_z_p_bz.html#st1w_z_p_bz_d_x32_unscaled">32-bit unpacked unscaled offset</a>
  AMED_AARCH64_CCLASS_st1w_z_p_bz_s_x32_unscaled, //!< <a href="../target/aarch64/st1w_z_p_bz.html#st1w_z_p_bz_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_st1w_z_p_bz_d_64_scaled, //!< <a href="../target/aarch64/st1w_z_p_bz.html#st1w_z_p_bz_d_64_scaled">64-bit scaled offset</a>
  AMED_AARCH64_CCLASS_st1w_z_p_bz_d_64_unscaled, //!< <a href="../target/aarch64/st1w_z_p_bz.html#st1w_z_p_bz_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_st2b_z_p_bi_contiguous, //!< <a href="../target/aarch64/st2b_z_p_bi.html#st2b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st2b_z_p_br_contiguous, //!< <a href="../target/aarch64/st2b_z_p_br.html#st2b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st2d_z_p_bi_contiguous, //!< <a href="../target/aarch64/st2d_z_p_bi.html#st2d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st2d_z_p_br_contiguous, //!< <a href="../target/aarch64/st2d_z_p_br.html#st2d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st2h_z_p_bi_contiguous, //!< <a href="../target/aarch64/st2h_z_p_bi.html#st2h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st2h_z_p_br_contiguous, //!< <a href="../target/aarch64/st2h_z_p_br.html#st2h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st2w_z_p_bi_contiguous, //!< <a href="../target/aarch64/st2w_z_p_bi.html#st2w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st2w_z_p_br_contiguous, //!< <a href="../target/aarch64/st2w_z_p_br.html#st2w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st3b_z_p_bi_contiguous, //!< <a href="../target/aarch64/st3b_z_p_bi.html#st3b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st3b_z_p_br_contiguous, //!< <a href="../target/aarch64/st3b_z_p_br.html#st3b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st3d_z_p_bi_contiguous, //!< <a href="../target/aarch64/st3d_z_p_bi.html#st3d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st3d_z_p_br_contiguous, //!< <a href="../target/aarch64/st3d_z_p_br.html#st3d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st3h_z_p_bi_contiguous, //!< <a href="../target/aarch64/st3h_z_p_bi.html#st3h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st3h_z_p_br_contiguous, //!< <a href="../target/aarch64/st3h_z_p_br.html#st3h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st3w_z_p_bi_contiguous, //!< <a href="../target/aarch64/st3w_z_p_bi.html#st3w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st3w_z_p_br_contiguous, //!< <a href="../target/aarch64/st3w_z_p_br.html#st3w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st4b_z_p_bi_contiguous, //!< <a href="../target/aarch64/st4b_z_p_bi.html#st4b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st4b_z_p_br_contiguous, //!< <a href="../target/aarch64/st4b_z_p_br.html#st4b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st4d_z_p_bi_contiguous, //!< <a href="../target/aarch64/st4d_z_p_bi.html#st4d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st4d_z_p_br_contiguous, //!< <a href="../target/aarch64/st4d_z_p_br.html#st4d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st4h_z_p_bi_contiguous, //!< <a href="../target/aarch64/st4h_z_p_bi.html#st4h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st4h_z_p_br_contiguous, //!< <a href="../target/aarch64/st4h_z_p_br.html#st4h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st4w_z_p_bi_contiguous, //!< <a href="../target/aarch64/st4w_z_p_bi.html#st4w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_st4w_z_p_br_contiguous, //!< <a href="../target/aarch64/st4w_z_p_br.html#st4w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_stnt1b_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/stnt1b_z_p_ar.html#stnt1b_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_stnt1b_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/stnt1b_z_p_ar.html#stnt1b_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_stnt1b_z_p_bi_contiguous, //!< <a href="../target/aarch64/stnt1b_z_p_bi.html#stnt1b_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_stnt1b_z_p_br_contiguous, //!< <a href="../target/aarch64/stnt1b_z_p_br.html#stnt1b_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_stnt1d_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/stnt1d_z_p_ar.html#stnt1d_z_p_ar_d_64_unscaled">SVE2</a>
  AMED_AARCH64_CCLASS_stnt1d_z_p_bi_contiguous, //!< <a href="../target/aarch64/stnt1d_z_p_bi.html#stnt1d_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_stnt1d_z_p_br_contiguous, //!< <a href="../target/aarch64/stnt1d_z_p_br.html#stnt1d_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_stnt1h_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/stnt1h_z_p_ar.html#stnt1h_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_stnt1h_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/stnt1h_z_p_ar.html#stnt1h_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_stnt1h_z_p_bi_contiguous, //!< <a href="../target/aarch64/stnt1h_z_p_bi.html#stnt1h_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_stnt1h_z_p_br_contiguous, //!< <a href="../target/aarch64/stnt1h_z_p_br.html#stnt1h_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_stnt1w_z_p_ar_s_x32_unscaled, //!< <a href="../target/aarch64/stnt1w_z_p_ar.html#stnt1w_z_p_ar_s_x32_unscaled">32-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_stnt1w_z_p_ar_d_64_unscaled, //!< <a href="../target/aarch64/stnt1w_z_p_ar.html#stnt1w_z_p_ar_d_64_unscaled">64-bit unscaled offset</a>
  AMED_AARCH64_CCLASS_stnt1w_z_p_bi_contiguous, //!< <a href="../target/aarch64/stnt1w_z_p_bi.html#stnt1w_z_p_bi_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_stnt1w_z_p_br_contiguous, //!< <a href="../target/aarch64/stnt1w_z_p_br.html#stnt1w_z_p_br_contiguous">SVE</a>
  AMED_AARCH64_CCLASS_str_p_bi_, //!< <a href="../target/aarch64/str_p_bi.html#str_p_bi_">SVE</a>
  AMED_AARCH64_CCLASS_str_z_bi_, //!< <a href="../target/aarch64/str_z_bi.html#str_z_bi_">SVE</a>
  AMED_AARCH64_CCLASS_sub_z_p_zz_, //!< <a href="../target/aarch64/sub_z_p_zz.html#sub_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_sub_z_zi_, //!< <a href="../target/aarch64/sub_z_zi.html#sub_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_sub_z_zz_, //!< <a href="../target/aarch64/sub_z_zz.html#sub_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_subhnb_z_zz_, //!< <a href="../target/aarch64/subhnb_z_zz.html#subhnb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_subhnt_z_zz_, //!< <a href="../target/aarch64/subhnt_z_zz.html#subhnt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_subr_z_p_zz_, //!< <a href="../target/aarch64/subr_z_p_zz.html#subr_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_subr_z_zi_, //!< <a href="../target/aarch64/subr_z_zi.html#subr_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_sudot_z_zzzi_s, //!< <a href="../target/aarch64/sudot_z_zzzi.html#sudot_z_zzzi_s">SVE</a>
  AMED_AARCH64_CCLASS_sunpkhi_z_z_, //!< <a href="../target/aarch64/sunpkhi_z_z.html#sunpkhi_z_z_">High half</a>
  AMED_AARCH64_CCLASS_sunpklo_z_z_, //!< <a href="../target/aarch64/sunpkhi_z_z.html#sunpklo_z_z_">Low half</a>
  AMED_AARCH64_CCLASS_suqadd_z_p_zz_, //!< <a href="../target/aarch64/suqadd_z_p_zz.html#suqadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_sxtb_z_p_z_, //!< <a href="../target/aarch64/sxtb_z_p_z.html#sxtb_z_p_z_">Byte</a>
  AMED_AARCH64_CCLASS_sxth_z_p_z_, //!< <a href="../target/aarch64/sxtb_z_p_z.html#sxth_z_p_z_">Halfword</a>
  AMED_AARCH64_CCLASS_sxtw_z_p_z_, //!< <a href="../target/aarch64/sxtb_z_p_z.html#sxtw_z_p_z_">Word</a>
  AMED_AARCH64_CCLASS_tbl_z_zz_1, //!< <a href="../target/aarch64/tbl_z_zz.html#tbl_z_zz_1">SVE</a>
  AMED_AARCH64_CCLASS_tbl_z_zz_2, //!< <a href="../target/aarch64/tbl_z_zz.html#tbl_z_zz_2">SVE2</a>
  AMED_AARCH64_CCLASS_tbx_z_zz_, //!< <a href="../target/aarch64/tbx_z_zz.html#tbx_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_trn1_p_pp_, //!< <a href="../target/aarch64/trn1_p_pp.html#trn1_p_pp_">Even</a>
  AMED_AARCH64_CCLASS_trn2_p_pp_, //!< <a href="../target/aarch64/trn1_p_pp.html#trn2_p_pp_">Odd</a>
  AMED_AARCH64_CCLASS_trn1_z_zz_, //!< <a href="../target/aarch64/trn1_z_zz.html#trn1_z_zz_">Even</a>
  AMED_AARCH64_CCLASS_trn1_z_zz_q, //!< <a href="../target/aarch64/trn1_z_zz.html#trn1_z_zz_q">Even (quadwords)</a>
  AMED_AARCH64_CCLASS_trn2_z_zz_, //!< <a href="../target/aarch64/trn1_z_zz.html#trn2_z_zz_">Odd</a>
  AMED_AARCH64_CCLASS_trn2_z_zz_q, //!< <a href="../target/aarch64/trn1_z_zz.html#trn2_z_zz_q">Odd (quadwords)</a>
  AMED_AARCH64_CCLASS_uaba_z_zzz_, //!< <a href="../target/aarch64/uaba_z_zzz.html#uaba_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_uabalb_z_zzz_, //!< <a href="../target/aarch64/uabalb_z_zzz.html#uabalb_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_uabalt_z_zzz_, //!< <a href="../target/aarch64/uabalt_z_zzz.html#uabalt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_uabd_z_p_zz_, //!< <a href="../target/aarch64/uabd_z_p_zz.html#uabd_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_uabdlb_z_zz_, //!< <a href="../target/aarch64/uabdlb_z_zz.html#uabdlb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uabdlt_z_zz_, //!< <a href="../target/aarch64/uabdlt_z_zz.html#uabdlt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uadalp_z_p_z_, //!< <a href="../target/aarch64/uadalp_z_p_z.html#uadalp_z_p_z_">SVE2</a>
  AMED_AARCH64_CCLASS_uaddlb_z_zz_, //!< <a href="../target/aarch64/uaddlb_z_zz.html#uaddlb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uaddlt_z_zz_, //!< <a href="../target/aarch64/uaddlt_z_zz.html#uaddlt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uaddv_r_p_z_, //!< <a href="../target/aarch64/uaddv_r_p_z.html#uaddv_r_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_uaddwb_z_zz_, //!< <a href="../target/aarch64/uaddwb_z_zz.html#uaddwb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uaddwt_z_zz_, //!< <a href="../target/aarch64/uaddwt_z_zz.html#uaddwt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_ucvtf_z_p_z_h2fp16, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_h2fp16">16-bit to half-precision</a>
  AMED_AARCH64_CCLASS_ucvtf_z_p_z_w2fp16, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_w2fp16">32-bit to half-precision</a>
  AMED_AARCH64_CCLASS_ucvtf_z_p_z_w2s, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_w2s">32-bit to single-precision</a>
  AMED_AARCH64_CCLASS_ucvtf_z_p_z_w2d, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_w2d">32-bit to double-precision</a>
  AMED_AARCH64_CCLASS_ucvtf_z_p_z_x2fp16, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_x2fp16">64-bit to half-precision</a>
  AMED_AARCH64_CCLASS_ucvtf_z_p_z_x2s, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_x2s">64-bit to single-precision</a>
  AMED_AARCH64_CCLASS_ucvtf_z_p_z_x2d, //!< <a href="../target/aarch64/ucvtf_z_p_z.html#ucvtf_z_p_z_x2d">64-bit to double-precision</a>
  AMED_AARCH64_CCLASS_udiv_z_p_zz_, //!< <a href="../target/aarch64/udiv_z_p_zz.html#udiv_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_udivr_z_p_zz_, //!< <a href="../target/aarch64/udivr_z_p_zz.html#udivr_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_udot_z_zzz_, //!< <a href="../target/aarch64/udot_z_zzz.html#udot_z_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_udot_z_zzzi_s, //!< <a href="../target/aarch64/udot_z_zzzi.html#udot_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_udot_z_zzzi_d, //!< <a href="../target/aarch64/udot_z_zzzi.html#udot_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_uhadd_z_p_zz_, //!< <a href="../target/aarch64/uhadd_z_p_zz.html#uhadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uhsub_z_p_zz_, //!< <a href="../target/aarch64/uhsub_z_p_zz.html#uhsub_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uhsubr_z_p_zz_, //!< <a href="../target/aarch64/uhsubr_z_p_zz.html#uhsubr_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_umax_z_p_zz_, //!< <a href="../target/aarch64/umax_z_p_zz.html#umax_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_umax_z_zi_, //!< <a href="../target/aarch64/umax_z_zi.html#umax_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_umaxp_z_p_zz_, //!< <a href="../target/aarch64/umaxp_z_p_zz.html#umaxp_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_umaxv_r_p_z_, //!< <a href="../target/aarch64/umaxv_r_p_z.html#umaxv_r_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_umin_z_p_zz_, //!< <a href="../target/aarch64/umin_z_p_zz.html#umin_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_umin_z_zi_, //!< <a href="../target/aarch64/umin_z_zi.html#umin_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_uminp_z_p_zz_, //!< <a href="../target/aarch64/uminp_z_p_zz.html#uminp_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uminv_r_p_z_, //!< <a href="../target/aarch64/uminv_r_p_z.html#uminv_r_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_umlalb_z_zzz_, //!< <a href="../target/aarch64/umlalb_z_zzz.html#umlalb_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_umlalb_z_zzzi_s, //!< <a href="../target/aarch64/umlalb_z_zzzi.html#umlalb_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_umlalb_z_zzzi_d, //!< <a href="../target/aarch64/umlalb_z_zzzi.html#umlalb_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_umlalt_z_zzz_, //!< <a href="../target/aarch64/umlalt_z_zzz.html#umlalt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_umlalt_z_zzzi_s, //!< <a href="../target/aarch64/umlalt_z_zzzi.html#umlalt_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_umlalt_z_zzzi_d, //!< <a href="../target/aarch64/umlalt_z_zzzi.html#umlalt_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_umlslb_z_zzz_, //!< <a href="../target/aarch64/umlslb_z_zzz.html#umlslb_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_umlslb_z_zzzi_s, //!< <a href="../target/aarch64/umlslb_z_zzzi.html#umlslb_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_umlslb_z_zzzi_d, //!< <a href="../target/aarch64/umlslb_z_zzzi.html#umlslb_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_umlslt_z_zzz_, //!< <a href="../target/aarch64/umlslt_z_zzz.html#umlslt_z_zzz_">SVE2</a>
  AMED_AARCH64_CCLASS_umlslt_z_zzzi_s, //!< <a href="../target/aarch64/umlslt_z_zzzi.html#umlslt_z_zzzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_umlslt_z_zzzi_d, //!< <a href="../target/aarch64/umlslt_z_zzzi.html#umlslt_z_zzzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_ummla_z_zzz_, //!< <a href="../target/aarch64/ummla_z_zzz.html#ummla_z_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_umulh_z_p_zz_, //!< <a href="../target/aarch64/umulh_z_p_zz.html#umulh_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_umulh_z_zz_, //!< <a href="../target/aarch64/umulh_z_zz.html#umulh_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_umullb_z_zz_, //!< <a href="../target/aarch64/umullb_z_zz.html#umullb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_umullb_z_zzi_s, //!< <a href="../target/aarch64/umullb_z_zzi.html#umullb_z_zzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_umullb_z_zzi_d, //!< <a href="../target/aarch64/umullb_z_zzi.html#umullb_z_zzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_umullt_z_zz_, //!< <a href="../target/aarch64/umullt_z_zz.html#umullt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_umullt_z_zzi_s, //!< <a href="../target/aarch64/umullt_z_zzi.html#umullt_z_zzi_s">32-bit</a>
  AMED_AARCH64_CCLASS_umullt_z_zzi_d, //!< <a href="../target/aarch64/umullt_z_zzi.html#umullt_z_zzi_d">64-bit</a>
  AMED_AARCH64_CCLASS_uqadd_z_p_zz_, //!< <a href="../target/aarch64/uqadd_z_p_zz.html#uqadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uqadd_z_zi_, //!< <a href="../target/aarch64/uqadd_z_zi.html#uqadd_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_uqadd_z_zz_, //!< <a href="../target/aarch64/uqadd_z_zz.html#uqadd_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_uqdecb_r_rs_uw, //!< <a href="../target/aarch64/uqdecb_r_rs.html#uqdecb_r_rs_uw">32-bit</a>
  AMED_AARCH64_CCLASS_uqdecb_r_rs_x, //!< <a href="../target/aarch64/uqdecb_r_rs.html#uqdecb_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_uqdecd_r_rs_uw, //!< <a href="../target/aarch64/uqdecd_r_rs.html#uqdecd_r_rs_uw">32-bit</a>
  AMED_AARCH64_CCLASS_uqdecd_r_rs_x, //!< <a href="../target/aarch64/uqdecd_r_rs.html#uqdecd_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_uqdecd_z_zs_, //!< <a href="../target/aarch64/uqdecd_z_zs.html#uqdecd_z_zs_">SVE</a>
  AMED_AARCH64_CCLASS_uqdech_r_rs_uw, //!< <a href="../target/aarch64/uqdech_r_rs.html#uqdech_r_rs_uw">32-bit</a>
  AMED_AARCH64_CCLASS_uqdech_r_rs_x, //!< <a href="../target/aarch64/uqdech_r_rs.html#uqdech_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_uqdech_z_zs_, //!< <a href="../target/aarch64/uqdech_z_zs.html#uqdech_z_zs_">SVE</a>
  AMED_AARCH64_CCLASS_uqdecp_r_p_r_uw, //!< <a href="../target/aarch64/uqdecp_r_p_r.html#uqdecp_r_p_r_uw">32-bit</a>
  AMED_AARCH64_CCLASS_uqdecp_r_p_r_x, //!< <a href="../target/aarch64/uqdecp_r_p_r.html#uqdecp_r_p_r_x">64-bit</a>
  AMED_AARCH64_CCLASS_uqdecp_z_p_z_, //!< <a href="../target/aarch64/uqdecp_z_p_z.html#uqdecp_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_uqdecw_r_rs_uw, //!< <a href="../target/aarch64/uqdecw_r_rs.html#uqdecw_r_rs_uw">32-bit</a>
  AMED_AARCH64_CCLASS_uqdecw_r_rs_x, //!< <a href="../target/aarch64/uqdecw_r_rs.html#uqdecw_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_uqdecw_z_zs_, //!< <a href="../target/aarch64/uqdecw_z_zs.html#uqdecw_z_zs_">SVE</a>
  AMED_AARCH64_CCLASS_uqincb_r_rs_uw, //!< <a href="../target/aarch64/uqincb_r_rs.html#uqincb_r_rs_uw">32-bit</a>
  AMED_AARCH64_CCLASS_uqincb_r_rs_x, //!< <a href="../target/aarch64/uqincb_r_rs.html#uqincb_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_uqincd_r_rs_uw, //!< <a href="../target/aarch64/uqincd_r_rs.html#uqincd_r_rs_uw">32-bit</a>
  AMED_AARCH64_CCLASS_uqincd_r_rs_x, //!< <a href="../target/aarch64/uqincd_r_rs.html#uqincd_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_uqincd_z_zs_, //!< <a href="../target/aarch64/uqincd_z_zs.html#uqincd_z_zs_">SVE</a>
  AMED_AARCH64_CCLASS_uqinch_r_rs_uw, //!< <a href="../target/aarch64/uqinch_r_rs.html#uqinch_r_rs_uw">32-bit</a>
  AMED_AARCH64_CCLASS_uqinch_r_rs_x, //!< <a href="../target/aarch64/uqinch_r_rs.html#uqinch_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_uqinch_z_zs_, //!< <a href="../target/aarch64/uqinch_z_zs.html#uqinch_z_zs_">SVE</a>
  AMED_AARCH64_CCLASS_uqincp_r_p_r_uw, //!< <a href="../target/aarch64/uqincp_r_p_r.html#uqincp_r_p_r_uw">32-bit</a>
  AMED_AARCH64_CCLASS_uqincp_r_p_r_x, //!< <a href="../target/aarch64/uqincp_r_p_r.html#uqincp_r_p_r_x">64-bit</a>
  AMED_AARCH64_CCLASS_uqincp_z_p_z_, //!< <a href="../target/aarch64/uqincp_z_p_z.html#uqincp_z_p_z_">SVE</a>
  AMED_AARCH64_CCLASS_uqincw_r_rs_uw, //!< <a href="../target/aarch64/uqincw_r_rs.html#uqincw_r_rs_uw">32-bit</a>
  AMED_AARCH64_CCLASS_uqincw_r_rs_x, //!< <a href="../target/aarch64/uqincw_r_rs.html#uqincw_r_rs_x">64-bit</a>
  AMED_AARCH64_CCLASS_uqincw_z_zs_, //!< <a href="../target/aarch64/uqincw_z_zs.html#uqincw_z_zs_">SVE</a>
  AMED_AARCH64_CCLASS_uqrshl_z_p_zz_, //!< <a href="../target/aarch64/uqrshl_z_p_zz.html#uqrshl_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uqrshlr_z_p_zz_, //!< <a href="../target/aarch64/uqrshlr_z_p_zz.html#uqrshlr_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uqrshrnb_z_zi_, //!< <a href="../target/aarch64/uqrshrnb_z_zi.html#uqrshrnb_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_uqrshrnt_z_zi_, //!< <a href="../target/aarch64/uqrshrnt_z_zi.html#uqrshrnt_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_uqshl_z_p_zi_, //!< <a href="../target/aarch64/uqshl_z_p_zi.html#uqshl_z_p_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_uqshl_z_p_zz_, //!< <a href="../target/aarch64/uqshl_z_p_zz.html#uqshl_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uqshlr_z_p_zz_, //!< <a href="../target/aarch64/uqshlr_z_p_zz.html#uqshlr_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uqshrnb_z_zi_, //!< <a href="../target/aarch64/uqshrnb_z_zi.html#uqshrnb_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_uqshrnt_z_zi_, //!< <a href="../target/aarch64/uqshrnt_z_zi.html#uqshrnt_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_uqsub_z_p_zz_, //!< <a href="../target/aarch64/uqsub_z_p_zz.html#uqsub_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uqsub_z_zi_, //!< <a href="../target/aarch64/uqsub_z_zi.html#uqsub_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_uqsub_z_zz_, //!< <a href="../target/aarch64/uqsub_z_zz.html#uqsub_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_uqsubr_z_p_zz_, //!< <a href="../target/aarch64/uqsubr_z_p_zz.html#uqsubr_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uqxtnb_z_zz_, //!< <a href="../target/aarch64/uqxtnb_z_zz.html#uqxtnb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uqxtnt_z_zz_, //!< <a href="../target/aarch64/uqxtnt_z_zz.html#uqxtnt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_urecpe_z_p_z_, //!< <a href="../target/aarch64/urecpe_z_p_z.html#urecpe_z_p_z_">SVE2</a>
  AMED_AARCH64_CCLASS_urhadd_z_p_zz_, //!< <a href="../target/aarch64/urhadd_z_p_zz.html#urhadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_urshl_z_p_zz_, //!< <a href="../target/aarch64/urshl_z_p_zz.html#urshl_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_urshlr_z_p_zz_, //!< <a href="../target/aarch64/urshlr_z_p_zz.html#urshlr_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_urshr_z_p_zi_, //!< <a href="../target/aarch64/urshr_z_p_zi.html#urshr_z_p_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_ursqrte_z_p_z_, //!< <a href="../target/aarch64/ursqrte_z_p_z.html#ursqrte_z_p_z_">SVE2</a>
  AMED_AARCH64_CCLASS_ursra_z_zi_, //!< <a href="../target/aarch64/ursra_z_zi.html#ursra_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_usdot_z_zzz_s, //!< <a href="../target/aarch64/usdot_z_zzz.html#usdot_z_zzz_s">SVE</a>
  AMED_AARCH64_CCLASS_usdot_z_zzzi_s, //!< <a href="../target/aarch64/usdot_z_zzzi.html#usdot_z_zzzi_s">SVE</a>
  AMED_AARCH64_CCLASS_ushllb_z_zi_, //!< <a href="../target/aarch64/ushllb_z_zi.html#ushllb_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_ushllt_z_zi_, //!< <a href="../target/aarch64/ushllt_z_zi.html#ushllt_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_usmmla_z_zzz_, //!< <a href="../target/aarch64/usmmla_z_zzz.html#usmmla_z_zzz_">SVE</a>
  AMED_AARCH64_CCLASS_usqadd_z_p_zz_, //!< <a href="../target/aarch64/usqadd_z_p_zz.html#usqadd_z_p_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_usra_z_zi_, //!< <a href="../target/aarch64/usra_z_zi.html#usra_z_zi_">SVE2</a>
  AMED_AARCH64_CCLASS_usublb_z_zz_, //!< <a href="../target/aarch64/usublb_z_zz.html#usublb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_usublt_z_zz_, //!< <a href="../target/aarch64/usublt_z_zz.html#usublt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_usubwb_z_zz_, //!< <a href="../target/aarch64/usubwb_z_zz.html#usubwb_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_usubwt_z_zz_, //!< <a href="../target/aarch64/usubwt_z_zz.html#usubwt_z_zz_">SVE2</a>
  AMED_AARCH64_CCLASS_uunpkhi_z_z_, //!< <a href="../target/aarch64/uunpkhi_z_z.html#uunpkhi_z_z_">High half</a>
  AMED_AARCH64_CCLASS_uunpklo_z_z_, //!< <a href="../target/aarch64/uunpkhi_z_z.html#uunpklo_z_z_">Low half</a>
  AMED_AARCH64_CCLASS_uxtb_z_p_z_, //!< <a href="../target/aarch64/uxtb_z_p_z.html#uxtb_z_p_z_">Byte</a>
  AMED_AARCH64_CCLASS_uxth_z_p_z_, //!< <a href="../target/aarch64/uxtb_z_p_z.html#uxth_z_p_z_">Halfword</a>
  AMED_AARCH64_CCLASS_uxtw_z_p_z_, //!< <a href="../target/aarch64/uxtb_z_p_z.html#uxtw_z_p_z_">Word</a>
  AMED_AARCH64_CCLASS_uzp1_p_pp_, //!< <a href="../target/aarch64/uzp1_p_pp.html#uzp1_p_pp_">Even</a>
  AMED_AARCH64_CCLASS_uzp2_p_pp_, //!< <a href="../target/aarch64/uzp1_p_pp.html#uzp2_p_pp_">Odd</a>
  AMED_AARCH64_CCLASS_uzp1_z_zz_, //!< <a href="../target/aarch64/uzp1_z_zz.html#uzp1_z_zz_">Even</a>
  AMED_AARCH64_CCLASS_uzp1_z_zz_q, //!< <a href="../target/aarch64/uzp1_z_zz.html#uzp1_z_zz_q">Even (quadwords)</a>
  AMED_AARCH64_CCLASS_uzp2_z_zz_, //!< <a href="../target/aarch64/uzp1_z_zz.html#uzp2_z_zz_">Odd</a>
  AMED_AARCH64_CCLASS_uzp2_z_zz_q, //!< <a href="../target/aarch64/uzp1_z_zz.html#uzp2_z_zz_q">Odd (quadwords)</a>
  AMED_AARCH64_CCLASS_whilege_p_p_rr_, //!< <a href="../target/aarch64/whilege_p_p_rr.html#whilege_p_p_rr_">SVE2</a>
  AMED_AARCH64_CCLASS_whilegt_p_p_rr_, //!< <a href="../target/aarch64/whilegt_p_p_rr.html#whilegt_p_p_rr_">SVE2</a>
  AMED_AARCH64_CCLASS_whilehi_p_p_rr_, //!< <a href="../target/aarch64/whilehi_p_p_rr.html#whilehi_p_p_rr_">SVE2</a>
  AMED_AARCH64_CCLASS_whilehs_p_p_rr_, //!< <a href="../target/aarch64/whilehs_p_p_rr.html#whilehs_p_p_rr_">SVE2</a>
  AMED_AARCH64_CCLASS_whilele_p_p_rr_, //!< <a href="../target/aarch64/whilele_p_p_rr.html#whilele_p_p_rr_">SVE</a>
  AMED_AARCH64_CCLASS_whilelo_p_p_rr_, //!< <a href="../target/aarch64/whilelo_p_p_rr.html#whilelo_p_p_rr_">SVE</a>
  AMED_AARCH64_CCLASS_whilels_p_p_rr_, //!< <a href="../target/aarch64/whilels_p_p_rr.html#whilels_p_p_rr_">SVE</a>
  AMED_AARCH64_CCLASS_whilelt_p_p_rr_, //!< <a href="../target/aarch64/whilelt_p_p_rr.html#whilelt_p_p_rr_">SVE</a>
  AMED_AARCH64_CCLASS_whilerw_p_rr_, //!< <a href="../target/aarch64/whilerw_p_rr.html#whilerw_p_rr_">SVE2</a>
  AMED_AARCH64_CCLASS_whilewr_p_rr_, //!< <a href="../target/aarch64/whilewr_p_rr.html#whilewr_p_rr_">SVE2</a>
  AMED_AARCH64_CCLASS_wrffr_f_p_, //!< <a href="../target/aarch64/wrffr_f_p.html#wrffr_f_p_">SVE</a>
  AMED_AARCH64_CCLASS_xar_z_zzi_, //!< <a href="../target/aarch64/xar_z_zzi.html#xar_z_zzi_">SVE2</a>
  AMED_AARCH64_CCLASS_zip2_p_pp_, //!< <a href="../target/aarch64/zip1_p_pp.html#zip2_p_pp_">High halves</a>
  AMED_AARCH64_CCLASS_zip1_p_pp_, //!< <a href="../target/aarch64/zip1_p_pp.html#zip1_p_pp_">Low halves</a>
  AMED_AARCH64_CCLASS_zip2_z_zz_, //!< <a href="../target/aarch64/zip1_z_zz.html#zip2_z_zz_">High halves</a>
  AMED_AARCH64_CCLASS_zip2_z_zz_q, //!< <a href="../target/aarch64/zip1_z_zz.html#zip2_z_zz_q">High halves (quadwords)</a>
  AMED_AARCH64_CCLASS_zip1_z_zz_, //!< <a href="../target/aarch64/zip1_z_zz.html#zip1_z_zz_">Low halves</a>
  AMED_AARCH64_CCLASS_zip1_z_zz_q, //!< <a href="../target/aarch64/zip1_z_zz.html#zip1_z_zz_q">Low halves (quadwords)</a>
  AMED_AARCH64_CCLASS_BIC_and_z_zi_and_z_zi_, //!< <a href="../target/aarch64/BIC_and_z_zi.html#and_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_CMPLE_cmpeq_p_p_zz_cmpge_p_p_zz_, //!< <a href="../target/aarch64/CMPLE_cmpeq_p_p_zz.html#cmpge_p_p_zz_">Greater than or equal</a>
  AMED_AARCH64_CCLASS_CMPLO_cmpeq_p_p_zz_cmphi_p_p_zz_, //!< <a href="../target/aarch64/CMPLO_cmpeq_p_p_zz.html#cmphi_p_p_zz_">Higher</a>
  AMED_AARCH64_CCLASS_CMPLS_cmpeq_p_p_zz_cmphs_p_p_zz_, //!< <a href="../target/aarch64/CMPLS_cmpeq_p_p_zz.html#cmphs_p_p_zz_">Higher or same</a>
  AMED_AARCH64_CCLASS_CMPLT_cmpeq_p_p_zz_cmpgt_p_p_zz_, //!< <a href="../target/aarch64/CMPLT_cmpeq_p_p_zz.html#cmpgt_p_p_zz_">Greater than</a>
  AMED_AARCH64_CCLASS_EON_eor_z_zi_eor_z_zi_, //!< <a href="../target/aarch64/EON_eor_z_zi.html#eor_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_FACLE_facge_p_p_zz_facge_p_p_zz_, //!< <a href="../target/aarch64/FACLE_facge_p_p_zz.html#facge_p_p_zz_">Greater than or equal</a>
  AMED_AARCH64_CCLASS_FACLT_facge_p_p_zz_facgt_p_p_zz_, //!< <a href="../target/aarch64/FACLT_facge_p_p_zz.html#facgt_p_p_zz_">Greater than</a>
  AMED_AARCH64_CCLASS_FCMLE_fcmeq_p_p_zz_fcmge_p_p_zz_, //!< <a href="../target/aarch64/FCMLE_fcmeq_p_p_zz.html#fcmge_p_p_zz_">Greater than or equal</a>
  AMED_AARCH64_CCLASS_FCMLT_fcmeq_p_p_zz_fcmgt_p_p_zz_, //!< <a href="../target/aarch64/FCMLT_fcmeq_p_p_zz.html#fcmgt_p_p_zz_">Greater than</a>
  AMED_AARCH64_CCLASS_FMOV_cpy_z_p_i_cpy_z_p_i_, //!< <a href="../target/aarch64/FMOV_cpy_z_p_i.html#cpy_z_p_i_">SVE</a>
  AMED_AARCH64_CCLASS_FMOV_dup_z_i_dup_z_i_, //!< <a href="../target/aarch64/FMOV_dup_z_i.html#dup_z_i_">SVE</a>
  AMED_AARCH64_CCLASS_FMOV_fcpy_z_p_i_fcpy_z_p_i_, //!< <a href="../target/aarch64/FMOV_fcpy_z_p_i.html#fcpy_z_p_i_">SVE</a>
  AMED_AARCH64_CCLASS_FMOV_fdup_z_i_fdup_z_i_, //!< <a href="../target/aarch64/FMOV_fdup_z_i.html#fdup_z_i_">SVE</a>
  AMED_AARCH64_CCLASS_MOV_and_p_p_pp_and_p_p_pp_z, //!< <a href="../target/aarch64/MOV_and_p_p_pp.html#and_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_MOV_cpy_z_o_i_cpy_z_o_i_, //!< <a href="../target/aarch64/MOV_cpy_z_o_i.html#cpy_z_o_i_">SVE</a>
  AMED_AARCH64_CCLASS_MOV_cpy_z_p_i_cpy_z_p_i_, //!< <a href="../target/aarch64/MOV_cpy_z_p_i.html#cpy_z_p_i_">SVE</a>
  AMED_AARCH64_CCLASS_MOV_cpy_z_p_r_cpy_z_p_r_, //!< <a href="../target/aarch64/MOV_cpy_z_p_r.html#cpy_z_p_r_">SVE</a>
  AMED_AARCH64_CCLASS_MOV_cpy_z_p_v_cpy_z_p_v_, //!< <a href="../target/aarch64/MOV_cpy_z_p_v.html#cpy_z_p_v_">SVE</a>
  AMED_AARCH64_CCLASS_MOV_dup_z_i_dup_z_i_, //!< <a href="../target/aarch64/MOV_dup_z_i.html#dup_z_i_">SVE</a>
  AMED_AARCH64_CCLASS_MOV_dup_z_r_dup_z_r_, //!< <a href="../target/aarch64/MOV_dup_z_r.html#dup_z_r_">SVE</a>
  AMED_AARCH64_CCLASS_MOV_dup_z_zi_dup_z_zi_, //!< <a href="../target/aarch64/MOV_dup_z_zi.html#dup_z_zi_">SVE</a>
  AMED_AARCH64_CCLASS_MOV_dupm_z_i_dupm_z_i_, //!< <a href="../target/aarch64/MOV_dupm_z_i.html#dupm_z_i_">SVE</a>
  AMED_AARCH64_CCLASS_MOV_orr_p_p_pp_orr_p_p_pp_z, //!< <a href="../target/aarch64/MOV_orr_p_p_pp.html#orr_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_MOV_orr_z_zz_orr_z_zz_, //!< <a href="../target/aarch64/MOV_orr_z_zz.html#orr_z_zz_">SVE</a>
  AMED_AARCH64_CCLASS_MOV_sel_p_p_pp_sel_p_p_pp_, //!< <a href="../target/aarch64/MOV_sel_p_p_pp.html#sel_p_p_pp_">SVE</a>
  AMED_AARCH64_CCLASS_MOV_sel_z_p_zz_sel_z_p_zz_, //!< <a href="../target/aarch64/MOV_sel_z_p_zz.html#sel_z_p_zz_">SVE</a>
  AMED_AARCH64_CCLASS_MOVS_and_p_p_pp_ands_p_p_pp_z, //!< <a href="../target/aarch64/MOVS_and_p_p_pp.html#ands_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_MOVS_orr_p_p_pp_orrs_p_p_pp_z, //!< <a href="../target/aarch64/MOVS_orr_p_p_pp.html#orrs_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_NOT_eor_p_p_pp_eor_p_p_pp_z, //!< <a href="../target/aarch64/NOT_eor_p_p_pp.html#eor_p_p_pp_z">Not setting the condition flags</a>
  AMED_AARCH64_CCLASS_NOTS_eor_p_p_pp_eors_p_p_pp_z, //!< <a href="../target/aarch64/NOTS_eor_p_p_pp.html#eors_p_p_pp_z">Setting the condition flags</a>
  AMED_AARCH64_CCLASS_ORN_orr_z_zi_orr_z_zi_, //!< <a href="../target/aarch64/ORN_orr_z_zi.html#orr_z_zi_">SVE</a>
} amed_aarch64_cclass;

#define AMED_AARCH64_DC_OP_MAX_TEXT_LENGTH (7 + 1)

typedef enum _amed_aarch64_dc_op
{
  AMED_AARCH64_DC_OP_NONE,
  AMED_AARCH64_DC_OP_CGDSW,
  AMED_AARCH64_DC_OP_CGDVAC,
  AMED_AARCH64_DC_OP_CGDVADP,
  AMED_AARCH64_DC_OP_CGDVAP,
  AMED_AARCH64_DC_OP_CGSW,
  AMED_AARCH64_DC_OP_CGVAC,
  AMED_AARCH64_DC_OP_CGVADP,
  AMED_AARCH64_DC_OP_CGVAP,
  AMED_AARCH64_DC_OP_CIGDSW,
  AMED_AARCH64_DC_OP_CIGDVAC,
  AMED_AARCH64_DC_OP_CIGSW,
  AMED_AARCH64_DC_OP_CIGVAC,
  AMED_AARCH64_DC_OP_CISW,
  AMED_AARCH64_DC_OP_CIVAC,
  AMED_AARCH64_DC_OP_CSW,
  AMED_AARCH64_DC_OP_CVAC,
  AMED_AARCH64_DC_OP_CVADP,
  AMED_AARCH64_DC_OP_CVAP,
  AMED_AARCH64_DC_OP_CVAU,
  AMED_AARCH64_DC_OP_GVA,
  AMED_AARCH64_DC_OP_GZVA,
  AMED_AARCH64_DC_OP_IGDSW,
  AMED_AARCH64_DC_OP_IGDVAC,
  AMED_AARCH64_DC_OP_IGSW,
  AMED_AARCH64_DC_OP_IGVAC,
  AMED_AARCH64_DC_OP_ISW,
  AMED_AARCH64_DC_OP_IVAC,
  AMED_AARCH64_DC_OP_ZVA,
} amed_aarch64_dc_op;

#define AMED_AARCH64_MNEMONIC_MAX_TEXT_LENGTH (9 + 1)

typedef enum _amed_aarch64_mnemonic
{
  AMED_AARCH64_MNEMONIC_NONE,
  AMED_AARCH64_MNEMONIC_INVALID,
  AMED_AARCH64_MNEMONIC_ADC,
  AMED_AARCH64_MNEMONIC_ADCS,
  AMED_AARCH64_MNEMONIC_ADD,
  AMED_AARCH64_MNEMONIC_ADDG,
  AMED_AARCH64_MNEMONIC_ADDS,
  AMED_AARCH64_MNEMONIC_ADR,
  AMED_AARCH64_MNEMONIC_ADRP,
  AMED_AARCH64_MNEMONIC_AND,
  AMED_AARCH64_MNEMONIC_ANDS,
  AMED_AARCH64_MNEMONIC_ASRV,
  AMED_AARCH64_MNEMONIC_AUTDA,
  AMED_AARCH64_MNEMONIC_AUTDZA,
  AMED_AARCH64_MNEMONIC_AUTDB,
  AMED_AARCH64_MNEMONIC_AUTDZB,
  AMED_AARCH64_MNEMONIC_AUTIA,
  AMED_AARCH64_MNEMONIC_AUTIZA,
  AMED_AARCH64_MNEMONIC_AUTIA1716,
  AMED_AARCH64_MNEMONIC_AUTIASP,
  AMED_AARCH64_MNEMONIC_AUTIAZ,
  AMED_AARCH64_MNEMONIC_AUTIB,
  AMED_AARCH64_MNEMONIC_AUTIZB,
  AMED_AARCH64_MNEMONIC_AUTIB1716,
  AMED_AARCH64_MNEMONIC_AUTIBSP,
  AMED_AARCH64_MNEMONIC_AUTIBZ,
  AMED_AARCH64_MNEMONIC_AXFLAG,
  AMED_AARCH64_MNEMONIC_B,
  AMED_AARCH64_MNEMONIC_BFM,
  AMED_AARCH64_MNEMONIC_BIC,
  AMED_AARCH64_MNEMONIC_BICS,
  AMED_AARCH64_MNEMONIC_BL,
  AMED_AARCH64_MNEMONIC_BLR,
  AMED_AARCH64_MNEMONIC_BLRAAZ,
  AMED_AARCH64_MNEMONIC_BLRAA,
  AMED_AARCH64_MNEMONIC_BLRABZ,
  AMED_AARCH64_MNEMONIC_BLRAB,
  AMED_AARCH64_MNEMONIC_BR,
  AMED_AARCH64_MNEMONIC_BRAAZ,
  AMED_AARCH64_MNEMONIC_BRAA,
  AMED_AARCH64_MNEMONIC_BRABZ,
  AMED_AARCH64_MNEMONIC_BRAB,
  AMED_AARCH64_MNEMONIC_BRK,
  AMED_AARCH64_MNEMONIC_BTI,
  AMED_AARCH64_MNEMONIC_CAS,
  AMED_AARCH64_MNEMONIC_CASA,
  AMED_AARCH64_MNEMONIC_CASAL,
  AMED_AARCH64_MNEMONIC_CASL,
  AMED_AARCH64_MNEMONIC_CASAB,
  AMED_AARCH64_MNEMONIC_CASALB,
  AMED_AARCH64_MNEMONIC_CASB,
  AMED_AARCH64_MNEMONIC_CASLB,
  AMED_AARCH64_MNEMONIC_CASAH,
  AMED_AARCH64_MNEMONIC_CASALH,
  AMED_AARCH64_MNEMONIC_CASH,
  AMED_AARCH64_MNEMONIC_CASLH,
  AMED_AARCH64_MNEMONIC_CASP,
  AMED_AARCH64_MNEMONIC_CASPA,
  AMED_AARCH64_MNEMONIC_CASPAL,
  AMED_AARCH64_MNEMONIC_CASPL,
  AMED_AARCH64_MNEMONIC_CBNZ,
  AMED_AARCH64_MNEMONIC_CBZ,
  AMED_AARCH64_MNEMONIC_CCMN,
  AMED_AARCH64_MNEMONIC_CCMP,
  AMED_AARCH64_MNEMONIC_CFINV,
  AMED_AARCH64_MNEMONIC_CLREX,
  AMED_AARCH64_MNEMONIC_CLS,
  AMED_AARCH64_MNEMONIC_CLZ,
  AMED_AARCH64_MNEMONIC_CRC32B,
  AMED_AARCH64_MNEMONIC_CRC32H,
  AMED_AARCH64_MNEMONIC_CRC32W,
  AMED_AARCH64_MNEMONIC_CRC32X,
  AMED_AARCH64_MNEMONIC_CRC32CB,
  AMED_AARCH64_MNEMONIC_CRC32CH,
  AMED_AARCH64_MNEMONIC_CRC32CW,
  AMED_AARCH64_MNEMONIC_CRC32CX,
  AMED_AARCH64_MNEMONIC_CSDB,
  AMED_AARCH64_MNEMONIC_CSEL,
  AMED_AARCH64_MNEMONIC_CSINC,
  AMED_AARCH64_MNEMONIC_CSINV,
  AMED_AARCH64_MNEMONIC_CSNEG,
  AMED_AARCH64_MNEMONIC_DCPS1,
  AMED_AARCH64_MNEMONIC_DCPS2,
  AMED_AARCH64_MNEMONIC_DCPS3,
  AMED_AARCH64_MNEMONIC_DGH,
  AMED_AARCH64_MNEMONIC_DMB,
  AMED_AARCH64_MNEMONIC_DRPS,
  AMED_AARCH64_MNEMONIC_DSB,
  AMED_AARCH64_MNEMONIC_EON,
  AMED_AARCH64_MNEMONIC_EOR,
  AMED_AARCH64_MNEMONIC_ERET,
  AMED_AARCH64_MNEMONIC_ERETAA,
  AMED_AARCH64_MNEMONIC_ERETAB,
  AMED_AARCH64_MNEMONIC_ESB,
  AMED_AARCH64_MNEMONIC_EXTR,
  AMED_AARCH64_MNEMONIC_GMI,
  AMED_AARCH64_MNEMONIC_HINT,
  AMED_AARCH64_MNEMONIC_HLT,
  AMED_AARCH64_MNEMONIC_HVC,
  AMED_AARCH64_MNEMONIC_IRG,
  AMED_AARCH64_MNEMONIC_ISB,
  AMED_AARCH64_MNEMONIC_LDADD,
  AMED_AARCH64_MNEMONIC_LDADDA,
  AMED_AARCH64_MNEMONIC_LDADDAL,
  AMED_AARCH64_MNEMONIC_LDADDL,
  AMED_AARCH64_MNEMONIC_LDADDAB,
  AMED_AARCH64_MNEMONIC_LDADDALB,
  AMED_AARCH64_MNEMONIC_LDADDB,
  AMED_AARCH64_MNEMONIC_LDADDLB,
  AMED_AARCH64_MNEMONIC_LDADDAH,
  AMED_AARCH64_MNEMONIC_LDADDALH,
  AMED_AARCH64_MNEMONIC_LDADDH,
  AMED_AARCH64_MNEMONIC_LDADDLH,
  AMED_AARCH64_MNEMONIC_LDAPR,
  AMED_AARCH64_MNEMONIC_LDAPRB,
  AMED_AARCH64_MNEMONIC_LDAPRH,
  AMED_AARCH64_MNEMONIC_LDAPUR,
  AMED_AARCH64_MNEMONIC_LDAPURB,
  AMED_AARCH64_MNEMONIC_LDAPURH,
  AMED_AARCH64_MNEMONIC_LDAPURSB,
  AMED_AARCH64_MNEMONIC_LDAPURSH,
  AMED_AARCH64_MNEMONIC_LDAPURSW,
  AMED_AARCH64_MNEMONIC_LDAR,
  AMED_AARCH64_MNEMONIC_LDARB,
  AMED_AARCH64_MNEMONIC_LDARH,
  AMED_AARCH64_MNEMONIC_LDAXP,
  AMED_AARCH64_MNEMONIC_LDAXR,
  AMED_AARCH64_MNEMONIC_LDAXRB,
  AMED_AARCH64_MNEMONIC_LDAXRH,
  AMED_AARCH64_MNEMONIC_LDCLR,
  AMED_AARCH64_MNEMONIC_LDCLRA,
  AMED_AARCH64_MNEMONIC_LDCLRAL,
  AMED_AARCH64_MNEMONIC_LDCLRL,
  AMED_AARCH64_MNEMONIC_LDCLRAB,
  AMED_AARCH64_MNEMONIC_LDCLRALB,
  AMED_AARCH64_MNEMONIC_LDCLRB,
  AMED_AARCH64_MNEMONIC_LDCLRLB,
  AMED_AARCH64_MNEMONIC_LDCLRAH,
  AMED_AARCH64_MNEMONIC_LDCLRALH,
  AMED_AARCH64_MNEMONIC_LDCLRH,
  AMED_AARCH64_MNEMONIC_LDCLRLH,
  AMED_AARCH64_MNEMONIC_LDEOR,
  AMED_AARCH64_MNEMONIC_LDEORA,
  AMED_AARCH64_MNEMONIC_LDEORAL,
  AMED_AARCH64_MNEMONIC_LDEORL,
  AMED_AARCH64_MNEMONIC_LDEORAB,
  AMED_AARCH64_MNEMONIC_LDEORALB,
  AMED_AARCH64_MNEMONIC_LDEORB,
  AMED_AARCH64_MNEMONIC_LDEORLB,
  AMED_AARCH64_MNEMONIC_LDEORAH,
  AMED_AARCH64_MNEMONIC_LDEORALH,
  AMED_AARCH64_MNEMONIC_LDEORH,
  AMED_AARCH64_MNEMONIC_LDEORLH,
  AMED_AARCH64_MNEMONIC_LDG,
  AMED_AARCH64_MNEMONIC_LDGM,
  AMED_AARCH64_MNEMONIC_LDLAR,
  AMED_AARCH64_MNEMONIC_LDLARB,
  AMED_AARCH64_MNEMONIC_LDLARH,
  AMED_AARCH64_MNEMONIC_LDNP,
  AMED_AARCH64_MNEMONIC_LDP,
  AMED_AARCH64_MNEMONIC_LDPSW,
  AMED_AARCH64_MNEMONIC_LDR,
  AMED_AARCH64_MNEMONIC_LDRAA,
  AMED_AARCH64_MNEMONIC_LDRAB,
  AMED_AARCH64_MNEMONIC_LDRB,
  AMED_AARCH64_MNEMONIC_LDRH,
  AMED_AARCH64_MNEMONIC_LDRSB,
  AMED_AARCH64_MNEMONIC_LDRSH,
  AMED_AARCH64_MNEMONIC_LDRSW,
  AMED_AARCH64_MNEMONIC_LDSET,
  AMED_AARCH64_MNEMONIC_LDSETA,
  AMED_AARCH64_MNEMONIC_LDSETAL,
  AMED_AARCH64_MNEMONIC_LDSETL,
  AMED_AARCH64_MNEMONIC_LDSETAB,
  AMED_AARCH64_MNEMONIC_LDSETALB,
  AMED_AARCH64_MNEMONIC_LDSETB,
  AMED_AARCH64_MNEMONIC_LDSETLB,
  AMED_AARCH64_MNEMONIC_LDSETAH,
  AMED_AARCH64_MNEMONIC_LDSETALH,
  AMED_AARCH64_MNEMONIC_LDSETH,
  AMED_AARCH64_MNEMONIC_LDSETLH,
  AMED_AARCH64_MNEMONIC_LDSMAX,
  AMED_AARCH64_MNEMONIC_LDSMAXA,
  AMED_AARCH64_MNEMONIC_LDSMAXAL,
  AMED_AARCH64_MNEMONIC_LDSMAXL,
  AMED_AARCH64_MNEMONIC_LDSMAXAB,
  AMED_AARCH64_MNEMONIC_LDSMAXALB,
  AMED_AARCH64_MNEMONIC_LDSMAXB,
  AMED_AARCH64_MNEMONIC_LDSMAXLB,
  AMED_AARCH64_MNEMONIC_LDSMAXAH,
  AMED_AARCH64_MNEMONIC_LDSMAXALH,
  AMED_AARCH64_MNEMONIC_LDSMAXH,
  AMED_AARCH64_MNEMONIC_LDSMAXLH,
  AMED_AARCH64_MNEMONIC_LDSMIN,
  AMED_AARCH64_MNEMONIC_LDSMINA,
  AMED_AARCH64_MNEMONIC_LDSMINAL,
  AMED_AARCH64_MNEMONIC_LDSMINL,
  AMED_AARCH64_MNEMONIC_LDSMINAB,
  AMED_AARCH64_MNEMONIC_LDSMINALB,
  AMED_AARCH64_MNEMONIC_LDSMINB,
  AMED_AARCH64_MNEMONIC_LDSMINLB,
  AMED_AARCH64_MNEMONIC_LDSMINAH,
  AMED_AARCH64_MNEMONIC_LDSMINALH,
  AMED_AARCH64_MNEMONIC_LDSMINH,
  AMED_AARCH64_MNEMONIC_LDSMINLH,
  AMED_AARCH64_MNEMONIC_LDTR,
  AMED_AARCH64_MNEMONIC_LDTRB,
  AMED_AARCH64_MNEMONIC_LDTRH,
  AMED_AARCH64_MNEMONIC_LDTRSB,
  AMED_AARCH64_MNEMONIC_LDTRSH,
  AMED_AARCH64_MNEMONIC_LDTRSW,
  AMED_AARCH64_MNEMONIC_LDUMAX,
  AMED_AARCH64_MNEMONIC_LDUMAXA,
  AMED_AARCH64_MNEMONIC_LDUMAXAL,
  AMED_AARCH64_MNEMONIC_LDUMAXL,
  AMED_AARCH64_MNEMONIC_LDUMAXAB,
  AMED_AARCH64_MNEMONIC_LDUMAXALB,
  AMED_AARCH64_MNEMONIC_LDUMAXB,
  AMED_AARCH64_MNEMONIC_LDUMAXLB,
  AMED_AARCH64_MNEMONIC_LDUMAXAH,
  AMED_AARCH64_MNEMONIC_LDUMAXALH,
  AMED_AARCH64_MNEMONIC_LDUMAXH,
  AMED_AARCH64_MNEMONIC_LDUMAXLH,
  AMED_AARCH64_MNEMONIC_LDUMIN,
  AMED_AARCH64_MNEMONIC_LDUMINA,
  AMED_AARCH64_MNEMONIC_LDUMINAL,
  AMED_AARCH64_MNEMONIC_LDUMINL,
  AMED_AARCH64_MNEMONIC_LDUMINAB,
  AMED_AARCH64_MNEMONIC_LDUMINALB,
  AMED_AARCH64_MNEMONIC_LDUMINB,
  AMED_AARCH64_MNEMONIC_LDUMINLB,
  AMED_AARCH64_MNEMONIC_LDUMINAH,
  AMED_AARCH64_MNEMONIC_LDUMINALH,
  AMED_AARCH64_MNEMONIC_LDUMINH,
  AMED_AARCH64_MNEMONIC_LDUMINLH,
  AMED_AARCH64_MNEMONIC_LDUR,
  AMED_AARCH64_MNEMONIC_LDURB,
  AMED_AARCH64_MNEMONIC_LDURH,
  AMED_AARCH64_MNEMONIC_LDURSB,
  AMED_AARCH64_MNEMONIC_LDURSH,
  AMED_AARCH64_MNEMONIC_LDURSW,
  AMED_AARCH64_MNEMONIC_LDXP,
  AMED_AARCH64_MNEMONIC_LDXR,
  AMED_AARCH64_MNEMONIC_LDXRB,
  AMED_AARCH64_MNEMONIC_LDXRH,
  AMED_AARCH64_MNEMONIC_LSLV,
  AMED_AARCH64_MNEMONIC_LSRV,
  AMED_AARCH64_MNEMONIC_MADD,
  AMED_AARCH64_MNEMONIC_MOVK,
  AMED_AARCH64_MNEMONIC_MOVN,
  AMED_AARCH64_MNEMONIC_MOVZ,
  AMED_AARCH64_MNEMONIC_MRS,
  AMED_AARCH64_MNEMONIC_MSR,
  AMED_AARCH64_MNEMONIC_MSUB,
  AMED_AARCH64_MNEMONIC_NOP,
  AMED_AARCH64_MNEMONIC_ORN,
  AMED_AARCH64_MNEMONIC_ORR,
  AMED_AARCH64_MNEMONIC_PACDA,
  AMED_AARCH64_MNEMONIC_PACDZA,
  AMED_AARCH64_MNEMONIC_PACDB,
  AMED_AARCH64_MNEMONIC_PACDZB,
  AMED_AARCH64_MNEMONIC_PACGA,
  AMED_AARCH64_MNEMONIC_PACIA,
  AMED_AARCH64_MNEMONIC_PACIZA,
  AMED_AARCH64_MNEMONIC_PACIA1716,
  AMED_AARCH64_MNEMONIC_PACIASP,
  AMED_AARCH64_MNEMONIC_PACIAZ,
  AMED_AARCH64_MNEMONIC_PACIB,
  AMED_AARCH64_MNEMONIC_PACIZB,
  AMED_AARCH64_MNEMONIC_PACIB1716,
  AMED_AARCH64_MNEMONIC_PACIBSP,
  AMED_AARCH64_MNEMONIC_PACIBZ,
  AMED_AARCH64_MNEMONIC_PRFM,
  AMED_AARCH64_MNEMONIC_PRFUM,
  AMED_AARCH64_MNEMONIC_PSB,
  AMED_AARCH64_MNEMONIC_PSSBB,
  AMED_AARCH64_MNEMONIC_RBIT,
  AMED_AARCH64_MNEMONIC_RET,
  AMED_AARCH64_MNEMONIC_RETAA,
  AMED_AARCH64_MNEMONIC_RETAB,
  AMED_AARCH64_MNEMONIC_REV,
  AMED_AARCH64_MNEMONIC_REV16,
  AMED_AARCH64_MNEMONIC_REV32,
  AMED_AARCH64_MNEMONIC_RMIF,
  AMED_AARCH64_MNEMONIC_RORV,
  AMED_AARCH64_MNEMONIC_SB,
  AMED_AARCH64_MNEMONIC_SBC,
  AMED_AARCH64_MNEMONIC_SBCS,
  AMED_AARCH64_MNEMONIC_SBFM,
  AMED_AARCH64_MNEMONIC_SDIV,
  AMED_AARCH64_MNEMONIC_SETF8,
  AMED_AARCH64_MNEMONIC_SETF16,
  AMED_AARCH64_MNEMONIC_SEV,
  AMED_AARCH64_MNEMONIC_SEVL,
  AMED_AARCH64_MNEMONIC_SMADDL,
  AMED_AARCH64_MNEMONIC_SMC,
  AMED_AARCH64_MNEMONIC_SMSUBL,
  AMED_AARCH64_MNEMONIC_SMULH,
  AMED_AARCH64_MNEMONIC_SSBB,
  AMED_AARCH64_MNEMONIC_ST2G,
  AMED_AARCH64_MNEMONIC_STG,
  AMED_AARCH64_MNEMONIC_STGM,
  AMED_AARCH64_MNEMONIC_STGP,
  AMED_AARCH64_MNEMONIC_STLLR,
  AMED_AARCH64_MNEMONIC_STLLRB,
  AMED_AARCH64_MNEMONIC_STLLRH,
  AMED_AARCH64_MNEMONIC_STLR,
  AMED_AARCH64_MNEMONIC_STLRB,
  AMED_AARCH64_MNEMONIC_STLRH,
  AMED_AARCH64_MNEMONIC_STLUR,
  AMED_AARCH64_MNEMONIC_STLURB,
  AMED_AARCH64_MNEMONIC_STLURH,
  AMED_AARCH64_MNEMONIC_STLXP,
  AMED_AARCH64_MNEMONIC_STLXR,
  AMED_AARCH64_MNEMONIC_STLXRB,
  AMED_AARCH64_MNEMONIC_STLXRH,
  AMED_AARCH64_MNEMONIC_STNP,
  AMED_AARCH64_MNEMONIC_STP,
  AMED_AARCH64_MNEMONIC_STR,
  AMED_AARCH64_MNEMONIC_STRB,
  AMED_AARCH64_MNEMONIC_STRH,
  AMED_AARCH64_MNEMONIC_STTR,
  AMED_AARCH64_MNEMONIC_STTRB,
  AMED_AARCH64_MNEMONIC_STTRH,
  AMED_AARCH64_MNEMONIC_STUR,
  AMED_AARCH64_MNEMONIC_STURB,
  AMED_AARCH64_MNEMONIC_STURH,
  AMED_AARCH64_MNEMONIC_STXP,
  AMED_AARCH64_MNEMONIC_STXR,
  AMED_AARCH64_MNEMONIC_STXRB,
  AMED_AARCH64_MNEMONIC_STXRH,
  AMED_AARCH64_MNEMONIC_STZ2G,
  AMED_AARCH64_MNEMONIC_STZG,
  AMED_AARCH64_MNEMONIC_STZGM,
  AMED_AARCH64_MNEMONIC_SUB,
  AMED_AARCH64_MNEMONIC_SUBG,
  AMED_AARCH64_MNEMONIC_SUBP,
  AMED_AARCH64_MNEMONIC_SUBPS,
  AMED_AARCH64_MNEMONIC_SUBS,
  AMED_AARCH64_MNEMONIC_SVC,
  AMED_AARCH64_MNEMONIC_SWP,
  AMED_AARCH64_MNEMONIC_SWPA,
  AMED_AARCH64_MNEMONIC_SWPAL,
  AMED_AARCH64_MNEMONIC_SWPL,
  AMED_AARCH64_MNEMONIC_SWPAB,
  AMED_AARCH64_MNEMONIC_SWPALB,
  AMED_AARCH64_MNEMONIC_SWPB,
  AMED_AARCH64_MNEMONIC_SWPLB,
  AMED_AARCH64_MNEMONIC_SWPAH,
  AMED_AARCH64_MNEMONIC_SWPALH,
  AMED_AARCH64_MNEMONIC_SWPH,
  AMED_AARCH64_MNEMONIC_SWPLH,
  AMED_AARCH64_MNEMONIC_SYS,
  AMED_AARCH64_MNEMONIC_SYSL,
  AMED_AARCH64_MNEMONIC_TBNZ,
  AMED_AARCH64_MNEMONIC_TBZ,
  AMED_AARCH64_MNEMONIC_TCANCEL,
  AMED_AARCH64_MNEMONIC_TCOMMIT,
  AMED_AARCH64_MNEMONIC_TSB,
  AMED_AARCH64_MNEMONIC_TSTART,
  AMED_AARCH64_MNEMONIC_TTEST,
  AMED_AARCH64_MNEMONIC_UBFM,
  AMED_AARCH64_MNEMONIC_UDF,
  AMED_AARCH64_MNEMONIC_UDIV,
  AMED_AARCH64_MNEMONIC_UMADDL,
  AMED_AARCH64_MNEMONIC_UMSUBL,
  AMED_AARCH64_MNEMONIC_UMULH,
  AMED_AARCH64_MNEMONIC_WFE,
  AMED_AARCH64_MNEMONIC_WFI,
  AMED_AARCH64_MNEMONIC_XAFLAG,
  AMED_AARCH64_MNEMONIC_XPACD,
  AMED_AARCH64_MNEMONIC_XPACI,
  AMED_AARCH64_MNEMONIC_XPACLRI,
  AMED_AARCH64_MNEMONIC_YIELD,
  AMED_AARCH64_MNEMONIC_ASR,
  AMED_AARCH64_MNEMONIC_AT,
  AMED_AARCH64_MNEMONIC_BFC,
  AMED_AARCH64_MNEMONIC_BFI,
  AMED_AARCH64_MNEMONIC_BFXIL,
  AMED_AARCH64_MNEMONIC_CFP,
  AMED_AARCH64_MNEMONIC_CINC,
  AMED_AARCH64_MNEMONIC_CINV,
  AMED_AARCH64_MNEMONIC_CMN,
  AMED_AARCH64_MNEMONIC_CMP,
  AMED_AARCH64_MNEMONIC_CMPP,
  AMED_AARCH64_MNEMONIC_CNEG,
  AMED_AARCH64_MNEMONIC_CPP,
  AMED_AARCH64_MNEMONIC_CSET,
  AMED_AARCH64_MNEMONIC_CSETM,
  AMED_AARCH64_MNEMONIC_DC,
  AMED_AARCH64_MNEMONIC_DFB,
  AMED_AARCH64_MNEMONIC_DVP,
  AMED_AARCH64_MNEMONIC_IC,
  AMED_AARCH64_MNEMONIC_LSL,
  AMED_AARCH64_MNEMONIC_LSR,
  AMED_AARCH64_MNEMONIC_MNEG,
  AMED_AARCH64_MNEMONIC_MOV,
  AMED_AARCH64_MNEMONIC_MUL,
  AMED_AARCH64_MNEMONIC_MVN,
  AMED_AARCH64_MNEMONIC_NEG,
  AMED_AARCH64_MNEMONIC_NEGS,
  AMED_AARCH64_MNEMONIC_NGC,
  AMED_AARCH64_MNEMONIC_NGCS,
  AMED_AARCH64_MNEMONIC_REV64,
  AMED_AARCH64_MNEMONIC_ROR,
  AMED_AARCH64_MNEMONIC_SBFIZ,
  AMED_AARCH64_MNEMONIC_SBFX,
  AMED_AARCH64_MNEMONIC_SMNEGL,
  AMED_AARCH64_MNEMONIC_SMULL,
  AMED_AARCH64_MNEMONIC_STADD,
  AMED_AARCH64_MNEMONIC_STADDL,
  AMED_AARCH64_MNEMONIC_STADDB,
  AMED_AARCH64_MNEMONIC_STADDLB,
  AMED_AARCH64_MNEMONIC_STADDH,
  AMED_AARCH64_MNEMONIC_STADDLH,
  AMED_AARCH64_MNEMONIC_STCLR,
  AMED_AARCH64_MNEMONIC_STCLRL,
  AMED_AARCH64_MNEMONIC_STCLRB,
  AMED_AARCH64_MNEMONIC_STCLRLB,
  AMED_AARCH64_MNEMONIC_STCLRH,
  AMED_AARCH64_MNEMONIC_STCLRLH,
  AMED_AARCH64_MNEMONIC_STEOR,
  AMED_AARCH64_MNEMONIC_STEORL,
  AMED_AARCH64_MNEMONIC_STEORB,
  AMED_AARCH64_MNEMONIC_STEORLB,
  AMED_AARCH64_MNEMONIC_STEORH,
  AMED_AARCH64_MNEMONIC_STEORLH,
  AMED_AARCH64_MNEMONIC_STSET,
  AMED_AARCH64_MNEMONIC_STSETL,
  AMED_AARCH64_MNEMONIC_STSETB,
  AMED_AARCH64_MNEMONIC_STSETLB,
  AMED_AARCH64_MNEMONIC_STSETH,
  AMED_AARCH64_MNEMONIC_STSETLH,
  AMED_AARCH64_MNEMONIC_STSMAX,
  AMED_AARCH64_MNEMONIC_STSMAXL,
  AMED_AARCH64_MNEMONIC_STSMAXB,
  AMED_AARCH64_MNEMONIC_STSMAXLB,
  AMED_AARCH64_MNEMONIC_STSMAXH,
  AMED_AARCH64_MNEMONIC_STSMAXLH,
  AMED_AARCH64_MNEMONIC_STSMIN,
  AMED_AARCH64_MNEMONIC_STSMINL,
  AMED_AARCH64_MNEMONIC_STSMINB,
  AMED_AARCH64_MNEMONIC_STSMINLB,
  AMED_AARCH64_MNEMONIC_STSMINH,
  AMED_AARCH64_MNEMONIC_STSMINLH,
  AMED_AARCH64_MNEMONIC_STUMAX,
  AMED_AARCH64_MNEMONIC_STUMAXL,
  AMED_AARCH64_MNEMONIC_STUMAXB,
  AMED_AARCH64_MNEMONIC_STUMAXLB,
  AMED_AARCH64_MNEMONIC_STUMAXH,
  AMED_AARCH64_MNEMONIC_STUMAXLH,
  AMED_AARCH64_MNEMONIC_STUMIN,
  AMED_AARCH64_MNEMONIC_STUMINL,
  AMED_AARCH64_MNEMONIC_STUMINB,
  AMED_AARCH64_MNEMONIC_STUMINLB,
  AMED_AARCH64_MNEMONIC_STUMINH,
  AMED_AARCH64_MNEMONIC_STUMINLH,
  AMED_AARCH64_MNEMONIC_SXTB,
  AMED_AARCH64_MNEMONIC_SXTH,
  AMED_AARCH64_MNEMONIC_SXTW,
  AMED_AARCH64_MNEMONIC_TLBI,
  AMED_AARCH64_MNEMONIC_TST,
  AMED_AARCH64_MNEMONIC_UBFIZ,
  AMED_AARCH64_MNEMONIC_UBFX,
  AMED_AARCH64_MNEMONIC_UMNEGL,
  AMED_AARCH64_MNEMONIC_UMULL,
  AMED_AARCH64_MNEMONIC_UXTB,
  AMED_AARCH64_MNEMONIC_UXTH,
  AMED_AARCH64_MNEMONIC_ABS,
  AMED_AARCH64_MNEMONIC_ADDHN,
  AMED_AARCH64_MNEMONIC_ADDHN2,
  AMED_AARCH64_MNEMONIC_ADDP,
  AMED_AARCH64_MNEMONIC_ADDV,
  AMED_AARCH64_MNEMONIC_AESD,
  AMED_AARCH64_MNEMONIC_AESE,
  AMED_AARCH64_MNEMONIC_AESIMC,
  AMED_AARCH64_MNEMONIC_AESMC,
  AMED_AARCH64_MNEMONIC_BCAX,
  AMED_AARCH64_MNEMONIC_BFCVT,
  AMED_AARCH64_MNEMONIC_BFCVTN,
  AMED_AARCH64_MNEMONIC_BFCVTN2,
  AMED_AARCH64_MNEMONIC_BFDOT,
  AMED_AARCH64_MNEMONIC_BFMLALB,
  AMED_AARCH64_MNEMONIC_BFMLALT,
  AMED_AARCH64_MNEMONIC_BFMMLA,
  AMED_AARCH64_MNEMONIC_BIF,
  AMED_AARCH64_MNEMONIC_BIT,
  AMED_AARCH64_MNEMONIC_BSL,
  AMED_AARCH64_MNEMONIC_CMEQ,
  AMED_AARCH64_MNEMONIC_CMGE,
  AMED_AARCH64_MNEMONIC_CMGT,
  AMED_AARCH64_MNEMONIC_CMHI,
  AMED_AARCH64_MNEMONIC_CMHS,
  AMED_AARCH64_MNEMONIC_CMLE,
  AMED_AARCH64_MNEMONIC_CMLT,
  AMED_AARCH64_MNEMONIC_CMTST,
  AMED_AARCH64_MNEMONIC_CNT,
  AMED_AARCH64_MNEMONIC_DUP,
  AMED_AARCH64_MNEMONIC_EOR3,
  AMED_AARCH64_MNEMONIC_EXT,
  AMED_AARCH64_MNEMONIC_FABD,
  AMED_AARCH64_MNEMONIC_FABS,
  AMED_AARCH64_MNEMONIC_FACGE,
  AMED_AARCH64_MNEMONIC_FACGT,
  AMED_AARCH64_MNEMONIC_FADD,
  AMED_AARCH64_MNEMONIC_FADDP,
  AMED_AARCH64_MNEMONIC_FCADD,
  AMED_AARCH64_MNEMONIC_FCCMP,
  AMED_AARCH64_MNEMONIC_FCCMPE,
  AMED_AARCH64_MNEMONIC_FCMEQ,
  AMED_AARCH64_MNEMONIC_FCMGE,
  AMED_AARCH64_MNEMONIC_FCMGT,
  AMED_AARCH64_MNEMONIC_FCMLA,
  AMED_AARCH64_MNEMONIC_FCMLE,
  AMED_AARCH64_MNEMONIC_FCMLT,
  AMED_AARCH64_MNEMONIC_FCMP,
  AMED_AARCH64_MNEMONIC_FCMPE,
  AMED_AARCH64_MNEMONIC_FCSEL,
  AMED_AARCH64_MNEMONIC_FCVT,
  AMED_AARCH64_MNEMONIC_FCVTAS,
  AMED_AARCH64_MNEMONIC_FCVTAU,
  AMED_AARCH64_MNEMONIC_FCVTL,
  AMED_AARCH64_MNEMONIC_FCVTL2,
  AMED_AARCH64_MNEMONIC_FCVTMS,
  AMED_AARCH64_MNEMONIC_FCVTMU,
  AMED_AARCH64_MNEMONIC_FCVTN,
  AMED_AARCH64_MNEMONIC_FCVTN2,
  AMED_AARCH64_MNEMONIC_FCVTNS,
  AMED_AARCH64_MNEMONIC_FCVTNU,
  AMED_AARCH64_MNEMONIC_FCVTPS,
  AMED_AARCH64_MNEMONIC_FCVTPU,
  AMED_AARCH64_MNEMONIC_FCVTXN,
  AMED_AARCH64_MNEMONIC_FCVTXN2,
  AMED_AARCH64_MNEMONIC_FCVTZS,
  AMED_AARCH64_MNEMONIC_FCVTZU,
  AMED_AARCH64_MNEMONIC_FDIV,
  AMED_AARCH64_MNEMONIC_FJCVTZS,
  AMED_AARCH64_MNEMONIC_FMADD,
  AMED_AARCH64_MNEMONIC_FMAX,
  AMED_AARCH64_MNEMONIC_FMAXNM,
  AMED_AARCH64_MNEMONIC_FMAXNMP,
  AMED_AARCH64_MNEMONIC_FMAXNMV,
  AMED_AARCH64_MNEMONIC_FMAXP,
  AMED_AARCH64_MNEMONIC_FMAXV,
  AMED_AARCH64_MNEMONIC_FMIN,
  AMED_AARCH64_MNEMONIC_FMINNM,
  AMED_AARCH64_MNEMONIC_FMINNMP,
  AMED_AARCH64_MNEMONIC_FMINNMV,
  AMED_AARCH64_MNEMONIC_FMINP,
  AMED_AARCH64_MNEMONIC_FMINV,
  AMED_AARCH64_MNEMONIC_FMLA,
  AMED_AARCH64_MNEMONIC_FMLAL,
  AMED_AARCH64_MNEMONIC_FMLAL2,
  AMED_AARCH64_MNEMONIC_FMLS,
  AMED_AARCH64_MNEMONIC_FMLSL,
  AMED_AARCH64_MNEMONIC_FMLSL2,
  AMED_AARCH64_MNEMONIC_FMOV,
  AMED_AARCH64_MNEMONIC_FMSUB,
  AMED_AARCH64_MNEMONIC_FMUL,
  AMED_AARCH64_MNEMONIC_FMULX,
  AMED_AARCH64_MNEMONIC_FNEG,
  AMED_AARCH64_MNEMONIC_FNMADD,
  AMED_AARCH64_MNEMONIC_FNMSUB,
  AMED_AARCH64_MNEMONIC_FNMUL,
  AMED_AARCH64_MNEMONIC_FRECPE,
  AMED_AARCH64_MNEMONIC_FRECPS,
  AMED_AARCH64_MNEMONIC_FRECPX,
  AMED_AARCH64_MNEMONIC_FRINT32X,
  AMED_AARCH64_MNEMONIC_FRINT32Z,
  AMED_AARCH64_MNEMONIC_FRINT64X,
  AMED_AARCH64_MNEMONIC_FRINT64Z,
  AMED_AARCH64_MNEMONIC_FRINTA,
  AMED_AARCH64_MNEMONIC_FRINTI,
  AMED_AARCH64_MNEMONIC_FRINTM,
  AMED_AARCH64_MNEMONIC_FRINTN,
  AMED_AARCH64_MNEMONIC_FRINTP,
  AMED_AARCH64_MNEMONIC_FRINTX,
  AMED_AARCH64_MNEMONIC_FRINTZ,
  AMED_AARCH64_MNEMONIC_FRSQRTE,
  AMED_AARCH64_MNEMONIC_FRSQRTS,
  AMED_AARCH64_MNEMONIC_FSQRT,
  AMED_AARCH64_MNEMONIC_FSUB,
  AMED_AARCH64_MNEMONIC_INS,
  AMED_AARCH64_MNEMONIC_LD1,
  AMED_AARCH64_MNEMONIC_LD1R,
  AMED_AARCH64_MNEMONIC_LD2,
  AMED_AARCH64_MNEMONIC_LD2R,
  AMED_AARCH64_MNEMONIC_LD3,
  AMED_AARCH64_MNEMONIC_LD3R,
  AMED_AARCH64_MNEMONIC_LD4,
  AMED_AARCH64_MNEMONIC_LD4R,
  AMED_AARCH64_MNEMONIC_MLA,
  AMED_AARCH64_MNEMONIC_MLS,
  AMED_AARCH64_MNEMONIC_MOVI,
  AMED_AARCH64_MNEMONIC_MVNI,
  AMED_AARCH64_MNEMONIC_NOT,
  AMED_AARCH64_MNEMONIC_PMUL,
  AMED_AARCH64_MNEMONIC_PMULL,
  AMED_AARCH64_MNEMONIC_PMULL2,
  AMED_AARCH64_MNEMONIC_RADDHN,
  AMED_AARCH64_MNEMONIC_RADDHN2,
  AMED_AARCH64_MNEMONIC_RAX1,
  AMED_AARCH64_MNEMONIC_RSHRN,
  AMED_AARCH64_MNEMONIC_RSHRN2,
  AMED_AARCH64_MNEMONIC_RSUBHN,
  AMED_AARCH64_MNEMONIC_RSUBHN2,
  AMED_AARCH64_MNEMONIC_SABA,
  AMED_AARCH64_MNEMONIC_SABAL,
  AMED_AARCH64_MNEMONIC_SABAL2,
  AMED_AARCH64_MNEMONIC_SABD,
  AMED_AARCH64_MNEMONIC_SABDL,
  AMED_AARCH64_MNEMONIC_SABDL2,
  AMED_AARCH64_MNEMONIC_SADALP,
  AMED_AARCH64_MNEMONIC_SADDL,
  AMED_AARCH64_MNEMONIC_SADDL2,
  AMED_AARCH64_MNEMONIC_SADDLP,
  AMED_AARCH64_MNEMONIC_SADDLV,
  AMED_AARCH64_MNEMONIC_SADDW,
  AMED_AARCH64_MNEMONIC_SADDW2,
  AMED_AARCH64_MNEMONIC_SCVTF,
  AMED_AARCH64_MNEMONIC_SDOT,
  AMED_AARCH64_MNEMONIC_SHA1C,
  AMED_AARCH64_MNEMONIC_SHA1H,
  AMED_AARCH64_MNEMONIC_SHA1M,
  AMED_AARCH64_MNEMONIC_SHA1P,
  AMED_AARCH64_MNEMONIC_SHA1SU0,
  AMED_AARCH64_MNEMONIC_SHA1SU1,
  AMED_AARCH64_MNEMONIC_SHA256H2,
  AMED_AARCH64_MNEMONIC_SHA256H,
  AMED_AARCH64_MNEMONIC_SHA256SU0,
  AMED_AARCH64_MNEMONIC_SHA256SU1,
  AMED_AARCH64_MNEMONIC_SHA512H2,
  AMED_AARCH64_MNEMONIC_SHA512H,
  AMED_AARCH64_MNEMONIC_SHA512SU0,
  AMED_AARCH64_MNEMONIC_SHA512SU1,
  AMED_AARCH64_MNEMONIC_SHADD,
  AMED_AARCH64_MNEMONIC_SHL,
  AMED_AARCH64_MNEMONIC_SHLL,
  AMED_AARCH64_MNEMONIC_SHLL2,
  AMED_AARCH64_MNEMONIC_SHRN,
  AMED_AARCH64_MNEMONIC_SHRN2,
  AMED_AARCH64_MNEMONIC_SHSUB,
  AMED_AARCH64_MNEMONIC_SLI,
  AMED_AARCH64_MNEMONIC_SM3PARTW1,
  AMED_AARCH64_MNEMONIC_SM3PARTW2,
  AMED_AARCH64_MNEMONIC_SM3SS1,
  AMED_AARCH64_MNEMONIC_SM3TT1A,
  AMED_AARCH64_MNEMONIC_SM3TT1B,
  AMED_AARCH64_MNEMONIC_SM3TT2A,
  AMED_AARCH64_MNEMONIC_SM3TT2B,
  AMED_AARCH64_MNEMONIC_SM4E,
  AMED_AARCH64_MNEMONIC_SM4EKEY,
  AMED_AARCH64_MNEMONIC_SMAX,
  AMED_AARCH64_MNEMONIC_SMAXP,
  AMED_AARCH64_MNEMONIC_SMAXV,
  AMED_AARCH64_MNEMONIC_SMIN,
  AMED_AARCH64_MNEMONIC_SMINP,
  AMED_AARCH64_MNEMONIC_SMINV,
  AMED_AARCH64_MNEMONIC_SMLAL,
  AMED_AARCH64_MNEMONIC_SMLAL2,
  AMED_AARCH64_MNEMONIC_SMLSL,
  AMED_AARCH64_MNEMONIC_SMLSL2,
  AMED_AARCH64_MNEMONIC_SMMLA,
  AMED_AARCH64_MNEMONIC_SMOV,
  AMED_AARCH64_MNEMONIC_SMULL2,
  AMED_AARCH64_MNEMONIC_SQABS,
  AMED_AARCH64_MNEMONIC_SQADD,
  AMED_AARCH64_MNEMONIC_SQDMLAL,
  AMED_AARCH64_MNEMONIC_SQDMLAL2,
  AMED_AARCH64_MNEMONIC_SQDMLSL,
  AMED_AARCH64_MNEMONIC_SQDMLSL2,
  AMED_AARCH64_MNEMONIC_SQDMULH,
  AMED_AARCH64_MNEMONIC_SQDMULL,
  AMED_AARCH64_MNEMONIC_SQDMULL2,
  AMED_AARCH64_MNEMONIC_SQNEG,
  AMED_AARCH64_MNEMONIC_SQRDMLAH,
  AMED_AARCH64_MNEMONIC_SQRDMLSH,
  AMED_AARCH64_MNEMONIC_SQRDMULH,
  AMED_AARCH64_MNEMONIC_SQRSHL,
  AMED_AARCH64_MNEMONIC_SQRSHRN,
  AMED_AARCH64_MNEMONIC_SQRSHRN2,
  AMED_AARCH64_MNEMONIC_SQRSHRUN,
  AMED_AARCH64_MNEMONIC_SQRSHRUN2,
  AMED_AARCH64_MNEMONIC_SQSHL,
  AMED_AARCH64_MNEMONIC_SQSHLU,
  AMED_AARCH64_MNEMONIC_SQSHRN,
  AMED_AARCH64_MNEMONIC_SQSHRN2,
  AMED_AARCH64_MNEMONIC_SQSHRUN,
  AMED_AARCH64_MNEMONIC_SQSHRUN2,
  AMED_AARCH64_MNEMONIC_SQSUB,
  AMED_AARCH64_MNEMONIC_SQXTN,
  AMED_AARCH64_MNEMONIC_SQXTN2,
  AMED_AARCH64_MNEMONIC_SQXTUN,
  AMED_AARCH64_MNEMONIC_SQXTUN2,
  AMED_AARCH64_MNEMONIC_SRHADD,
  AMED_AARCH64_MNEMONIC_SRI,
  AMED_AARCH64_MNEMONIC_SRSHL,
  AMED_AARCH64_MNEMONIC_SRSHR,
  AMED_AARCH64_MNEMONIC_SRSRA,
  AMED_AARCH64_MNEMONIC_SSHL,
  AMED_AARCH64_MNEMONIC_SSHLL,
  AMED_AARCH64_MNEMONIC_SSHLL2,
  AMED_AARCH64_MNEMONIC_SSHR,
  AMED_AARCH64_MNEMONIC_SSRA,
  AMED_AARCH64_MNEMONIC_SSUBL,
  AMED_AARCH64_MNEMONIC_SSUBL2,
  AMED_AARCH64_MNEMONIC_SSUBW,
  AMED_AARCH64_MNEMONIC_SSUBW2,
  AMED_AARCH64_MNEMONIC_ST1,
  AMED_AARCH64_MNEMONIC_ST2,
  AMED_AARCH64_MNEMONIC_ST3,
  AMED_AARCH64_MNEMONIC_ST4,
  AMED_AARCH64_MNEMONIC_SUBHN,
  AMED_AARCH64_MNEMONIC_SUBHN2,
  AMED_AARCH64_MNEMONIC_SUDOT,
  AMED_AARCH64_MNEMONIC_SUQADD,
  AMED_AARCH64_MNEMONIC_TBL,
  AMED_AARCH64_MNEMONIC_TBX,
  AMED_AARCH64_MNEMONIC_TRN1,
  AMED_AARCH64_MNEMONIC_TRN2,
  AMED_AARCH64_MNEMONIC_UABA,
  AMED_AARCH64_MNEMONIC_UABAL,
  AMED_AARCH64_MNEMONIC_UABAL2,
  AMED_AARCH64_MNEMONIC_UABD,
  AMED_AARCH64_MNEMONIC_UABDL,
  AMED_AARCH64_MNEMONIC_UABDL2,
  AMED_AARCH64_MNEMONIC_UADALP,
  AMED_AARCH64_MNEMONIC_UADDL,
  AMED_AARCH64_MNEMONIC_UADDL2,
  AMED_AARCH64_MNEMONIC_UADDLP,
  AMED_AARCH64_MNEMONIC_UADDLV,
  AMED_AARCH64_MNEMONIC_UADDW,
  AMED_AARCH64_MNEMONIC_UADDW2,
  AMED_AARCH64_MNEMONIC_UCVTF,
  AMED_AARCH64_MNEMONIC_UDOT,
  AMED_AARCH64_MNEMONIC_UHADD,
  AMED_AARCH64_MNEMONIC_UHSUB,
  AMED_AARCH64_MNEMONIC_UMAX,
  AMED_AARCH64_MNEMONIC_UMAXP,
  AMED_AARCH64_MNEMONIC_UMAXV,
  AMED_AARCH64_MNEMONIC_UMIN,
  AMED_AARCH64_MNEMONIC_UMINP,
  AMED_AARCH64_MNEMONIC_UMINV,
  AMED_AARCH64_MNEMONIC_UMLAL,
  AMED_AARCH64_MNEMONIC_UMLAL2,
  AMED_AARCH64_MNEMONIC_UMLSL,
  AMED_AARCH64_MNEMONIC_UMLSL2,
  AMED_AARCH64_MNEMONIC_UMMLA,
  AMED_AARCH64_MNEMONIC_UMOV,
  AMED_AARCH64_MNEMONIC_UMULL2,
  AMED_AARCH64_MNEMONIC_UQADD,
  AMED_AARCH64_MNEMONIC_UQRSHL,
  AMED_AARCH64_MNEMONIC_UQRSHRN,
  AMED_AARCH64_MNEMONIC_UQRSHRN2,
  AMED_AARCH64_MNEMONIC_UQSHL,
  AMED_AARCH64_MNEMONIC_UQSHRN,
  AMED_AARCH64_MNEMONIC_UQSHRN2,
  AMED_AARCH64_MNEMONIC_UQSUB,
  AMED_AARCH64_MNEMONIC_UQXTN,
  AMED_AARCH64_MNEMONIC_UQXTN2,
  AMED_AARCH64_MNEMONIC_URECPE,
  AMED_AARCH64_MNEMONIC_URHADD,
  AMED_AARCH64_MNEMONIC_URSHL,
  AMED_AARCH64_MNEMONIC_URSHR,
  AMED_AARCH64_MNEMONIC_URSQRTE,
  AMED_AARCH64_MNEMONIC_URSRA,
  AMED_AARCH64_MNEMONIC_USDOT,
  AMED_AARCH64_MNEMONIC_USHL,
  AMED_AARCH64_MNEMONIC_USHLL,
  AMED_AARCH64_MNEMONIC_USHLL2,
  AMED_AARCH64_MNEMONIC_USHR,
  AMED_AARCH64_MNEMONIC_USMMLA,
  AMED_AARCH64_MNEMONIC_USQADD,
  AMED_AARCH64_MNEMONIC_USRA,
  AMED_AARCH64_MNEMONIC_USUBL,
  AMED_AARCH64_MNEMONIC_USUBL2,
  AMED_AARCH64_MNEMONIC_USUBW,
  AMED_AARCH64_MNEMONIC_USUBW2,
  AMED_AARCH64_MNEMONIC_UZP1,
  AMED_AARCH64_MNEMONIC_UZP2,
  AMED_AARCH64_MNEMONIC_XAR,
  AMED_AARCH64_MNEMONIC_XTN,
  AMED_AARCH64_MNEMONIC_XTN2,
  AMED_AARCH64_MNEMONIC_ZIP1,
  AMED_AARCH64_MNEMONIC_ZIP2,
  AMED_AARCH64_MNEMONIC_SXTL,
  AMED_AARCH64_MNEMONIC_SXTL2,
  AMED_AARCH64_MNEMONIC_UXTL,
  AMED_AARCH64_MNEMONIC_UXTL2,
  AMED_AARCH64_MNEMONIC_ADCLB,
  AMED_AARCH64_MNEMONIC_ADCLT,
  AMED_AARCH64_MNEMONIC_ADDHNB,
  AMED_AARCH64_MNEMONIC_ADDHNT,
  AMED_AARCH64_MNEMONIC_ADDPL,
  AMED_AARCH64_MNEMONIC_ADDVL,
  AMED_AARCH64_MNEMONIC_ANDV,
  AMED_AARCH64_MNEMONIC_ASRD,
  AMED_AARCH64_MNEMONIC_ASRR,
  AMED_AARCH64_MNEMONIC_BDEP,
  AMED_AARCH64_MNEMONIC_BEXT,
  AMED_AARCH64_MNEMONIC_BFCVTNT,
  AMED_AARCH64_MNEMONIC_BGRP,
  AMED_AARCH64_MNEMONIC_BRKA,
  AMED_AARCH64_MNEMONIC_BRKAS,
  AMED_AARCH64_MNEMONIC_BRKB,
  AMED_AARCH64_MNEMONIC_BRKBS,
  AMED_AARCH64_MNEMONIC_BRKN,
  AMED_AARCH64_MNEMONIC_BRKNS,
  AMED_AARCH64_MNEMONIC_BRKPA,
  AMED_AARCH64_MNEMONIC_BRKPAS,
  AMED_AARCH64_MNEMONIC_BRKPB,
  AMED_AARCH64_MNEMONIC_BRKPBS,
  AMED_AARCH64_MNEMONIC_BSL1N,
  AMED_AARCH64_MNEMONIC_BSL2N,
  AMED_AARCH64_MNEMONIC_CADD,
  AMED_AARCH64_MNEMONIC_CDOT,
  AMED_AARCH64_MNEMONIC_CLASTA,
  AMED_AARCH64_MNEMONIC_CLASTB,
  AMED_AARCH64_MNEMONIC_CMLA,
  AMED_AARCH64_MNEMONIC_CMPEQ,
  AMED_AARCH64_MNEMONIC_CMPGT,
  AMED_AARCH64_MNEMONIC_CMPGE,
  AMED_AARCH64_MNEMONIC_CMPHI,
  AMED_AARCH64_MNEMONIC_CMPHS,
  AMED_AARCH64_MNEMONIC_CMPLT,
  AMED_AARCH64_MNEMONIC_CMPLE,
  AMED_AARCH64_MNEMONIC_CMPLO,
  AMED_AARCH64_MNEMONIC_CMPLS,
  AMED_AARCH64_MNEMONIC_CMPNE,
  AMED_AARCH64_MNEMONIC_CNOT,
  AMED_AARCH64_MNEMONIC_CNTB,
  AMED_AARCH64_MNEMONIC_CNTD,
  AMED_AARCH64_MNEMONIC_CNTH,
  AMED_AARCH64_MNEMONIC_CNTW,
  AMED_AARCH64_MNEMONIC_CNTP,
  AMED_AARCH64_MNEMONIC_COMPACT,
  AMED_AARCH64_MNEMONIC_CPY,
  AMED_AARCH64_MNEMONIC_CTERMEQ,
  AMED_AARCH64_MNEMONIC_CTERMNE,
  AMED_AARCH64_MNEMONIC_DECB,
  AMED_AARCH64_MNEMONIC_DECD,
  AMED_AARCH64_MNEMONIC_DECH,
  AMED_AARCH64_MNEMONIC_DECW,
  AMED_AARCH64_MNEMONIC_DECP,
  AMED_AARCH64_MNEMONIC_DUPM,
  AMED_AARCH64_MNEMONIC_EORS,
  AMED_AARCH64_MNEMONIC_EORBT,
  AMED_AARCH64_MNEMONIC_EORTB,
  AMED_AARCH64_MNEMONIC_EORV,
  AMED_AARCH64_MNEMONIC_FADDA,
  AMED_AARCH64_MNEMONIC_FADDV,
  AMED_AARCH64_MNEMONIC_FCMNE,
  AMED_AARCH64_MNEMONIC_FCMUO,
  AMED_AARCH64_MNEMONIC_FCPY,
  AMED_AARCH64_MNEMONIC_FCVTLT,
  AMED_AARCH64_MNEMONIC_FCVTNT,
  AMED_AARCH64_MNEMONIC_FCVTX,
  AMED_AARCH64_MNEMONIC_FCVTXNT,
  AMED_AARCH64_MNEMONIC_FDIVR,
  AMED_AARCH64_MNEMONIC_FDUP,
  AMED_AARCH64_MNEMONIC_FEXPA,
  AMED_AARCH64_MNEMONIC_FLOGB,
  AMED_AARCH64_MNEMONIC_FMAD,
  AMED_AARCH64_MNEMONIC_FMLALB,
  AMED_AARCH64_MNEMONIC_FMLALT,
  AMED_AARCH64_MNEMONIC_FMLSLB,
  AMED_AARCH64_MNEMONIC_FMLSLT,
  AMED_AARCH64_MNEMONIC_FMMLA,
  AMED_AARCH64_MNEMONIC_FMSB,
  AMED_AARCH64_MNEMONIC_FNMAD,
  AMED_AARCH64_MNEMONIC_FNMLA,
  AMED_AARCH64_MNEMONIC_FNMLS,
  AMED_AARCH64_MNEMONIC_FNMSB,
  AMED_AARCH64_MNEMONIC_FSCALE,
  AMED_AARCH64_MNEMONIC_FSUBR,
  AMED_AARCH64_MNEMONIC_FTMAD,
  AMED_AARCH64_MNEMONIC_FTSMUL,
  AMED_AARCH64_MNEMONIC_FTSSEL,
  AMED_AARCH64_MNEMONIC_HISTCNT,
  AMED_AARCH64_MNEMONIC_HISTSEG,
  AMED_AARCH64_MNEMONIC_INCB,
  AMED_AARCH64_MNEMONIC_INCD,
  AMED_AARCH64_MNEMONIC_INCH,
  AMED_AARCH64_MNEMONIC_INCW,
  AMED_AARCH64_MNEMONIC_INCP,
  AMED_AARCH64_MNEMONIC_INDEX,
  AMED_AARCH64_MNEMONIC_INSR,
  AMED_AARCH64_MNEMONIC_LASTA,
  AMED_AARCH64_MNEMONIC_LASTB,
  AMED_AARCH64_MNEMONIC_LD1B,
  AMED_AARCH64_MNEMONIC_LD1D,
  AMED_AARCH64_MNEMONIC_LD1H,
  AMED_AARCH64_MNEMONIC_LD1RB,
  AMED_AARCH64_MNEMONIC_LD1RD,
  AMED_AARCH64_MNEMONIC_LD1RH,
  AMED_AARCH64_MNEMONIC_LD1ROB,
  AMED_AARCH64_MNEMONIC_LD1ROD,
  AMED_AARCH64_MNEMONIC_LD1ROH,
  AMED_AARCH64_MNEMONIC_LD1ROW,
  AMED_AARCH64_MNEMONIC_LD1RQB,
  AMED_AARCH64_MNEMONIC_LD1RQD,
  AMED_AARCH64_MNEMONIC_LD1RQH,
  AMED_AARCH64_MNEMONIC_LD1RQW,
  AMED_AARCH64_MNEMONIC_LD1RSB,
  AMED_AARCH64_MNEMONIC_LD1RSH,
  AMED_AARCH64_MNEMONIC_LD1RSW,
  AMED_AARCH64_MNEMONIC_LD1RW,
  AMED_AARCH64_MNEMONIC_LD1SB,
  AMED_AARCH64_MNEMONIC_LD1SH,
  AMED_AARCH64_MNEMONIC_LD1SW,
  AMED_AARCH64_MNEMONIC_LD1W,
  AMED_AARCH64_MNEMONIC_LD2B,
  AMED_AARCH64_MNEMONIC_LD2D,
  AMED_AARCH64_MNEMONIC_LD2H,
  AMED_AARCH64_MNEMONIC_LD2W,
  AMED_AARCH64_MNEMONIC_LD3B,
  AMED_AARCH64_MNEMONIC_LD3D,
  AMED_AARCH64_MNEMONIC_LD3H,
  AMED_AARCH64_MNEMONIC_LD3W,
  AMED_AARCH64_MNEMONIC_LD4B,
  AMED_AARCH64_MNEMONIC_LD4D,
  AMED_AARCH64_MNEMONIC_LD4H,
  AMED_AARCH64_MNEMONIC_LD4W,
  AMED_AARCH64_MNEMONIC_LDFF1B,
  AMED_AARCH64_MNEMONIC_LDFF1D,
  AMED_AARCH64_MNEMONIC_LDFF1H,
  AMED_AARCH64_MNEMONIC_LDFF1SB,
  AMED_AARCH64_MNEMONIC_LDFF1SH,
  AMED_AARCH64_MNEMONIC_LDFF1SW,
  AMED_AARCH64_MNEMONIC_LDFF1W,
  AMED_AARCH64_MNEMONIC_LDNF1B,
  AMED_AARCH64_MNEMONIC_LDNF1D,
  AMED_AARCH64_MNEMONIC_LDNF1H,
  AMED_AARCH64_MNEMONIC_LDNF1SB,
  AMED_AARCH64_MNEMONIC_LDNF1SH,
  AMED_AARCH64_MNEMONIC_LDNF1SW,
  AMED_AARCH64_MNEMONIC_LDNF1W,
  AMED_AARCH64_MNEMONIC_LDNT1B,
  AMED_AARCH64_MNEMONIC_LDNT1D,
  AMED_AARCH64_MNEMONIC_LDNT1H,
  AMED_AARCH64_MNEMONIC_LDNT1SB,
  AMED_AARCH64_MNEMONIC_LDNT1SH,
  AMED_AARCH64_MNEMONIC_LDNT1SW,
  AMED_AARCH64_MNEMONIC_LDNT1W,
  AMED_AARCH64_MNEMONIC_LSLR,
  AMED_AARCH64_MNEMONIC_LSRR,
  AMED_AARCH64_MNEMONIC_MAD,
  AMED_AARCH64_MNEMONIC_MATCH,
  AMED_AARCH64_MNEMONIC_MOVPRFX,
  AMED_AARCH64_MNEMONIC_MSB,
  AMED_AARCH64_MNEMONIC_NAND,
  AMED_AARCH64_MNEMONIC_NANDS,
  AMED_AARCH64_MNEMONIC_NBSL,
  AMED_AARCH64_MNEMONIC_NMATCH,
  AMED_AARCH64_MNEMONIC_NOR,
  AMED_AARCH64_MNEMONIC_NORS,
  AMED_AARCH64_MNEMONIC_ORNS,
  AMED_AARCH64_MNEMONIC_ORRS,
  AMED_AARCH64_MNEMONIC_ORV,
  AMED_AARCH64_MNEMONIC_PFALSE,
  AMED_AARCH64_MNEMONIC_PFIRST,
  AMED_AARCH64_MNEMONIC_PMULLB,
  AMED_AARCH64_MNEMONIC_PMULLT,
  AMED_AARCH64_MNEMONIC_PNEXT,
  AMED_AARCH64_MNEMONIC_PRFB,
  AMED_AARCH64_MNEMONIC_PRFD,
  AMED_AARCH64_MNEMONIC_PRFH,
  AMED_AARCH64_MNEMONIC_PRFW,
  AMED_AARCH64_MNEMONIC_PTEST,
  AMED_AARCH64_MNEMONIC_PTRUE,
  AMED_AARCH64_MNEMONIC_PTRUES,
  AMED_AARCH64_MNEMONIC_PUNPKHI,
  AMED_AARCH64_MNEMONIC_PUNPKLO,
  AMED_AARCH64_MNEMONIC_RADDHNB,
  AMED_AARCH64_MNEMONIC_RADDHNT,
  AMED_AARCH64_MNEMONIC_RDFFR,
  AMED_AARCH64_MNEMONIC_RDFFRS,
  AMED_AARCH64_MNEMONIC_RDVL,
  AMED_AARCH64_MNEMONIC_REVB,
  AMED_AARCH64_MNEMONIC_REVH,
  AMED_AARCH64_MNEMONIC_REVW,
  AMED_AARCH64_MNEMONIC_RSHRNB,
  AMED_AARCH64_MNEMONIC_RSHRNT,
  AMED_AARCH64_MNEMONIC_RSUBHNB,
  AMED_AARCH64_MNEMONIC_RSUBHNT,
  AMED_AARCH64_MNEMONIC_SABALB,
  AMED_AARCH64_MNEMONIC_SABALT,
  AMED_AARCH64_MNEMONIC_SABDLB,
  AMED_AARCH64_MNEMONIC_SABDLT,
  AMED_AARCH64_MNEMONIC_SADDLB,
  AMED_AARCH64_MNEMONIC_SADDLBT,
  AMED_AARCH64_MNEMONIC_SADDLT,
  AMED_AARCH64_MNEMONIC_SADDV,
  AMED_AARCH64_MNEMONIC_SADDWB,
  AMED_AARCH64_MNEMONIC_SADDWT,
  AMED_AARCH64_MNEMONIC_SBCLB,
  AMED_AARCH64_MNEMONIC_SBCLT,
  AMED_AARCH64_MNEMONIC_SDIVR,
  AMED_AARCH64_MNEMONIC_SEL,
  AMED_AARCH64_MNEMONIC_SETFFR,
  AMED_AARCH64_MNEMONIC_SHRNB,
  AMED_AARCH64_MNEMONIC_SHRNT,
  AMED_AARCH64_MNEMONIC_SHSUBR,
  AMED_AARCH64_MNEMONIC_SMLALB,
  AMED_AARCH64_MNEMONIC_SMLALT,
  AMED_AARCH64_MNEMONIC_SMLSLB,
  AMED_AARCH64_MNEMONIC_SMLSLT,
  AMED_AARCH64_MNEMONIC_SMULLB,
  AMED_AARCH64_MNEMONIC_SMULLT,
  AMED_AARCH64_MNEMONIC_SPLICE,
  AMED_AARCH64_MNEMONIC_SQCADD,
  AMED_AARCH64_MNEMONIC_SQDECB,
  AMED_AARCH64_MNEMONIC_SQDECD,
  AMED_AARCH64_MNEMONIC_SQDECH,
  AMED_AARCH64_MNEMONIC_SQDECP,
  AMED_AARCH64_MNEMONIC_SQDECW,
  AMED_AARCH64_MNEMONIC_SQDMLALB,
  AMED_AARCH64_MNEMONIC_SQDMLALBT,
  AMED_AARCH64_MNEMONIC_SQDMLALT,
  AMED_AARCH64_MNEMONIC_SQDMLSLB,
  AMED_AARCH64_MNEMONIC_SQDMLSLBT,
  AMED_AARCH64_MNEMONIC_SQDMLSLT,
  AMED_AARCH64_MNEMONIC_SQDMULLB,
  AMED_AARCH64_MNEMONIC_SQDMULLT,
  AMED_AARCH64_MNEMONIC_SQINCB,
  AMED_AARCH64_MNEMONIC_SQINCD,
  AMED_AARCH64_MNEMONIC_SQINCH,
  AMED_AARCH64_MNEMONIC_SQINCP,
  AMED_AARCH64_MNEMONIC_SQINCW,
  AMED_AARCH64_MNEMONIC_SQRDCMLAH,
  AMED_AARCH64_MNEMONIC_SQRSHLR,
  AMED_AARCH64_MNEMONIC_SQRSHRNB,
  AMED_AARCH64_MNEMONIC_SQRSHRNT,
  AMED_AARCH64_MNEMONIC_SQRSHRUNB,
  AMED_AARCH64_MNEMONIC_SQRSHRUNT,
  AMED_AARCH64_MNEMONIC_SQSHLR,
  AMED_AARCH64_MNEMONIC_SQSHRNB,
  AMED_AARCH64_MNEMONIC_SQSHRNT,
  AMED_AARCH64_MNEMONIC_SQSHRUNB,
  AMED_AARCH64_MNEMONIC_SQSHRUNT,
  AMED_AARCH64_MNEMONIC_SQSUBR,
  AMED_AARCH64_MNEMONIC_SQXTNB,
  AMED_AARCH64_MNEMONIC_SQXTNT,
  AMED_AARCH64_MNEMONIC_SQXTUNB,
  AMED_AARCH64_MNEMONIC_SQXTUNT,
  AMED_AARCH64_MNEMONIC_SRSHLR,
  AMED_AARCH64_MNEMONIC_SSHLLB,
  AMED_AARCH64_MNEMONIC_SSHLLT,
  AMED_AARCH64_MNEMONIC_SSUBLB,
  AMED_AARCH64_MNEMONIC_SSUBLBT,
  AMED_AARCH64_MNEMONIC_SSUBLT,
  AMED_AARCH64_MNEMONIC_SSUBLTB,
  AMED_AARCH64_MNEMONIC_SSUBWB,
  AMED_AARCH64_MNEMONIC_SSUBWT,
  AMED_AARCH64_MNEMONIC_ST1B,
  AMED_AARCH64_MNEMONIC_ST1D,
  AMED_AARCH64_MNEMONIC_ST1H,
  AMED_AARCH64_MNEMONIC_ST1W,
  AMED_AARCH64_MNEMONIC_ST2B,
  AMED_AARCH64_MNEMONIC_ST2D,
  AMED_AARCH64_MNEMONIC_ST2H,
  AMED_AARCH64_MNEMONIC_ST2W,
  AMED_AARCH64_MNEMONIC_ST3B,
  AMED_AARCH64_MNEMONIC_ST3D,
  AMED_AARCH64_MNEMONIC_ST3H,
  AMED_AARCH64_MNEMONIC_ST3W,
  AMED_AARCH64_MNEMONIC_ST4B,
  AMED_AARCH64_MNEMONIC_ST4D,
  AMED_AARCH64_MNEMONIC_ST4H,
  AMED_AARCH64_MNEMONIC_ST4W,
  AMED_AARCH64_MNEMONIC_STNT1B,
  AMED_AARCH64_MNEMONIC_STNT1D,
  AMED_AARCH64_MNEMONIC_STNT1H,
  AMED_AARCH64_MNEMONIC_STNT1W,
  AMED_AARCH64_MNEMONIC_SUBHNB,
  AMED_AARCH64_MNEMONIC_SUBHNT,
  AMED_AARCH64_MNEMONIC_SUBR,
  AMED_AARCH64_MNEMONIC_SUNPKHI,
  AMED_AARCH64_MNEMONIC_SUNPKLO,
  AMED_AARCH64_MNEMONIC_UABALB,
  AMED_AARCH64_MNEMONIC_UABALT,
  AMED_AARCH64_MNEMONIC_UABDLB,
  AMED_AARCH64_MNEMONIC_UABDLT,
  AMED_AARCH64_MNEMONIC_UADDLB,
  AMED_AARCH64_MNEMONIC_UADDLT,
  AMED_AARCH64_MNEMONIC_UADDV,
  AMED_AARCH64_MNEMONIC_UADDWB,
  AMED_AARCH64_MNEMONIC_UADDWT,
  AMED_AARCH64_MNEMONIC_UDIVR,
  AMED_AARCH64_MNEMONIC_UHSUBR,
  AMED_AARCH64_MNEMONIC_UMLALB,
  AMED_AARCH64_MNEMONIC_UMLALT,
  AMED_AARCH64_MNEMONIC_UMLSLB,
  AMED_AARCH64_MNEMONIC_UMLSLT,
  AMED_AARCH64_MNEMONIC_UMULLB,
  AMED_AARCH64_MNEMONIC_UMULLT,
  AMED_AARCH64_MNEMONIC_UQDECB,
  AMED_AARCH64_MNEMONIC_UQDECD,
  AMED_AARCH64_MNEMONIC_UQDECH,
  AMED_AARCH64_MNEMONIC_UQDECP,
  AMED_AARCH64_MNEMONIC_UQDECW,
  AMED_AARCH64_MNEMONIC_UQINCB,
  AMED_AARCH64_MNEMONIC_UQINCD,
  AMED_AARCH64_MNEMONIC_UQINCH,
  AMED_AARCH64_MNEMONIC_UQINCP,
  AMED_AARCH64_MNEMONIC_UQINCW,
  AMED_AARCH64_MNEMONIC_UQRSHLR,
  AMED_AARCH64_MNEMONIC_UQRSHRNB,
  AMED_AARCH64_MNEMONIC_UQRSHRNT,
  AMED_AARCH64_MNEMONIC_UQSHLR,
  AMED_AARCH64_MNEMONIC_UQSHRNB,
  AMED_AARCH64_MNEMONIC_UQSHRNT,
  AMED_AARCH64_MNEMONIC_UQSUBR,
  AMED_AARCH64_MNEMONIC_UQXTNB,
  AMED_AARCH64_MNEMONIC_UQXTNT,
  AMED_AARCH64_MNEMONIC_URSHLR,
  AMED_AARCH64_MNEMONIC_USHLLB,
  AMED_AARCH64_MNEMONIC_USHLLT,
  AMED_AARCH64_MNEMONIC_USUBLB,
  AMED_AARCH64_MNEMONIC_USUBLT,
  AMED_AARCH64_MNEMONIC_USUBWB,
  AMED_AARCH64_MNEMONIC_USUBWT,
  AMED_AARCH64_MNEMONIC_UUNPKHI,
  AMED_AARCH64_MNEMONIC_UUNPKLO,
  AMED_AARCH64_MNEMONIC_UXTW,
  AMED_AARCH64_MNEMONIC_WHILEGE,
  AMED_AARCH64_MNEMONIC_WHILEGT,
  AMED_AARCH64_MNEMONIC_WHILEHI,
  AMED_AARCH64_MNEMONIC_WHILEHS,
  AMED_AARCH64_MNEMONIC_WHILELE,
  AMED_AARCH64_MNEMONIC_WHILELO,
  AMED_AARCH64_MNEMONIC_WHILELS,
  AMED_AARCH64_MNEMONIC_WHILELT,
  AMED_AARCH64_MNEMONIC_WHILERW,
  AMED_AARCH64_MNEMONIC_WHILEWR,
  AMED_AARCH64_MNEMONIC_WRFFR,
  AMED_AARCH64_MNEMONIC_FACLE,
  AMED_AARCH64_MNEMONIC_FACLT,
  AMED_AARCH64_MNEMONIC_MOVS,
  AMED_AARCH64_MNEMONIC_NOTS,
} amed_aarch64_mnemonic;

#define AMED_AARCH64_BTI_OP_MAX_TEXT_LENGTH (4 + 1)

typedef enum _amed_aarch64_bti_op
{
  AMED_AARCH64_BTI_OP_NONE,
  AMED_AARCH64_BTI_OP_c,
  AMED_AARCH64_BTI_OP_j,
  AMED_AARCH64_BTI_OP_jc,
} amed_aarch64_bti_op;

#define AMED_AARCH64_AT_OP_MAX_TEXT_LENGTH (6 + 1)

typedef enum _amed_aarch64_at_op
{
  AMED_AARCH64_AT_OP_NONE,
  AMED_AARCH64_AT_OP_S12E0R,
  AMED_AARCH64_AT_OP_S12E0W,
  AMED_AARCH64_AT_OP_S12E1R,
  AMED_AARCH64_AT_OP_S12E1W,
  AMED_AARCH64_AT_OP_S1E0R,
  AMED_AARCH64_AT_OP_S1E0W,
  AMED_AARCH64_AT_OP_S1E1R,
  AMED_AARCH64_AT_OP_S1E1RP,
  AMED_AARCH64_AT_OP_S1E1W,
  AMED_AARCH64_AT_OP_S1E1WP,
  AMED_AARCH64_AT_OP_S1E2R,
  AMED_AARCH64_AT_OP_S1E2W,
  AMED_AARCH64_AT_OP_S1E3R,
  AMED_AARCH64_AT_OP_S1E3W,
} amed_aarch64_at_op;

#define AMED_AARCH64_IC_OP_MAX_TEXT_LENGTH (7 + 1)

typedef enum _amed_aarch64_ic_op
{
  AMED_AARCH64_IC_OP_NONE,
  AMED_AARCH64_IC_OP_IALLU,
  AMED_AARCH64_IC_OP_IALLUIS,
  AMED_AARCH64_IC_OP_IVAU,
} amed_aarch64_ic_op;

#define AMED_AARCH64_SYNC_OP_MAX_TEXT_LENGTH (5 + 1)

typedef enum _amed_aarch64_sync_op
{
  AMED_AARCH64_SYNC_OP_NONE,
  AMED_AARCH64_SYNC_OP_CSYNC,
} amed_aarch64_sync_op;

#define AMED_AARCH64_PATTERN_MAX_TEXT_LENGTH (5 + 1)

typedef enum _amed_aarch64_pattern
{
  AMED_AARCH64_PATTERN_NONE,
  AMED_AARCH64_PATTERN_ALL,
  AMED_AARCH64_PATTERN_MUL3,
  AMED_AARCH64_PATTERN_MUL4,
  AMED_AARCH64_PATTERN_POW2,
  AMED_AARCH64_PATTERN_VL1,
  AMED_AARCH64_PATTERN_VL128,
  AMED_AARCH64_PATTERN_VL16,
  AMED_AARCH64_PATTERN_VL2,
  AMED_AARCH64_PATTERN_VL256,
  AMED_AARCH64_PATTERN_VL3,
  AMED_AARCH64_PATTERN_VL32,
  AMED_AARCH64_PATTERN_VL4,
  AMED_AARCH64_PATTERN_VL5,
  AMED_AARCH64_PATTERN_VL6,
  AMED_AARCH64_PATTERN_VL64,
  AMED_AARCH64_PATTERN_VL7,
  AMED_AARCH64_PATTERN_VL8,
  AMED_AARCH64_PATTERN_uimm5,
} amed_aarch64_pattern;

#define AMED_AARCH64_CTX_OP_MAX_TEXT_LENGTH (4 + 1)

typedef enum _amed_aarch64_ctx_op
{
  AMED_AARCH64_CTX_OP_NONE,
  AMED_AARCH64_CTX_OP_RCTX,
} amed_aarch64_ctx_op;

#define AMED_AARCH64_PAGE_MAX_TEXT_LENGTH (22 + 1)

typedef enum _amed_aarch64_page
{
  AMED_AARCH64_PAGE_NONE,
  AMED_AARCH64_PAGE_invalid, //!< invalid:invalid
  AMED_AARCH64_PAGE_ADC, //!< <a href="../target/aarch64/ADC.html">ADC:Add with Carry</a>
  AMED_AARCH64_PAGE_ADCS, //!< <a href="../target/aarch64/ADCS.html">ADCS:Add with Carry, setting flags</a>
  AMED_AARCH64_PAGE_ADD_addsub_ext, //!< <a href="../target/aarch64/ADD_addsub_ext.html">ADD (extended register):Add (extended register)</a>
  AMED_AARCH64_PAGE_ADD_addsub_imm, //!< <a href="../target/aarch64/ADD_addsub_imm.html">ADD (immediate):Add (immediate)</a>
  AMED_AARCH64_PAGE_ADD_addsub_shift, //!< <a href="../target/aarch64/ADD_addsub_shift.html">ADD (shifted register):Add (shifted register)</a>
  AMED_AARCH64_PAGE_ADDG, //!< <a href="../target/aarch64/ADDG.html">ADDG:Add with Tag</a>
  AMED_AARCH64_PAGE_ADDS_addsub_ext, //!< <a href="../target/aarch64/ADDS_addsub_ext.html">ADDS (extended register):Add (extended register), setting flags</a>
  AMED_AARCH64_PAGE_ADDS_addsub_imm, //!< <a href="../target/aarch64/ADDS_addsub_imm.html">ADDS (immediate):Add (immediate), setting flags</a>
  AMED_AARCH64_PAGE_ADDS_addsub_shift, //!< <a href="../target/aarch64/ADDS_addsub_shift.html">ADDS (shifted register):Add (shifted register), setting flags</a>
  AMED_AARCH64_PAGE_ADR, //!< <a href="../target/aarch64/ADR.html">ADR:Form PC-relative address</a>
  AMED_AARCH64_PAGE_ADRP, //!< <a href="../target/aarch64/ADRP.html">ADRP:Form PC-relative address to 4KB page</a>
  AMED_AARCH64_PAGE_AND_log_imm, //!< <a href="../target/aarch64/AND_log_imm.html">AND (immediate):Bitwise AND (immediate)</a>
  AMED_AARCH64_PAGE_AND_log_shift, //!< <a href="../target/aarch64/AND_log_shift.html">AND (shifted register):Bitwise AND (shifted register)</a>
  AMED_AARCH64_PAGE_ANDS_log_imm, //!< <a href="../target/aarch64/ANDS_log_imm.html">ANDS (immediate):Bitwise AND (immediate), setting flags</a>
  AMED_AARCH64_PAGE_ANDS_log_shift, //!< <a href="../target/aarch64/ANDS_log_shift.html">ANDS (shifted register):Bitwise AND (shifted register), setting flags</a>
  AMED_AARCH64_PAGE_ASRV, //!< <a href="../target/aarch64/ASRV.html">ASRV:Arithmetic Shift Right Variable</a>
  AMED_AARCH64_PAGE_AUTDA, //!< <a href="../target/aarch64/AUTDA.html">AUTDA, AUTDZA:Authenticate Data address, using key A</a>
  AMED_AARCH64_PAGE_AUTDB, //!< <a href="../target/aarch64/AUTDB.html">AUTDB, AUTDZB:Authenticate Data address, using key B</a>
  AMED_AARCH64_PAGE_AUTIA, //!< <a href="../target/aarch64/AUTIA.html">AUTIA, AUTIA1716, AUTIASP, AUTIAZ, AUTIZA:Authenticate Instruction address, using key A</a>
  AMED_AARCH64_PAGE_AUTIB, //!< <a href="../target/aarch64/AUTIB.html">AUTIB, AUTIB1716, AUTIBSP, AUTIBZ, AUTIZB:Authenticate Instruction address, using key B</a>
  AMED_AARCH64_PAGE_AXFLAG, //!< <a href="../target/aarch64/AXFLAG.html">AXFLAG:Convert floating-point condition flags from Arm to external format</a>
  AMED_AARCH64_PAGE_B_cond, //!< <a href="../target/aarch64/B_cond.html">B.cond:Branch conditionally</a>
  AMED_AARCH64_PAGE_B_uncond, //!< <a href="../target/aarch64/B_uncond.html">B:Branch</a>
  AMED_AARCH64_PAGE_BFM, //!< <a href="../target/aarch64/BFM.html">BFM:Bitfield Move</a>
  AMED_AARCH64_PAGE_BIC_log_shift, //!< <a href="../target/aarch64/BIC_log_shift.html">BIC (shifted register):Bitwise Bit Clear (shifted register)</a>
  AMED_AARCH64_PAGE_BICS, //!< <a href="../target/aarch64/BICS.html">BICS (shifted register):Bitwise Bit Clear (shifted register), setting flags</a>
  AMED_AARCH64_PAGE_BL, //!< <a href="../target/aarch64/BL.html">BL:Branch with Link</a>
  AMED_AARCH64_PAGE_BLR, //!< <a href="../target/aarch64/BLR.html">BLR:Branch with Link to Register</a>
  AMED_AARCH64_PAGE_BLRA, //!< <a href="../target/aarch64/BLRA.html">BLRAA, BLRAAZ, BLRAB, BLRABZ:Branch with Link to Register, with pointer authentication</a>
  AMED_AARCH64_PAGE_BR, //!< <a href="../target/aarch64/BR.html">BR:Branch to Register</a>
  AMED_AARCH64_PAGE_BRA, //!< <a href="../target/aarch64/BRA.html">BRAA, BRAAZ, BRAB, BRABZ:Branch to Register, with pointer authentication</a>
  AMED_AARCH64_PAGE_BRK, //!< <a href="../target/aarch64/BRK.html">BRK:Breakpoint instruction</a>
  AMED_AARCH64_PAGE_BTI, //!< <a href="../target/aarch64/BTI.html">BTI:Branch Target Identification</a>
  AMED_AARCH64_PAGE_CAS, //!< <a href="../target/aarch64/CAS.html">CAS, CASA, CASAL, CASL:Compare and Swap word or doubleword in memory</a>
  AMED_AARCH64_PAGE_CASB, //!< <a href="../target/aarch64/CASB.html">CASB, CASAB, CASALB, CASLB:Compare and Swap byte in memory</a>
  AMED_AARCH64_PAGE_CASH, //!< <a href="../target/aarch64/CASH.html">CASH, CASAH, CASALH, CASLH:Compare and Swap halfword in memory</a>
  AMED_AARCH64_PAGE_CASP, //!< <a href="../target/aarch64/CASP.html">CASP, CASPA, CASPAL, CASPL:Compare and Swap Pair of words or doublewords in memory</a>
  AMED_AARCH64_PAGE_CBNZ, //!< <a href="../target/aarch64/CBNZ.html">CBNZ:Compare and Branch on Nonzero</a>
  AMED_AARCH64_PAGE_CBZ, //!< <a href="../target/aarch64/CBZ.html">CBZ:Compare and Branch on Zero</a>
  AMED_AARCH64_PAGE_CCMN_imm, //!< <a href="../target/aarch64/CCMN_imm.html">CCMN (immediate):Conditional Compare Negative (immediate)</a>
  AMED_AARCH64_PAGE_CCMN_reg, //!< <a href="../target/aarch64/CCMN_reg.html">CCMN (register):Conditional Compare Negative (register)</a>
  AMED_AARCH64_PAGE_CCMP_imm, //!< <a href="../target/aarch64/CCMP_imm.html">CCMP (immediate):Conditional Compare (immediate)</a>
  AMED_AARCH64_PAGE_CCMP_reg, //!< <a href="../target/aarch64/CCMP_reg.html">CCMP (register):Conditional Compare (register)</a>
  AMED_AARCH64_PAGE_CFINV, //!< <a href="../target/aarch64/CFINV.html">CFINV:Invert Carry Flag</a>
  AMED_AARCH64_PAGE_CLREX, //!< <a href="../target/aarch64/CLREX.html">CLREX:Clear Exclusive</a>
  AMED_AARCH64_PAGE_CLS_int, //!< <a href="../target/aarch64/CLS_int.html">CLS:Count Leading Sign bits</a>
  AMED_AARCH64_PAGE_CLZ_int, //!< <a href="../target/aarch64/CLZ_int.html">CLZ:Count Leading Zeros</a>
  AMED_AARCH64_PAGE_CRC32, //!< <a href="../target/aarch64/CRC32.html">CRC32B, CRC32H, CRC32W, CRC32X:CRC32 checksum</a>
  AMED_AARCH64_PAGE_CRC32C, //!< <a href="../target/aarch64/CRC32C.html">CRC32CB, CRC32CH, CRC32CW, CRC32CX:CRC32C checksum</a>
  AMED_AARCH64_PAGE_CSDB, //!< <a href="../target/aarch64/CSDB.html">CSDB:Consumption of Speculative Data Barrier</a>
  AMED_AARCH64_PAGE_CSEL, //!< <a href="../target/aarch64/CSEL.html">CSEL:Conditional Select</a>
  AMED_AARCH64_PAGE_CSINC, //!< <a href="../target/aarch64/CSINC.html">CSINC:Conditional Select Increment</a>
  AMED_AARCH64_PAGE_CSINV, //!< <a href="../target/aarch64/CSINV.html">CSINV:Conditional Select Invert</a>
  AMED_AARCH64_PAGE_CSNEG, //!< <a href="../target/aarch64/CSNEG.html">CSNEG:Conditional Select Negation</a>
  AMED_AARCH64_PAGE_DCPS1, //!< <a href="../target/aarch64/DCPS1.html">DCPS1:Debug Change PE State to EL1.</a>
  AMED_AARCH64_PAGE_DCPS2, //!< <a href="../target/aarch64/DCPS2.html">DCPS2:Debug Change PE State to EL2.</a>
  AMED_AARCH64_PAGE_DCPS3, //!< <a href="../target/aarch64/DCPS3.html">DCPS3:Debug Change PE State to EL3</a>
  AMED_AARCH64_PAGE_DGH, //!< <a href="../target/aarch64/DGH.html">DGH:Data Gathering Hint</a>
  AMED_AARCH64_PAGE_DMB, //!< <a href="../target/aarch64/DMB.html">DMB:Data Memory Barrier</a>
  AMED_AARCH64_PAGE_DRPS, //!< <a href="../target/aarch64/DRPS.html">DRPS:Debug restore process state</a>
  AMED_AARCH64_PAGE_DSB, //!< <a href="../target/aarch64/DSB.html">DSB:Data Synchronization Barrier</a>
  AMED_AARCH64_PAGE_EON, //!< <a href="../target/aarch64/EON.html">EON (shifted register):Bitwise Exclusive OR NOT (shifted register)</a>
  AMED_AARCH64_PAGE_EOR_log_imm, //!< <a href="../target/aarch64/EOR_log_imm.html">EOR (immediate):Bitwise Exclusive OR (immediate)</a>
  AMED_AARCH64_PAGE_EOR_log_shift, //!< <a href="../target/aarch64/EOR_log_shift.html">EOR (shifted register):Bitwise Exclusive OR (shifted register)</a>
  AMED_AARCH64_PAGE_ERET, //!< <a href="../target/aarch64/ERET.html">ERET:Exception Return</a>
  AMED_AARCH64_PAGE_ERETA, //!< <a href="../target/aarch64/ERETA.html">ERETAA, ERETAB:Exception Return, with pointer authentication</a>
  AMED_AARCH64_PAGE_ESB, //!< <a href="../target/aarch64/ESB.html">ESB:Error Synchronization Barrier</a>
  AMED_AARCH64_PAGE_EXTR, //!< <a href="../target/aarch64/EXTR.html">EXTR:Extract register</a>
  AMED_AARCH64_PAGE_GMI, //!< <a href="../target/aarch64/GMI.html">GMI:Tag Mask Insert</a>
  AMED_AARCH64_PAGE_HINT, //!< <a href="../target/aarch64/HINT.html">HINT:Hint instruction</a>
  AMED_AARCH64_PAGE_HLT, //!< <a href="../target/aarch64/HLT.html">HLT:Halt instruction</a>
  AMED_AARCH64_PAGE_HVC, //!< <a href="../target/aarch64/HVC.html">HVC:Hypervisor Call</a>
  AMED_AARCH64_PAGE_IRG, //!< <a href="../target/aarch64/IRG.html">IRG:Insert Random Tag</a>
  AMED_AARCH64_PAGE_ISB, //!< <a href="../target/aarch64/ISB.html">ISB:Instruction Synchronization Barrier</a>
  AMED_AARCH64_PAGE_LDADD, //!< <a href="../target/aarch64/LDADD.html">LDADD, LDADDA, LDADDAL, LDADDL:Atomic add on word or doubleword in memory</a>
  AMED_AARCH64_PAGE_LDADDB, //!< <a href="../target/aarch64/LDADDB.html">LDADDB, LDADDAB, LDADDALB, LDADDLB:Atomic add on byte in memory</a>
  AMED_AARCH64_PAGE_LDADDH, //!< <a href="../target/aarch64/LDADDH.html">LDADDH, LDADDAH, LDADDALH, LDADDLH:Atomic add on halfword in memory</a>
  AMED_AARCH64_PAGE_LDAPR, //!< <a href="../target/aarch64/LDAPR.html">LDAPR:Load-Acquire RCpc Register</a>
  AMED_AARCH64_PAGE_LDAPRB, //!< <a href="../target/aarch64/LDAPRB.html">LDAPRB:Load-Acquire RCpc Register Byte</a>
  AMED_AARCH64_PAGE_LDAPRH, //!< <a href="../target/aarch64/LDAPRH.html">LDAPRH:Load-Acquire RCpc Register Halfword</a>
  AMED_AARCH64_PAGE_LDAPUR_gen, //!< <a href="../target/aarch64/LDAPUR_gen.html">LDAPUR:Load-Acquire RCpc Register (unscaled)</a>
  AMED_AARCH64_PAGE_LDAPURB, //!< <a href="../target/aarch64/LDAPURB.html">LDAPURB:Load-Acquire RCpc Register Byte (unscaled)</a>
  AMED_AARCH64_PAGE_LDAPURH, //!< <a href="../target/aarch64/LDAPURH.html">LDAPURH:Load-Acquire RCpc Register Halfword (unscaled)</a>
  AMED_AARCH64_PAGE_LDAPURSB, //!< <a href="../target/aarch64/LDAPURSB.html">LDAPURSB:Load-Acquire RCpc Register Signed Byte (unscaled)</a>
  AMED_AARCH64_PAGE_LDAPURSH, //!< <a href="../target/aarch64/LDAPURSH.html">LDAPURSH:Load-Acquire RCpc Register Signed Halfword (unscaled)</a>
  AMED_AARCH64_PAGE_LDAPURSW, //!< <a href="../target/aarch64/LDAPURSW.html">LDAPURSW:Load-Acquire RCpc Register Signed Word (unscaled)</a>
  AMED_AARCH64_PAGE_LDAR, //!< <a href="../target/aarch64/LDAR.html">LDAR:Load-Acquire Register</a>
  AMED_AARCH64_PAGE_LDARB, //!< <a href="../target/aarch64/LDARB.html">LDARB:Load-Acquire Register Byte</a>
  AMED_AARCH64_PAGE_LDARH, //!< <a href="../target/aarch64/LDARH.html">LDARH:Load-Acquire Register Halfword</a>
  AMED_AARCH64_PAGE_LDAXP, //!< <a href="../target/aarch64/LDAXP.html">LDAXP:Load-Acquire Exclusive Pair of Registers</a>
  AMED_AARCH64_PAGE_LDAXR, //!< <a href="../target/aarch64/LDAXR.html">LDAXR:Load-Acquire Exclusive Register</a>
  AMED_AARCH64_PAGE_LDAXRB, //!< <a href="../target/aarch64/LDAXRB.html">LDAXRB:Load-Acquire Exclusive Register Byte</a>
  AMED_AARCH64_PAGE_LDAXRH, //!< <a href="../target/aarch64/LDAXRH.html">LDAXRH:Load-Acquire Exclusive Register Halfword</a>
  AMED_AARCH64_PAGE_LDCLR, //!< <a href="../target/aarch64/LDCLR.html">LDCLR, LDCLRA, LDCLRAL, LDCLRL:Atomic bit clear on word or doubleword in memory</a>
  AMED_AARCH64_PAGE_LDCLRB, //!< <a href="../target/aarch64/LDCLRB.html">LDCLRB, LDCLRAB, LDCLRALB, LDCLRLB:Atomic bit clear on byte in memory</a>
  AMED_AARCH64_PAGE_LDCLRH, //!< <a href="../target/aarch64/LDCLRH.html">LDCLRH, LDCLRAH, LDCLRALH, LDCLRLH:Atomic bit clear on halfword in memory</a>
  AMED_AARCH64_PAGE_LDEOR, //!< <a href="../target/aarch64/LDEOR.html">LDEOR, LDEORA, LDEORAL, LDEORL:Atomic exclusive OR on word or doubleword in memory</a>
  AMED_AARCH64_PAGE_LDEORB, //!< <a href="../target/aarch64/LDEORB.html">LDEORB, LDEORAB, LDEORALB, LDEORLB:Atomic exclusive OR on byte in memory</a>
  AMED_AARCH64_PAGE_LDEORH, //!< <a href="../target/aarch64/LDEORH.html">LDEORH, LDEORAH, LDEORALH, LDEORLH:Atomic exclusive OR on halfword in memory</a>
  AMED_AARCH64_PAGE_LDG, //!< <a href="../target/aarch64/LDG.html">LDG:Load Allocation Tag</a>
  AMED_AARCH64_PAGE_LDGM, //!< <a href="../target/aarch64/LDGM.html">LDGM:Load Tag Multiple</a>
  AMED_AARCH64_PAGE_LDLAR, //!< <a href="../target/aarch64/LDLAR.html">LDLAR:Load LOAcquire Register</a>
  AMED_AARCH64_PAGE_LDLARB, //!< <a href="../target/aarch64/LDLARB.html">LDLARB:Load LOAcquire Register Byte</a>
  AMED_AARCH64_PAGE_LDLARH, //!< <a href="../target/aarch64/LDLARH.html">LDLARH:Load LOAcquire Register Halfword</a>
  AMED_AARCH64_PAGE_LDNP_gen, //!< <a href="../target/aarch64/LDNP_gen.html">LDNP:Load Pair of Registers, with non-temporal hint</a>
  AMED_AARCH64_PAGE_LDP_gen, //!< <a href="../target/aarch64/LDP_gen.html">LDP:Load Pair of Registers</a>
  AMED_AARCH64_PAGE_LDPSW, //!< <a href="../target/aarch64/LDPSW.html">LDPSW:Load Pair of Registers Signed Word</a>
  AMED_AARCH64_PAGE_LDR_imm_gen, //!< <a href="../target/aarch64/LDR_imm_gen.html">LDR (immediate):Load Register (immediate)</a>
  AMED_AARCH64_PAGE_LDR_lit_gen, //!< <a href="../target/aarch64/LDR_lit_gen.html">LDR (literal):Load Register (literal)</a>
  AMED_AARCH64_PAGE_LDR_reg_gen, //!< <a href="../target/aarch64/LDR_reg_gen.html">LDR (register):Load Register (register)</a>
  AMED_AARCH64_PAGE_LDRA, //!< <a href="../target/aarch64/LDRA.html">LDRAA, LDRAB:Load Register, with pointer authentication</a>
  AMED_AARCH64_PAGE_LDRB_imm, //!< <a href="../target/aarch64/LDRB_imm.html">LDRB (immediate):Load Register Byte (immediate)</a>
  AMED_AARCH64_PAGE_LDRB_reg, //!< <a href="../target/aarch64/LDRB_reg.html">LDRB (register):Load Register Byte (register)</a>
  AMED_AARCH64_PAGE_LDRH_imm, //!< <a href="../target/aarch64/LDRH_imm.html">LDRH (immediate):Load Register Halfword (immediate)</a>
  AMED_AARCH64_PAGE_LDRH_reg, //!< <a href="../target/aarch64/LDRH_reg.html">LDRH (register):Load Register Halfword (register)</a>
  AMED_AARCH64_PAGE_LDRSB_imm, //!< <a href="../target/aarch64/LDRSB_imm.html">LDRSB (immediate):Load Register Signed Byte (immediate)</a>
  AMED_AARCH64_PAGE_LDRSB_reg, //!< <a href="../target/aarch64/LDRSB_reg.html">LDRSB (register):Load Register Signed Byte (register)</a>
  AMED_AARCH64_PAGE_LDRSH_imm, //!< <a href="../target/aarch64/LDRSH_imm.html">LDRSH (immediate):Load Register Signed Halfword (immediate)</a>
  AMED_AARCH64_PAGE_LDRSH_reg, //!< <a href="../target/aarch64/LDRSH_reg.html">LDRSH (register):Load Register Signed Halfword (register)</a>
  AMED_AARCH64_PAGE_LDRSW_imm, //!< <a href="../target/aarch64/LDRSW_imm.html">LDRSW (immediate):Load Register Signed Word (immediate)</a>
  AMED_AARCH64_PAGE_LDRSW_lit, //!< <a href="../target/aarch64/LDRSW_lit.html">LDRSW (literal):Load Register Signed Word (literal)</a>
  AMED_AARCH64_PAGE_LDRSW_reg, //!< <a href="../target/aarch64/LDRSW_reg.html">LDRSW (register):Load Register Signed Word (register)</a>
  AMED_AARCH64_PAGE_LDSET, //!< <a href="../target/aarch64/LDSET.html">LDSET, LDSETA, LDSETAL, LDSETL:Atomic bit set on word or doubleword in memory</a>
  AMED_AARCH64_PAGE_LDSETB, //!< <a href="../target/aarch64/LDSETB.html">LDSETB, LDSETAB, LDSETALB, LDSETLB:Atomic bit set on byte in memory</a>
  AMED_AARCH64_PAGE_LDSETH, //!< <a href="../target/aarch64/LDSETH.html">LDSETH, LDSETAH, LDSETALH, LDSETLH:Atomic bit set on halfword in memory</a>
  AMED_AARCH64_PAGE_LDSMAX, //!< <a href="../target/aarch64/LDSMAX.html">LDSMAX, LDSMAXA, LDSMAXAL, LDSMAXL:Atomic signed maximum on word or doubleword in memory</a>
  AMED_AARCH64_PAGE_LDSMAXB, //!< <a href="../target/aarch64/LDSMAXB.html">LDSMAXB, LDSMAXAB, LDSMAXALB, LDSMAXLB:Atomic signed maximum on byte in memory</a>
  AMED_AARCH64_PAGE_LDSMAXH, //!< <a href="../target/aarch64/LDSMAXH.html">LDSMAXH, LDSMAXAH, LDSMAXALH, LDSMAXLH:Atomic signed maximum on halfword in memory</a>
  AMED_AARCH64_PAGE_LDSMIN, //!< <a href="../target/aarch64/LDSMIN.html">LDSMIN, LDSMINA, LDSMINAL, LDSMINL:Atomic signed minimum on word or doubleword in memory</a>
  AMED_AARCH64_PAGE_LDSMINB, //!< <a href="../target/aarch64/LDSMINB.html">LDSMINB, LDSMINAB, LDSMINALB, LDSMINLB:Atomic signed minimum on byte in memory</a>
  AMED_AARCH64_PAGE_LDSMINH, //!< <a href="../target/aarch64/LDSMINH.html">LDSMINH, LDSMINAH, LDSMINALH, LDSMINLH:Atomic signed minimum on halfword in memory</a>
  AMED_AARCH64_PAGE_LDTR, //!< <a href="../target/aarch64/LDTR.html">LDTR:Load Register (unprivileged)</a>
  AMED_AARCH64_PAGE_LDTRB, //!< <a href="../target/aarch64/LDTRB.html">LDTRB:Load Register Byte (unprivileged)</a>
  AMED_AARCH64_PAGE_LDTRH, //!< <a href="../target/aarch64/LDTRH.html">LDTRH:Load Register Halfword (unprivileged)</a>
  AMED_AARCH64_PAGE_LDTRSB, //!< <a href="../target/aarch64/LDTRSB.html">LDTRSB:Load Register Signed Byte (unprivileged)</a>
  AMED_AARCH64_PAGE_LDTRSH, //!< <a href="../target/aarch64/LDTRSH.html">LDTRSH:Load Register Signed Halfword (unprivileged)</a>
  AMED_AARCH64_PAGE_LDTRSW, //!< <a href="../target/aarch64/LDTRSW.html">LDTRSW:Load Register Signed Word (unprivileged)</a>
  AMED_AARCH64_PAGE_LDUMAX, //!< <a href="../target/aarch64/LDUMAX.html">LDUMAX, LDUMAXA, LDUMAXAL, LDUMAXL:Atomic unsigned maximum on word or doubleword in memory</a>
  AMED_AARCH64_PAGE_LDUMAXB, //!< <a href="../target/aarch64/LDUMAXB.html">LDUMAXB, LDUMAXAB, LDUMAXALB, LDUMAXLB:Atomic unsigned maximum on byte in memory</a>
  AMED_AARCH64_PAGE_LDUMAXH, //!< <a href="../target/aarch64/LDUMAXH.html">LDUMAXH, LDUMAXAH, LDUMAXALH, LDUMAXLH:Atomic unsigned maximum on halfword in memory</a>
  AMED_AARCH64_PAGE_LDUMIN, //!< <a href="../target/aarch64/LDUMIN.html">LDUMIN, LDUMINA, LDUMINAL, LDUMINL:Atomic unsigned minimum on word or doubleword in memory</a>
  AMED_AARCH64_PAGE_LDUMINB, //!< <a href="../target/aarch64/LDUMINB.html">LDUMINB, LDUMINAB, LDUMINALB, LDUMINLB:Atomic unsigned minimum on byte in memory</a>
  AMED_AARCH64_PAGE_LDUMINH, //!< <a href="../target/aarch64/LDUMINH.html">LDUMINH, LDUMINAH, LDUMINALH, LDUMINLH:Atomic unsigned minimum on halfword in memory</a>
  AMED_AARCH64_PAGE_LDUR_gen, //!< <a href="../target/aarch64/LDUR_gen.html">LDUR:Load Register (unscaled)</a>
  AMED_AARCH64_PAGE_LDURB, //!< <a href="../target/aarch64/LDURB.html">LDURB:Load Register Byte (unscaled)</a>
  AMED_AARCH64_PAGE_LDURH, //!< <a href="../target/aarch64/LDURH.html">LDURH:Load Register Halfword (unscaled)</a>
  AMED_AARCH64_PAGE_LDURSB, //!< <a href="../target/aarch64/LDURSB.html">LDURSB:Load Register Signed Byte (unscaled)</a>
  AMED_AARCH64_PAGE_LDURSH, //!< <a href="../target/aarch64/LDURSH.html">LDURSH:Load Register Signed Halfword (unscaled)</a>
  AMED_AARCH64_PAGE_LDURSW, //!< <a href="../target/aarch64/LDURSW.html">LDURSW:Load Register Signed Word (unscaled)</a>
  AMED_AARCH64_PAGE_LDXP, //!< <a href="../target/aarch64/LDXP.html">LDXP:Load Exclusive Pair of Registers</a>
  AMED_AARCH64_PAGE_LDXR, //!< <a href="../target/aarch64/LDXR.html">LDXR:Load Exclusive Register</a>
  AMED_AARCH64_PAGE_LDXRB, //!< <a href="../target/aarch64/LDXRB.html">LDXRB:Load Exclusive Register Byte</a>
  AMED_AARCH64_PAGE_LDXRH, //!< <a href="../target/aarch64/LDXRH.html">LDXRH:Load Exclusive Register Halfword</a>
  AMED_AARCH64_PAGE_LSLV, //!< <a href="../target/aarch64/LSLV.html">LSLV:Logical Shift Left Variable</a>
  AMED_AARCH64_PAGE_LSRV, //!< <a href="../target/aarch64/LSRV.html">LSRV:Logical Shift Right Variable</a>
  AMED_AARCH64_PAGE_MADD, //!< <a href="../target/aarch64/MADD.html">MADD:Multiply-Add</a>
  AMED_AARCH64_PAGE_MOVK, //!< <a href="../target/aarch64/MOVK.html">MOVK:Move wide with keep</a>
  AMED_AARCH64_PAGE_MOVN, //!< <a href="../target/aarch64/MOVN.html">MOVN:Move wide with NOT</a>
  AMED_AARCH64_PAGE_MOVZ, //!< <a href="../target/aarch64/MOVZ.html">MOVZ:Move wide with zero</a>
  AMED_AARCH64_PAGE_MRS, //!< <a href="../target/aarch64/MRS.html">MRS:Move System Register</a>
  AMED_AARCH64_PAGE_MSR_imm, //!< <a href="../target/aarch64/MSR_imm.html">MSR (immediate):Move immediate value to Special Register</a>
  AMED_AARCH64_PAGE_MSR_reg, //!< <a href="../target/aarch64/MSR_reg.html">MSR (register):Move general-purpose register to System Register</a>
  AMED_AARCH64_PAGE_MSUB, //!< <a href="../target/aarch64/MSUB.html">MSUB:Multiply-Subtract</a>
  AMED_AARCH64_PAGE_NOP, //!< <a href="../target/aarch64/NOP.html">NOP:No Operation</a>
  AMED_AARCH64_PAGE_ORN_log_shift, //!< <a href="../target/aarch64/ORN_log_shift.html">ORN (shifted register):Bitwise OR NOT (shifted register)</a>
  AMED_AARCH64_PAGE_ORR_log_imm, //!< <a href="../target/aarch64/ORR_log_imm.html">ORR (immediate):Bitwise OR (immediate)</a>
  AMED_AARCH64_PAGE_ORR_log_shift, //!< <a href="../target/aarch64/ORR_log_shift.html">ORR (shifted register):Bitwise OR (shifted register)</a>
  AMED_AARCH64_PAGE_PACDA, //!< <a href="../target/aarch64/PACDA.html">PACDA, PACDZA:Pointer Authentication Code for Data address, using key A</a>
  AMED_AARCH64_PAGE_PACDB, //!< <a href="../target/aarch64/PACDB.html">PACDB, PACDZB:Pointer Authentication Code for Data address, using key B</a>
  AMED_AARCH64_PAGE_PACGA, //!< <a href="../target/aarch64/PACGA.html">PACGA:Pointer Authentication Code, using Generic key</a>
  AMED_AARCH64_PAGE_PACIA, //!< <a href="../target/aarch64/PACIA.html">PACIA, PACIA1716, PACIASP, PACIAZ, PACIZA:Pointer Authentication Code for Instruction address, using key A</a>
  AMED_AARCH64_PAGE_PACIB, //!< <a href="../target/aarch64/PACIB.html">PACIB, PACIB1716, PACIBSP, PACIBZ, PACIZB:Pointer Authentication Code for Instruction address, using key B</a>
  AMED_AARCH64_PAGE_PRFM_imm, //!< <a href="../target/aarch64/PRFM_imm.html">PRFM (immediate):Prefetch Memory (immediate)</a>
  AMED_AARCH64_PAGE_PRFM_lit, //!< <a href="../target/aarch64/PRFM_lit.html">PRFM (literal):Prefetch Memory (literal)</a>
  AMED_AARCH64_PAGE_PRFM_reg, //!< <a href="../target/aarch64/PRFM_reg.html">PRFM (register):Prefetch Memory (register)</a>
  AMED_AARCH64_PAGE_PRFUM, //!< <a href="../target/aarch64/PRFUM.html">PRFUM:Prefetch Memory (unscaled offset)</a>
  AMED_AARCH64_PAGE_PSB, //!< <a href="../target/aarch64/PSB.html">PSB CSYNC:Profiling Synchronization Barrier</a>
  AMED_AARCH64_PAGE_PSSBB, //!< <a href="../target/aarch64/PSSBB.html">PSSBB:Physical Speculative Store Bypass Barrier</a>
  AMED_AARCH64_PAGE_RBIT_int, //!< <a href="../target/aarch64/RBIT_int.html">RBIT:Reverse Bits</a>
  AMED_AARCH64_PAGE_RET, //!< <a href="../target/aarch64/RET.html">RET:Return from subroutine</a>
  AMED_AARCH64_PAGE_RETA, //!< <a href="../target/aarch64/RETA.html">RETAA, RETAB:Return from subroutine, with pointer authentication</a>
  AMED_AARCH64_PAGE_REV, //!< <a href="../target/aarch64/REV.html">REV:Reverse Bytes</a>
  AMED_AARCH64_PAGE_REV16_int, //!< <a href="../target/aarch64/REV16_int.html">REV16:Reverse bytes in 16-bit halfwords</a>
  AMED_AARCH64_PAGE_REV32_int, //!< <a href="../target/aarch64/REV32_int.html">REV32:Reverse bytes in 32-bit words</a>
  AMED_AARCH64_PAGE_RMIF, //!< <a href="../target/aarch64/RMIF.html">RMIF:Rotate, Mask Insert Flags</a>
  AMED_AARCH64_PAGE_RORV, //!< <a href="../target/aarch64/RORV.html">RORV:Rotate Right Variable</a>
  AMED_AARCH64_PAGE_SB, //!< <a href="../target/aarch64/SB.html">SB:Speculation Barrier</a>
  AMED_AARCH64_PAGE_SBC, //!< <a href="../target/aarch64/SBC.html">SBC:Subtract with Carry</a>
  AMED_AARCH64_PAGE_SBCS, //!< <a href="../target/aarch64/SBCS.html">SBCS:Subtract with Carry, setting flags</a>
  AMED_AARCH64_PAGE_SBFM, //!< <a href="../target/aarch64/SBFM.html">SBFM:Signed Bitfield Move</a>
  AMED_AARCH64_PAGE_SDIV, //!< <a href="../target/aarch64/SDIV.html">SDIV:Signed Divide</a>
  AMED_AARCH64_PAGE_SETF, //!< <a href="../target/aarch64/SETF.html">SETF8, SETF16:Evaluation of 8 or 16 bit flag values</a>
  AMED_AARCH64_PAGE_SEV, //!< <a href="../target/aarch64/SEV.html">SEV:Send Event</a>
  AMED_AARCH64_PAGE_SEVL, //!< <a href="../target/aarch64/SEVL.html">SEVL:Send Event Local</a>
  AMED_AARCH64_PAGE_SMADDL, //!< <a href="../target/aarch64/SMADDL.html">SMADDL:Signed Multiply-Add Long</a>
  AMED_AARCH64_PAGE_SMC, //!< <a href="../target/aarch64/SMC.html">SMC:Secure Monitor Call</a>
  AMED_AARCH64_PAGE_SMSUBL, //!< <a href="../target/aarch64/SMSUBL.html">SMSUBL:Signed Multiply-Subtract Long</a>
  AMED_AARCH64_PAGE_SMULH, //!< <a href="../target/aarch64/SMULH.html">SMULH:Signed Multiply High</a>
  AMED_AARCH64_PAGE_SSBB, //!< <a href="../target/aarch64/SSBB.html">SSBB:Speculative Store Bypass Barrier</a>
  AMED_AARCH64_PAGE_ST2G, //!< <a href="../target/aarch64/ST2G.html">ST2G:Store Allocation Tags</a>
  AMED_AARCH64_PAGE_STG, //!< <a href="../target/aarch64/STG.html">STG:Store Allocation Tag</a>
  AMED_AARCH64_PAGE_STGM, //!< <a href="../target/aarch64/STGM.html">STGM:Store Tag Multiple</a>
  AMED_AARCH64_PAGE_STGP, //!< <a href="../target/aarch64/STGP.html">STGP:Store Allocation Tag and Pair of registers</a>
  AMED_AARCH64_PAGE_STLLR, //!< <a href="../target/aarch64/STLLR.html">STLLR:Store LORelease Register</a>
  AMED_AARCH64_PAGE_STLLRB, //!< <a href="../target/aarch64/STLLRB.html">STLLRB:Store LORelease Register Byte</a>
  AMED_AARCH64_PAGE_STLLRH, //!< <a href="../target/aarch64/STLLRH.html">STLLRH:Store LORelease Register Halfword</a>
  AMED_AARCH64_PAGE_STLR, //!< <a href="../target/aarch64/STLR.html">STLR:Store-Release Register</a>
  AMED_AARCH64_PAGE_STLRB, //!< <a href="../target/aarch64/STLRB.html">STLRB:Store-Release Register Byte</a>
  AMED_AARCH64_PAGE_STLRH, //!< <a href="../target/aarch64/STLRH.html">STLRH:Store-Release Register Halfword</a>
  AMED_AARCH64_PAGE_STLUR_gen, //!< <a href="../target/aarch64/STLUR_gen.html">STLUR:Store-Release Register (unscaled)</a>
  AMED_AARCH64_PAGE_STLURB, //!< <a href="../target/aarch64/STLURB.html">STLURB:Store-Release Register Byte (unscaled)</a>
  AMED_AARCH64_PAGE_STLURH, //!< <a href="../target/aarch64/STLURH.html">STLURH:Store-Release Register Halfword (unscaled)</a>
  AMED_AARCH64_PAGE_STLXP, //!< <a href="../target/aarch64/STLXP.html">STLXP:Store-Release Exclusive Pair of registers</a>
  AMED_AARCH64_PAGE_STLXR, //!< <a href="../target/aarch64/STLXR.html">STLXR:Store-Release Exclusive Register</a>
  AMED_AARCH64_PAGE_STLXRB, //!< <a href="../target/aarch64/STLXRB.html">STLXRB:Store-Release Exclusive Register Byte</a>
  AMED_AARCH64_PAGE_STLXRH, //!< <a href="../target/aarch64/STLXRH.html">STLXRH:Store-Release Exclusive Register Halfword</a>
  AMED_AARCH64_PAGE_STNP_gen, //!< <a href="../target/aarch64/STNP_gen.html">STNP:Store Pair of Registers, with non-temporal hint</a>
  AMED_AARCH64_PAGE_STP_gen, //!< <a href="../target/aarch64/STP_gen.html">STP:Store Pair of Registers</a>
  AMED_AARCH64_PAGE_STR_imm_gen, //!< <a href="../target/aarch64/STR_imm_gen.html">STR (immediate):Store Register (immediate)</a>
  AMED_AARCH64_PAGE_STR_reg_gen, //!< <a href="../target/aarch64/STR_reg_gen.html">STR (register):Store Register (register)</a>
  AMED_AARCH64_PAGE_STRB_imm, //!< <a href="../target/aarch64/STRB_imm.html">STRB (immediate):Store Register Byte (immediate)</a>
  AMED_AARCH64_PAGE_STRB_reg, //!< <a href="../target/aarch64/STRB_reg.html">STRB (register):Store Register Byte (register)</a>
  AMED_AARCH64_PAGE_STRH_imm, //!< <a href="../target/aarch64/STRH_imm.html">STRH (immediate):Store Register Halfword (immediate)</a>
  AMED_AARCH64_PAGE_STRH_reg, //!< <a href="../target/aarch64/STRH_reg.html">STRH (register):Store Register Halfword (register)</a>
  AMED_AARCH64_PAGE_STTR, //!< <a href="../target/aarch64/STTR.html">STTR:Store Register (unprivileged)</a>
  AMED_AARCH64_PAGE_STTRB, //!< <a href="../target/aarch64/STTRB.html">STTRB:Store Register Byte (unprivileged)</a>
  AMED_AARCH64_PAGE_STTRH, //!< <a href="../target/aarch64/STTRH.html">STTRH:Store Register Halfword (unprivileged)</a>
  AMED_AARCH64_PAGE_STUR_gen, //!< <a href="../target/aarch64/STUR_gen.html">STUR:Store Register (unscaled)</a>
  AMED_AARCH64_PAGE_STURB, //!< <a href="../target/aarch64/STURB.html">STURB:Store Register Byte (unscaled)</a>
  AMED_AARCH64_PAGE_STURH, //!< <a href="../target/aarch64/STURH.html">STURH:Store Register Halfword (unscaled)</a>
  AMED_AARCH64_PAGE_STXP, //!< <a href="../target/aarch64/STXP.html">STXP:Store Exclusive Pair of registers</a>
  AMED_AARCH64_PAGE_STXR, //!< <a href="../target/aarch64/STXR.html">STXR:Store Exclusive Register</a>
  AMED_AARCH64_PAGE_STXRB, //!< <a href="../target/aarch64/STXRB.html">STXRB:Store Exclusive Register Byte</a>
  AMED_AARCH64_PAGE_STXRH, //!< <a href="../target/aarch64/STXRH.html">STXRH:Store Exclusive Register Halfword</a>
  AMED_AARCH64_PAGE_STZ2G, //!< <a href="../target/aarch64/STZ2G.html">STZ2G:Store Allocation Tags, Zeroing</a>
  AMED_AARCH64_PAGE_STZG, //!< <a href="../target/aarch64/STZG.html">STZG:Store Allocation Tag, Zeroing</a>
  AMED_AARCH64_PAGE_STZGM, //!< <a href="../target/aarch64/STZGM.html">STZGM:Store Tag and Zero Multiple</a>
  AMED_AARCH64_PAGE_SUB_addsub_ext, //!< <a href="../target/aarch64/SUB_addsub_ext.html">SUB (extended register):Subtract (extended register)</a>
  AMED_AARCH64_PAGE_SUB_addsub_imm, //!< <a href="../target/aarch64/SUB_addsub_imm.html">SUB (immediate):Subtract (immediate)</a>
  AMED_AARCH64_PAGE_SUB_addsub_shift, //!< <a href="../target/aarch64/SUB_addsub_shift.html">SUB (shifted register):Subtract (shifted register)</a>
  AMED_AARCH64_PAGE_SUBG, //!< <a href="../target/aarch64/SUBG.html">SUBG:Subtract with Tag</a>
  AMED_AARCH64_PAGE_SUBP, //!< <a href="../target/aarch64/SUBP.html">SUBP:Subtract Pointer</a>
  AMED_AARCH64_PAGE_SUBPS, //!< <a href="../target/aarch64/SUBPS.html">SUBPS:Subtract Pointer, setting Flags</a>
  AMED_AARCH64_PAGE_SUBS_addsub_ext, //!< <a href="../target/aarch64/SUBS_addsub_ext.html">SUBS (extended register):Subtract (extended register), setting flags</a>
  AMED_AARCH64_PAGE_SUBS_addsub_imm, //!< <a href="../target/aarch64/SUBS_addsub_imm.html">SUBS (immediate):Subtract (immediate), setting flags</a>
  AMED_AARCH64_PAGE_SUBS_addsub_shift, //!< <a href="../target/aarch64/SUBS_addsub_shift.html">SUBS (shifted register):Subtract (shifted register), setting flags</a>
  AMED_AARCH64_PAGE_SVC, //!< <a href="../target/aarch64/SVC.html">SVC:Supervisor Call</a>
  AMED_AARCH64_PAGE_SWP, //!< <a href="../target/aarch64/SWP.html">SWP, SWPA, SWPAL, SWPL:Swap word or doubleword in memory</a>
  AMED_AARCH64_PAGE_SWPB, //!< <a href="../target/aarch64/SWPB.html">SWPB, SWPAB, SWPALB, SWPLB:Swap byte in memory</a>
  AMED_AARCH64_PAGE_SWPH, //!< <a href="../target/aarch64/SWPH.html">SWPH, SWPAH, SWPALH, SWPLH:Swap halfword in memory</a>
  AMED_AARCH64_PAGE_SYS, //!< <a href="../target/aarch64/SYS.html">SYS:System instruction</a>
  AMED_AARCH64_PAGE_SYSL, //!< <a href="../target/aarch64/SYSL.html">SYSL:System instruction with result</a>
  AMED_AARCH64_PAGE_TBNZ, //!< <a href="../target/aarch64/TBNZ.html">TBNZ:Test bit and Branch if Nonzero</a>
  AMED_AARCH64_PAGE_TBZ, //!< <a href="../target/aarch64/TBZ.html">TBZ:Test bit and Branch if Zero</a>
  AMED_AARCH64_PAGE_TCANCEL, //!< <a href="../target/aarch64/TCANCEL.html">TCANCEL:Cancel current transaction</a>
  AMED_AARCH64_PAGE_TCOMMIT, //!< <a href="../target/aarch64/TCOMMIT.html">TCOMMIT:Commit current transaction</a>
  AMED_AARCH64_PAGE_TSB, //!< <a href="../target/aarch64/TSB.html">TSB CSYNC:Trace Synchronization Barrier</a>
  AMED_AARCH64_PAGE_TSTART, //!< <a href="../target/aarch64/TSTART.html">TSTART:Start transaction</a>
  AMED_AARCH64_PAGE_TTEST, //!< <a href="../target/aarch64/TTEST.html">TTEST:Test transaction state</a>
  AMED_AARCH64_PAGE_UBFM, //!< <a href="../target/aarch64/UBFM.html">UBFM:Unsigned Bitfield Move</a>
  AMED_AARCH64_PAGE_UDF_perm_undef, //!< <a href="../target/aarch64/UDF_perm_undef.html">UDF:Permanently Undefined</a>
  AMED_AARCH64_PAGE_UDIV, //!< <a href="../target/aarch64/UDIV.html">UDIV:Unsigned Divide</a>
  AMED_AARCH64_PAGE_UMADDL, //!< <a href="../target/aarch64/UMADDL.html">UMADDL:Unsigned Multiply-Add Long</a>
  AMED_AARCH64_PAGE_UMSUBL, //!< <a href="../target/aarch64/UMSUBL.html">UMSUBL:Unsigned Multiply-Subtract Long</a>
  AMED_AARCH64_PAGE_UMULH, //!< <a href="../target/aarch64/UMULH.html">UMULH:Unsigned Multiply High</a>
  AMED_AARCH64_PAGE_WFE, //!< <a href="../target/aarch64/WFE.html">WFE:Wait For Event</a>
  AMED_AARCH64_PAGE_WFI, //!< <a href="../target/aarch64/WFI.html">WFI:Wait For Interrupt</a>
  AMED_AARCH64_PAGE_XAFLAG, //!< <a href="../target/aarch64/XAFLAG.html">XAFLAG:Convert floating-point condition flags from external format to Arm format</a>
  AMED_AARCH64_PAGE_XPAC, //!< <a href="../target/aarch64/XPAC.html">XPACD, XPACI, XPACLRI:Strip Pointer Authentication Code</a>
  AMED_AARCH64_PAGE_YIELD, //!< <a href="../target/aarch64/YIELD.html">YIELD:YIELD</a>
  AMED_AARCH64_PAGE_ASR_ASRV, //!< <a href="../target/aarch64/ASR_ASRV.html">ASR (register):Arithmetic Shift Right (register)</a>
  AMED_AARCH64_PAGE_ASR_SBFM, //!< <a href="../target/aarch64/ASR_SBFM.html">ASR (immediate):Arithmetic Shift Right (immediate)</a>
  AMED_AARCH64_PAGE_AT_SYS, //!< <a href="../target/aarch64/AT_SYS.html">AT:Address Translate</a>
  AMED_AARCH64_PAGE_BFC_BFM, //!< <a href="../target/aarch64/BFC_BFM.html">BFC:Bitfield Clear</a>
  AMED_AARCH64_PAGE_BFI_BFM, //!< <a href="../target/aarch64/BFI_BFM.html">BFI:Bitfield Insert</a>
  AMED_AARCH64_PAGE_BFXIL_BFM, //!< <a href="../target/aarch64/BFXIL_BFM.html">BFXIL:Bitfield extract and insert at low end</a>
  AMED_AARCH64_PAGE_CFP_SYS, //!< <a href="../target/aarch64/CFP_SYS.html">CFP:Control Flow Prediction Restriction by Context</a>
  AMED_AARCH64_PAGE_CINC_CSINC, //!< <a href="../target/aarch64/CINC_CSINC.html">CINC:Conditional Increment</a>
  AMED_AARCH64_PAGE_CINV_CSINV, //!< <a href="../target/aarch64/CINV_CSINV.html">CINV:Conditional Invert</a>
  AMED_AARCH64_PAGE_CMN_ADDS_addsub_ext, //!< <a href="../target/aarch64/CMN_ADDS_addsub_ext.html">CMN (extended register):Compare Negative (extended register)</a>
  AMED_AARCH64_PAGE_CMN_ADDS_addsub_imm, //!< <a href="../target/aarch64/CMN_ADDS_addsub_imm.html">CMN (immediate):Compare Negative (immediate)</a>
  AMED_AARCH64_PAGE_CMN_ADDS_addsub_shift, //!< <a href="../target/aarch64/CMN_ADDS_addsub_shift.html">CMN (shifted register):Compare Negative (shifted register)</a>
  AMED_AARCH64_PAGE_CMP_SUBS_addsub_ext, //!< <a href="../target/aarch64/CMP_SUBS_addsub_ext.html">CMP (extended register):Compare (extended register)</a>
  AMED_AARCH64_PAGE_CMP_SUBS_addsub_imm, //!< <a href="../target/aarch64/CMP_SUBS_addsub_imm.html">CMP (immediate):Compare (immediate)</a>
  AMED_AARCH64_PAGE_CMP_SUBS_addsub_shift, //!< <a href="../target/aarch64/CMP_SUBS_addsub_shift.html">CMP (shifted register):Compare (shifted register)</a>
  AMED_AARCH64_PAGE_CMPP_SUBPS, //!< <a href="../target/aarch64/CMPP_SUBPS.html">CMPP:Compare with Tag</a>
  AMED_AARCH64_PAGE_CNEG_CSNEG, //!< <a href="../target/aarch64/CNEG_CSNEG.html">CNEG:Conditional Negate</a>
  AMED_AARCH64_PAGE_CPP_SYS, //!< <a href="../target/aarch64/CPP_SYS.html">CPP:Cache Prefetch Prediction Restriction by Context</a>
  AMED_AARCH64_PAGE_CSET_CSINC, //!< <a href="../target/aarch64/CSET_CSINC.html">CSET:Conditional Set</a>
  AMED_AARCH64_PAGE_CSETM_CSINV, //!< <a href="../target/aarch64/CSETM_CSINV.html">CSETM:Conditional Set Mask</a>
  AMED_AARCH64_PAGE_DC_SYS, //!< <a href="../target/aarch64/DC_SYS.html">DC:Data Cache operation</a>
  AMED_AARCH64_PAGE_DFB_DSB, //!< <a href="../target/aarch64/DFB_DSB.html">DFB:Data Full Barrier</a>
  AMED_AARCH64_PAGE_DVP_SYS, //!< <a href="../target/aarch64/DVP_SYS.html">DVP:Data Value Prediction Restriction by Context</a>
  AMED_AARCH64_PAGE_IC_SYS, //!< <a href="../target/aarch64/IC_SYS.html">IC:Instruction Cache operation</a>
  AMED_AARCH64_PAGE_LSL_LSLV, //!< <a href="../target/aarch64/LSL_LSLV.html">LSL (register):Logical Shift Left (register)</a>
  AMED_AARCH64_PAGE_LSL_UBFM, //!< <a href="../target/aarch64/LSL_UBFM.html">LSL (immediate):Logical Shift Left (immediate)</a>
  AMED_AARCH64_PAGE_LSR_LSRV, //!< <a href="../target/aarch64/LSR_LSRV.html">LSR (register):Logical Shift Right (register)</a>
  AMED_AARCH64_PAGE_LSR_UBFM, //!< <a href="../target/aarch64/LSR_UBFM.html">LSR (immediate):Logical Shift Right (immediate)</a>
  AMED_AARCH64_PAGE_MNEG_MSUB, //!< <a href="../target/aarch64/MNEG_MSUB.html">MNEG:Multiply-Negate</a>
  AMED_AARCH64_PAGE_MOV_ADD_addsub_imm, //!< <a href="../target/aarch64/MOV_ADD_addsub_imm.html">MOV (to/from SP):Move between register and stack pointer</a>
  AMED_AARCH64_PAGE_MOV_MOVN, //!< <a href="../target/aarch64/MOV_MOVN.html">MOV (inverted wide immediate):Move (inverted wide immediate)</a>
  AMED_AARCH64_PAGE_MOV_MOVZ, //!< <a href="../target/aarch64/MOV_MOVZ.html">MOV (wide immediate):Move (wide immediate)</a>
  AMED_AARCH64_PAGE_MOV_ORR_log_imm, //!< <a href="../target/aarch64/MOV_ORR_log_imm.html">MOV (bitmask immediate):Move (bitmask immediate)</a>
  AMED_AARCH64_PAGE_MOV_ORR_log_shift, //!< <a href="../target/aarch64/MOV_ORR_log_shift.html">MOV (register):Move (register)</a>
  AMED_AARCH64_PAGE_MUL_MADD, //!< <a href="../target/aarch64/MUL_MADD.html">MUL:Multiply</a>
  AMED_AARCH64_PAGE_MVN_ORN_log_shift, //!< <a href="../target/aarch64/MVN_ORN_log_shift.html">MVN:Bitwise NOT</a>
  AMED_AARCH64_PAGE_NEG_SUB_addsub_shift, //!< <a href="../target/aarch64/NEG_SUB_addsub_shift.html">NEG (shifted register):Negate (shifted register)</a>
  AMED_AARCH64_PAGE_NEGS_SUBS_addsub_shift, //!< <a href="../target/aarch64/NEGS_SUBS_addsub_shift.html">NEGS:Negate, setting flags</a>
  AMED_AARCH64_PAGE_NGC_SBC, //!< <a href="../target/aarch64/NGC_SBC.html">NGC:Negate with Carry</a>
  AMED_AARCH64_PAGE_NGCS_SBCS, //!< <a href="../target/aarch64/NGCS_SBCS.html">NGCS:Negate with Carry, setting flags</a>
  AMED_AARCH64_PAGE_REV64_REV, //!< <a href="../target/aarch64/REV64_REV.html">REV64:Reverse Bytes</a>
  AMED_AARCH64_PAGE_ROR_EXTR, //!< <a href="../target/aarch64/ROR_EXTR.html">ROR (immediate):Rotate right (immediate)</a>
  AMED_AARCH64_PAGE_ROR_RORV, //!< <a href="../target/aarch64/ROR_RORV.html">ROR (register):Rotate Right (register)</a>
  AMED_AARCH64_PAGE_SBFIZ_SBFM, //!< <a href="../target/aarch64/SBFIZ_SBFM.html">SBFIZ:Signed Bitfield Insert in Zero</a>
  AMED_AARCH64_PAGE_SBFX_SBFM, //!< <a href="../target/aarch64/SBFX_SBFM.html">SBFX:Signed Bitfield Extract</a>
  AMED_AARCH64_PAGE_SMNEGL_SMSUBL, //!< <a href="../target/aarch64/SMNEGL_SMSUBL.html">SMNEGL:Signed Multiply-Negate Long</a>
  AMED_AARCH64_PAGE_SMULL_SMADDL, //!< <a href="../target/aarch64/SMULL_SMADDL.html">SMULL:Signed Multiply Long</a>
  AMED_AARCH64_PAGE_STADD_LDADD, //!< <a href="../target/aarch64/STADD_LDADD.html">STADD, STADDL:Atomic add on word or doubleword in memory, without return</a>
  AMED_AARCH64_PAGE_STADDB_LDADDB, //!< <a href="../target/aarch64/STADDB_LDADDB.html">STADDB, STADDLB:Atomic add on byte in memory, without return</a>
  AMED_AARCH64_PAGE_STADDH_LDADDH, //!< <a href="../target/aarch64/STADDH_LDADDH.html">STADDH, STADDLH:Atomic add on halfword in memory, without return</a>
  AMED_AARCH64_PAGE_STCLR_LDCLR, //!< <a href="../target/aarch64/STCLR_LDCLR.html">STCLR, STCLRL:Atomic bit clear on word or doubleword in memory, without return</a>
  AMED_AARCH64_PAGE_STCLRB_LDCLRB, //!< <a href="../target/aarch64/STCLRB_LDCLRB.html">STCLRB, STCLRLB:Atomic bit clear on byte in memory, without return</a>
  AMED_AARCH64_PAGE_STCLRH_LDCLRH, //!< <a href="../target/aarch64/STCLRH_LDCLRH.html">STCLRH, STCLRLH:Atomic bit clear on halfword in memory, without return</a>
  AMED_AARCH64_PAGE_STEOR_LDEOR, //!< <a href="../target/aarch64/STEOR_LDEOR.html">STEOR, STEORL:Atomic exclusive OR on word or doubleword in memory, without return</a>
  AMED_AARCH64_PAGE_STEORB_LDEORB, //!< <a href="../target/aarch64/STEORB_LDEORB.html">STEORB, STEORLB:Atomic exclusive OR on byte in memory, without return</a>
  AMED_AARCH64_PAGE_STEORH_LDEORH, //!< <a href="../target/aarch64/STEORH_LDEORH.html">STEORH, STEORLH:Atomic exclusive OR on halfword in memory, without return</a>
  AMED_AARCH64_PAGE_STSET_LDSET, //!< <a href="../target/aarch64/STSET_LDSET.html">STSET, STSETL:Atomic bit set on word or doubleword in memory, without return</a>
  AMED_AARCH64_PAGE_STSETB_LDSETB, //!< <a href="../target/aarch64/STSETB_LDSETB.html">STSETB, STSETLB:Atomic bit set on byte in memory, without return</a>
  AMED_AARCH64_PAGE_STSETH_LDSETH, //!< <a href="../target/aarch64/STSETH_LDSETH.html">STSETH, STSETLH:Atomic bit set on halfword in memory, without return</a>
  AMED_AARCH64_PAGE_STSMAX_LDSMAX, //!< <a href="../target/aarch64/STSMAX_LDSMAX.html">STSMAX, STSMAXL:Atomic signed maximum on word or doubleword in memory, without return</a>
  AMED_AARCH64_PAGE_STSMAXB_LDSMAXB, //!< <a href="../target/aarch64/STSMAXB_LDSMAXB.html">STSMAXB, STSMAXLB:Atomic signed maximum on byte in memory, without return</a>
  AMED_AARCH64_PAGE_STSMAXH_LDSMAXH, //!< <a href="../target/aarch64/STSMAXH_LDSMAXH.html">STSMAXH, STSMAXLH:Atomic signed maximum on halfword in memory, without return</a>
  AMED_AARCH64_PAGE_STSMIN_LDSMIN, //!< <a href="../target/aarch64/STSMIN_LDSMIN.html">STSMIN, STSMINL:Atomic signed minimum on word or doubleword in memory, without return</a>
  AMED_AARCH64_PAGE_STSMINB_LDSMINB, //!< <a href="../target/aarch64/STSMINB_LDSMINB.html">STSMINB, STSMINLB:Atomic signed minimum on byte in memory, without return</a>
  AMED_AARCH64_PAGE_STSMINH_LDSMINH, //!< <a href="../target/aarch64/STSMINH_LDSMINH.html">STSMINH, STSMINLH:Atomic signed minimum on halfword in memory, without return</a>
  AMED_AARCH64_PAGE_STUMAX_LDUMAX, //!< <a href="../target/aarch64/STUMAX_LDUMAX.html">STUMAX, STUMAXL:Atomic unsigned maximum on word or doubleword in memory, without return</a>
  AMED_AARCH64_PAGE_STUMAXB_LDUMAXB, //!< <a href="../target/aarch64/STUMAXB_LDUMAXB.html">STUMAXB, STUMAXLB:Atomic unsigned maximum on byte in memory, without return</a>
  AMED_AARCH64_PAGE_STUMAXH_LDUMAXH, //!< <a href="../target/aarch64/STUMAXH_LDUMAXH.html">STUMAXH, STUMAXLH:Atomic unsigned maximum on halfword in memory, without return</a>
  AMED_AARCH64_PAGE_STUMIN_LDUMIN, //!< <a href="../target/aarch64/STUMIN_LDUMIN.html">STUMIN, STUMINL:Atomic unsigned minimum on word or doubleword in memory, without return</a>
  AMED_AARCH64_PAGE_STUMINB_LDUMINB, //!< <a href="../target/aarch64/STUMINB_LDUMINB.html">STUMINB, STUMINLB:Atomic unsigned minimum on byte in memory, without return</a>
  AMED_AARCH64_PAGE_STUMINH_LDUMINH, //!< <a href="../target/aarch64/STUMINH_LDUMINH.html">STUMINH, STUMINLH:Atomic unsigned minimum on halfword in memory, without return</a>
  AMED_AARCH64_PAGE_SXTB_SBFM, //!< <a href="../target/aarch64/SXTB_SBFM.html">SXTB:Signed Extend Byte</a>
  AMED_AARCH64_PAGE_SXTH_SBFM, //!< <a href="../target/aarch64/SXTH_SBFM.html">SXTH:Sign Extend Halfword</a>
  AMED_AARCH64_PAGE_SXTW_SBFM, //!< <a href="../target/aarch64/SXTW_SBFM.html">SXTW:Sign Extend Word</a>
  AMED_AARCH64_PAGE_TLBI_SYS, //!< <a href="../target/aarch64/TLBI_SYS.html">TLBI:TLB Invalidate operation</a>
  AMED_AARCH64_PAGE_TST_ANDS_log_imm, //!< <a href="../target/aarch64/TST_ANDS_log_imm.html">TST (immediate):Test bits (immediate)</a>
  AMED_AARCH64_PAGE_TST_ANDS_log_shift, //!< <a href="../target/aarch64/TST_ANDS_log_shift.html">TST (shifted register):Test (shifted register)</a>
  AMED_AARCH64_PAGE_UBFIZ_UBFM, //!< <a href="../target/aarch64/UBFIZ_UBFM.html">UBFIZ:Unsigned Bitfield Insert in Zero</a>
  AMED_AARCH64_PAGE_UBFX_UBFM, //!< <a href="../target/aarch64/UBFX_UBFM.html">UBFX:Unsigned Bitfield Extract</a>
  AMED_AARCH64_PAGE_UMNEGL_UMSUBL, //!< <a href="../target/aarch64/UMNEGL_UMSUBL.html">UMNEGL:Unsigned Multiply-Negate Long</a>
  AMED_AARCH64_PAGE_UMULL_UMADDL, //!< <a href="../target/aarch64/UMULL_UMADDL.html">UMULL:Unsigned Multiply Long</a>
  AMED_AARCH64_PAGE_UXTB_UBFM, //!< <a href="../target/aarch64/UXTB_UBFM.html">UXTB:Unsigned Extend Byte</a>
  AMED_AARCH64_PAGE_UXTH_UBFM, //!< <a href="../target/aarch64/UXTH_UBFM.html">UXTH:Unsigned Extend Halfword</a>
  AMED_AARCH64_PAGE_ABS_advsimd, //!< <a href="../target/aarch64/ABS_advsimd.html">ABS:Absolute value (vector)</a>
  AMED_AARCH64_PAGE_ADD_advsimd, //!< <a href="../target/aarch64/ADD_advsimd.html">ADD (vector):Add (vector)</a>
  AMED_AARCH64_PAGE_ADDHN_advsimd, //!< <a href="../target/aarch64/ADDHN_advsimd.html">ADDHN, ADDHN2:Add returning High Narrow</a>
  AMED_AARCH64_PAGE_ADDP_advsimd_pair, //!< <a href="../target/aarch64/ADDP_advsimd_pair.html">ADDP (scalar):Add Pair of elements (scalar)</a>
  AMED_AARCH64_PAGE_ADDP_advsimd_vec, //!< <a href="../target/aarch64/ADDP_advsimd_vec.html">ADDP (vector):Add Pairwise (vector)</a>
  AMED_AARCH64_PAGE_ADDV_advsimd, //!< <a href="../target/aarch64/ADDV_advsimd.html">ADDV:Add across Vector</a>
  AMED_AARCH64_PAGE_AESD_advsimd, //!< <a href="../target/aarch64/AESD_advsimd.html">AESD:AES single round decryption</a>
  AMED_AARCH64_PAGE_AESE_advsimd, //!< <a href="../target/aarch64/AESE_advsimd.html">AESE:AES single round encryption</a>
  AMED_AARCH64_PAGE_AESIMC_advsimd, //!< <a href="../target/aarch64/AESIMC_advsimd.html">AESIMC:AES inverse mix columns</a>
  AMED_AARCH64_PAGE_AESMC_advsimd, //!< <a href="../target/aarch64/AESMC_advsimd.html">AESMC:AES mix columns</a>
  AMED_AARCH64_PAGE_AND_advsimd, //!< <a href="../target/aarch64/AND_advsimd.html">AND (vector):Bitwise AND (vector)</a>
  AMED_AARCH64_PAGE_BCAX_advsimd, //!< <a href="../target/aarch64/BCAX_advsimd.html">BCAX:Bit Clear and XOR</a>
  AMED_AARCH64_PAGE_BFCVT_float, //!< <a href="../target/aarch64/BFCVT_float.html">BFCVT:Floating-point convert from single-precision to BFloat16 format (scalar)</a>
  AMED_AARCH64_PAGE_BFCVTN_advsimd, //!< <a href="../target/aarch64/BFCVTN_advsimd.html">BFCVTN, BFCVTN2:Floating-point convert from single-precision to BFloat16 format (vector)</a>
  AMED_AARCH64_PAGE_BFDOT_advsimd_elt, //!< <a href="../target/aarch64/BFDOT_advsimd_elt.html">BFDOT (by element):BFloat16 floating-point dot product (vector, by element)</a>
  AMED_AARCH64_PAGE_BFDOT_advsimd_vec, //!< <a href="../target/aarch64/BFDOT_advsimd_vec.html">BFDOT (vector):BFloat16 floating-point dot product (vector)</a>
  AMED_AARCH64_PAGE_BFMLAL_advsimd_elt, //!< <a href="../target/aarch64/BFMLAL_advsimd_elt.html">BFMLALB, BFMLALT (by element):BFloat16 floating-point widening multiply-add long (by element)</a>
  AMED_AARCH64_PAGE_BFMLAL_advsimd_vec, //!< <a href="../target/aarch64/BFMLAL_advsimd_vec.html">BFMLALB, BFMLALT (vector):BFloat16 floating-point widening multiply-add long (vector)</a>
  AMED_AARCH64_PAGE_BFMMLA_advsimd, //!< <a href="../target/aarch64/BFMMLA_advsimd.html">BFMMLA:BFloat16 floating-point matrix multiply-accumulate into 2x2 matrix</a>
  AMED_AARCH64_PAGE_BIC_advsimd_imm, //!< <a href="../target/aarch64/BIC_advsimd_imm.html">BIC (vector, immediate):Bitwise bit Clear (vector, immediate)</a>
  AMED_AARCH64_PAGE_BIC_advsimd_reg, //!< <a href="../target/aarch64/BIC_advsimd_reg.html">BIC (vector, register):Bitwise bit Clear (vector, register)</a>
  AMED_AARCH64_PAGE_BIF_advsimd, //!< <a href="../target/aarch64/BIF_advsimd.html">BIF:Bitwise Insert if False</a>
  AMED_AARCH64_PAGE_BIT_advsimd, //!< <a href="../target/aarch64/BIT_advsimd.html">BIT:Bitwise Insert if True</a>
  AMED_AARCH64_PAGE_BSL_advsimd, //!< <a href="../target/aarch64/BSL_advsimd.html">BSL:Bitwise Select</a>
  AMED_AARCH64_PAGE_CLS_advsimd, //!< <a href="../target/aarch64/CLS_advsimd.html">CLS (vector):Count Leading Sign bits (vector)</a>
  AMED_AARCH64_PAGE_CLZ_advsimd, //!< <a href="../target/aarch64/CLZ_advsimd.html">CLZ (vector):Count Leading Zero bits (vector)</a>
  AMED_AARCH64_PAGE_CMEQ_advsimd_reg, //!< <a href="../target/aarch64/CMEQ_advsimd_reg.html">CMEQ (register):Compare bitwise Equal (vector)</a>
  AMED_AARCH64_PAGE_CMEQ_advsimd_zero, //!< <a href="../target/aarch64/CMEQ_advsimd_zero.html">CMEQ (zero):Compare bitwise Equal to zero (vector)</a>
  AMED_AARCH64_PAGE_CMGE_advsimd_reg, //!< <a href="../target/aarch64/CMGE_advsimd_reg.html">CMGE (register):Compare signed Greater than or Equal (vector)</a>
  AMED_AARCH64_PAGE_CMGE_advsimd_zero, //!< <a href="../target/aarch64/CMGE_advsimd_zero.html">CMGE (zero):Compare signed Greater than or Equal to zero (vector)</a>
  AMED_AARCH64_PAGE_CMGT_advsimd_reg, //!< <a href="../target/aarch64/CMGT_advsimd_reg.html">CMGT (register):Compare signed Greater than (vector)</a>
  AMED_AARCH64_PAGE_CMGT_advsimd_zero, //!< <a href="../target/aarch64/CMGT_advsimd_zero.html">CMGT (zero):Compare signed Greater than zero (vector)</a>
  AMED_AARCH64_PAGE_CMHI_advsimd, //!< <a href="../target/aarch64/CMHI_advsimd.html">CMHI (register):Compare unsigned Higher (vector)</a>
  AMED_AARCH64_PAGE_CMHS_advsimd, //!< <a href="../target/aarch64/CMHS_advsimd.html">CMHS (register):Compare unsigned Higher or Same (vector)</a>
  AMED_AARCH64_PAGE_CMLE_advsimd, //!< <a href="../target/aarch64/CMLE_advsimd.html">CMLE (zero):Compare signed Less than or Equal to zero (vector)</a>
  AMED_AARCH64_PAGE_CMLT_advsimd, //!< <a href="../target/aarch64/CMLT_advsimd.html">CMLT (zero):Compare signed Less than zero (vector)</a>
  AMED_AARCH64_PAGE_CMTST_advsimd, //!< <a href="../target/aarch64/CMTST_advsimd.html">CMTST:Compare bitwise Test bits nonzero (vector)</a>
  AMED_AARCH64_PAGE_CNT_advsimd, //!< <a href="../target/aarch64/CNT_advsimd.html">CNT:Population Count per byte</a>
  AMED_AARCH64_PAGE_DUP_advsimd_elt, //!< <a href="../target/aarch64/DUP_advsimd_elt.html">DUP (element):Duplicate vector element to vector or scalar</a>
  AMED_AARCH64_PAGE_DUP_advsimd_gen, //!< <a href="../target/aarch64/DUP_advsimd_gen.html">DUP (general):Duplicate general-purpose register to vector</a>
  AMED_AARCH64_PAGE_EOR3_advsimd, //!< <a href="../target/aarch64/EOR3_advsimd.html">EOR3:Three-way Exclusive OR</a>
  AMED_AARCH64_PAGE_EOR_advsimd, //!< <a href="../target/aarch64/EOR_advsimd.html">EOR (vector):Bitwise Exclusive OR (vector)</a>
  AMED_AARCH64_PAGE_EXT_advsimd, //!< <a href="../target/aarch64/EXT_advsimd.html">EXT:Extract vector from pair of vectors</a>
  AMED_AARCH64_PAGE_FABD_advsimd, //!< <a href="../target/aarch64/FABD_advsimd.html">FABD:Floating-point Absolute Difference (vector)</a>
  AMED_AARCH64_PAGE_FABS_advsimd, //!< <a href="../target/aarch64/FABS_advsimd.html">FABS (vector):Floating-point Absolute value (vector)</a>
  AMED_AARCH64_PAGE_FABS_float, //!< <a href="../target/aarch64/FABS_float.html">FABS (scalar):Floating-point Absolute value (scalar)</a>
  AMED_AARCH64_PAGE_FACGE_advsimd, //!< <a href="../target/aarch64/FACGE_advsimd.html">FACGE:Floating-point Absolute Compare Greater than or Equal (vector)</a>
  AMED_AARCH64_PAGE_FACGT_advsimd, //!< <a href="../target/aarch64/FACGT_advsimd.html">FACGT:Floating-point Absolute Compare Greater than (vector)</a>
  AMED_AARCH64_PAGE_FADD_advsimd, //!< <a href="../target/aarch64/FADD_advsimd.html">FADD (vector):Floating-point Add (vector)</a>
  AMED_AARCH64_PAGE_FADD_float, //!< <a href="../target/aarch64/FADD_float.html">FADD (scalar):Floating-point Add (scalar)</a>
  AMED_AARCH64_PAGE_FADDP_advsimd_pair, //!< <a href="../target/aarch64/FADDP_advsimd_pair.html">FADDP (scalar):Floating-point Add Pair of elements (scalar)</a>
  AMED_AARCH64_PAGE_FADDP_advsimd_vec, //!< <a href="../target/aarch64/FADDP_advsimd_vec.html">FADDP (vector):Floating-point Add Pairwise (vector)</a>
  AMED_AARCH64_PAGE_FCADD_advsimd_vec, //!< <a href="../target/aarch64/FCADD_advsimd_vec.html">FCADD:Floating-point Complex Add</a>
  AMED_AARCH64_PAGE_FCCMP_float, //!< <a href="../target/aarch64/FCCMP_float.html">FCCMP:Floating-point Conditional quiet Compare (scalar)</a>
  AMED_AARCH64_PAGE_FCCMPE_float, //!< <a href="../target/aarch64/FCCMPE_float.html">FCCMPE:Floating-point Conditional signaling Compare (scalar)</a>
  AMED_AARCH64_PAGE_FCMEQ_advsimd_reg, //!< <a href="../target/aarch64/FCMEQ_advsimd_reg.html">FCMEQ (register):Floating-point Compare Equal (vector)</a>
  AMED_AARCH64_PAGE_FCMEQ_advsimd_zero, //!< <a href="../target/aarch64/FCMEQ_advsimd_zero.html">FCMEQ (zero):Floating-point Compare Equal to zero (vector)</a>
  AMED_AARCH64_PAGE_FCMGE_advsimd_reg, //!< <a href="../target/aarch64/FCMGE_advsimd_reg.html">FCMGE (register):Floating-point Compare Greater than or Equal (vector)</a>
  AMED_AARCH64_PAGE_FCMGE_advsimd_zero, //!< <a href="../target/aarch64/FCMGE_advsimd_zero.html">FCMGE (zero):Floating-point Compare Greater than or Equal to zero (vector)</a>
  AMED_AARCH64_PAGE_FCMGT_advsimd_reg, //!< <a href="../target/aarch64/FCMGT_advsimd_reg.html">FCMGT (register):Floating-point Compare Greater than (vector)</a>
  AMED_AARCH64_PAGE_FCMGT_advsimd_zero, //!< <a href="../target/aarch64/FCMGT_advsimd_zero.html">FCMGT (zero):Floating-point Compare Greater than zero (vector)</a>
  AMED_AARCH64_PAGE_FCMLA_advsimd_elt, //!< <a href="../target/aarch64/FCMLA_advsimd_elt.html">FCMLA (by element):Floating-point Complex Multiply Accumulate (by element)</a>
  AMED_AARCH64_PAGE_FCMLA_advsimd_vec, //!< <a href="../target/aarch64/FCMLA_advsimd_vec.html">FCMLA:Floating-point Complex Multiply Accumulate</a>
  AMED_AARCH64_PAGE_FCMLE_advsimd, //!< <a href="../target/aarch64/FCMLE_advsimd.html">FCMLE (zero):Floating-point Compare Less than or Equal to zero (vector)</a>
  AMED_AARCH64_PAGE_FCMLT_advsimd, //!< <a href="../target/aarch64/FCMLT_advsimd.html">FCMLT (zero):Floating-point Compare Less than zero (vector)</a>
  AMED_AARCH64_PAGE_FCMP_float, //!< <a href="../target/aarch64/FCMP_float.html">FCMP:Floating-point quiet Compare (scalar)</a>
  AMED_AARCH64_PAGE_FCMPE_float, //!< <a href="../target/aarch64/FCMPE_float.html">FCMPE:Floating-point signaling Compare (scalar)</a>
  AMED_AARCH64_PAGE_FCSEL_float, //!< <a href="../target/aarch64/FCSEL_float.html">FCSEL:Floating-point Conditional Select (scalar)</a>
  AMED_AARCH64_PAGE_FCVT_float, //!< <a href="../target/aarch64/FCVT_float.html">FCVT:Floating-point Convert precision (scalar)</a>
  AMED_AARCH64_PAGE_FCVTAS_advsimd, //!< <a href="../target/aarch64/FCVTAS_advsimd.html">FCVTAS (vector):Floating-point Convert to Signed integer, rounding to nearest with ties to Away (vector)</a>
  AMED_AARCH64_PAGE_FCVTAS_float, //!< <a href="../target/aarch64/FCVTAS_float.html">FCVTAS (scalar):Floating-point Convert to Signed integer, rounding to nearest with ties to Away (scalar)</a>
  AMED_AARCH64_PAGE_FCVTAU_advsimd, //!< <a href="../target/aarch64/FCVTAU_advsimd.html">FCVTAU (vector):Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (vector)</a>
  AMED_AARCH64_PAGE_FCVTAU_float, //!< <a href="../target/aarch64/FCVTAU_float.html">FCVTAU (scalar):Floating-point Convert to Unsigned integer, rounding to nearest with ties to Away (scalar)</a>
  AMED_AARCH64_PAGE_FCVTL_advsimd, //!< <a href="../target/aarch64/FCVTL_advsimd.html">FCVTL, FCVTL2:Floating-point Convert to higher precision Long (vector)</a>
  AMED_AARCH64_PAGE_FCVTMS_advsimd, //!< <a href="../target/aarch64/FCVTMS_advsimd.html">FCVTMS (vector):Floating-point Convert to Signed integer, rounding toward Minus infinity (vector)</a>
  AMED_AARCH64_PAGE_FCVTMS_float, //!< <a href="../target/aarch64/FCVTMS_float.html">FCVTMS (scalar):Floating-point Convert to Signed integer, rounding toward Minus infinity (scalar)</a>
  AMED_AARCH64_PAGE_FCVTMU_advsimd, //!< <a href="../target/aarch64/FCVTMU_advsimd.html">FCVTMU (vector):Floating-point Convert to Unsigned integer, rounding toward Minus infinity (vector)</a>
  AMED_AARCH64_PAGE_FCVTMU_float, //!< <a href="../target/aarch64/FCVTMU_float.html">FCVTMU (scalar):Floating-point Convert to Unsigned integer, rounding toward Minus infinity (scalar)</a>
  AMED_AARCH64_PAGE_FCVTN_advsimd, //!< <a href="../target/aarch64/FCVTN_advsimd.html">FCVTN, FCVTN2:Floating-point Convert to lower precision Narrow (vector)</a>
  AMED_AARCH64_PAGE_FCVTNS_advsimd, //!< <a href="../target/aarch64/FCVTNS_advsimd.html">FCVTNS (vector):Floating-point Convert to Signed integer, rounding to nearest with ties to even (vector)</a>
  AMED_AARCH64_PAGE_FCVTNS_float, //!< <a href="../target/aarch64/FCVTNS_float.html">FCVTNS (scalar):Floating-point Convert to Signed integer, rounding to nearest with ties to even (scalar)</a>
  AMED_AARCH64_PAGE_FCVTNU_advsimd, //!< <a href="../target/aarch64/FCVTNU_advsimd.html">FCVTNU (vector):Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (vector)</a>
  AMED_AARCH64_PAGE_FCVTNU_float, //!< <a href="../target/aarch64/FCVTNU_float.html">FCVTNU (scalar):Floating-point Convert to Unsigned integer, rounding to nearest with ties to even (scalar)</a>
  AMED_AARCH64_PAGE_FCVTPS_advsimd, //!< <a href="../target/aarch64/FCVTPS_advsimd.html">FCVTPS (vector):Floating-point Convert to Signed integer, rounding toward Plus infinity (vector)</a>
  AMED_AARCH64_PAGE_FCVTPS_float, //!< <a href="../target/aarch64/FCVTPS_float.html">FCVTPS (scalar):Floating-point Convert to Signed integer, rounding toward Plus infinity (scalar)</a>
  AMED_AARCH64_PAGE_FCVTPU_advsimd, //!< <a href="../target/aarch64/FCVTPU_advsimd.html">FCVTPU (vector):Floating-point Convert to Unsigned integer, rounding toward Plus infinity (vector)</a>
  AMED_AARCH64_PAGE_FCVTPU_float, //!< <a href="../target/aarch64/FCVTPU_float.html">FCVTPU (scalar):Floating-point Convert to Unsigned integer, rounding toward Plus infinity (scalar)</a>
  AMED_AARCH64_PAGE_FCVTXN_advsimd, //!< <a href="../target/aarch64/FCVTXN_advsimd.html">FCVTXN, FCVTXN2:Floating-point Convert to lower precision Narrow, rounding to odd (vector)</a>
  AMED_AARCH64_PAGE_FCVTZS_advsimd_fix, //!< <a href="../target/aarch64/FCVTZS_advsimd_fix.html">FCVTZS (vector, fixed-point):Floating-point Convert to Signed fixed-point, rounding toward Zero (vector)</a>
  AMED_AARCH64_PAGE_FCVTZS_advsimd_int, //!< <a href="../target/aarch64/FCVTZS_advsimd_int.html">FCVTZS (vector, integer):Floating-point Convert to Signed integer, rounding toward Zero (vector)</a>
  AMED_AARCH64_PAGE_FCVTZS_float_fix, //!< <a href="../target/aarch64/FCVTZS_float_fix.html">FCVTZS (scalar, fixed-point):Floating-point Convert to Signed fixed-point, rounding toward Zero (scalar)</a>
  AMED_AARCH64_PAGE_FCVTZS_float_int, //!< <a href="../target/aarch64/FCVTZS_float_int.html">FCVTZS (scalar, integer):Floating-point Convert to Signed integer, rounding toward Zero (scalar)</a>
  AMED_AARCH64_PAGE_FCVTZU_advsimd_fix, //!< <a href="../target/aarch64/FCVTZU_advsimd_fix.html">FCVTZU (vector, fixed-point):Floating-point Convert to Unsigned fixed-point, rounding toward Zero (vector)</a>
  AMED_AARCH64_PAGE_FCVTZU_advsimd_int, //!< <a href="../target/aarch64/FCVTZU_advsimd_int.html">FCVTZU (vector, integer):Floating-point Convert to Unsigned integer, rounding toward Zero (vector)</a>
  AMED_AARCH64_PAGE_FCVTZU_float_fix, //!< <a href="../target/aarch64/FCVTZU_float_fix.html">FCVTZU (scalar, fixed-point):Floating-point Convert to Unsigned fixed-point, rounding toward Zero (scalar)</a>
  AMED_AARCH64_PAGE_FCVTZU_float_int, //!< <a href="../target/aarch64/FCVTZU_float_int.html">FCVTZU (scalar, integer):Floating-point Convert to Unsigned integer, rounding toward Zero (scalar)</a>
  AMED_AARCH64_PAGE_FDIV_advsimd, //!< <a href="../target/aarch64/FDIV_advsimd.html">FDIV (vector):Floating-point Divide (vector)</a>
  AMED_AARCH64_PAGE_FDIV_float, //!< <a href="../target/aarch64/FDIV_float.html">FDIV (scalar):Floating-point Divide (scalar)</a>
  AMED_AARCH64_PAGE_FJCVTZS, //!< <a href="../target/aarch64/FJCVTZS.html">FJCVTZS:Floating-point Javascript Convert to Signed fixed-point, rounding toward Zero</a>
  AMED_AARCH64_PAGE_FMADD_float, //!< <a href="../target/aarch64/FMADD_float.html">FMADD:Floating-point fused Multiply-Add (scalar)</a>
  AMED_AARCH64_PAGE_FMAX_advsimd, //!< <a href="../target/aarch64/FMAX_advsimd.html">FMAX (vector):Floating-point Maximum (vector)</a>
  AMED_AARCH64_PAGE_FMAX_float, //!< <a href="../target/aarch64/FMAX_float.html">FMAX (scalar):Floating-point Maximum (scalar)</a>
  AMED_AARCH64_PAGE_FMAXNM_advsimd, //!< <a href="../target/aarch64/FMAXNM_advsimd.html">FMAXNM (vector):Floating-point Maximum Number (vector)</a>
  AMED_AARCH64_PAGE_FMAXNM_float, //!< <a href="../target/aarch64/FMAXNM_float.html">FMAXNM (scalar):Floating-point Maximum Number (scalar)</a>
  AMED_AARCH64_PAGE_FMAXNMP_advsimd_pair, //!< <a href="../target/aarch64/FMAXNMP_advsimd_pair.html">FMAXNMP (scalar):Floating-point Maximum Number of Pair of elements (scalar)</a>
  AMED_AARCH64_PAGE_FMAXNMP_advsimd_vec, //!< <a href="../target/aarch64/FMAXNMP_advsimd_vec.html">FMAXNMP (vector):Floating-point Maximum Number Pairwise (vector)</a>
  AMED_AARCH64_PAGE_FMAXNMV_advsimd, //!< <a href="../target/aarch64/FMAXNMV_advsimd.html">FMAXNMV:Floating-point Maximum Number across Vector</a>
  AMED_AARCH64_PAGE_FMAXP_advsimd_pair, //!< <a href="../target/aarch64/FMAXP_advsimd_pair.html">FMAXP (scalar):Floating-point Maximum of Pair of elements (scalar)</a>
  AMED_AARCH64_PAGE_FMAXP_advsimd_vec, //!< <a href="../target/aarch64/FMAXP_advsimd_vec.html">FMAXP (vector):Floating-point Maximum Pairwise (vector)</a>
  AMED_AARCH64_PAGE_FMAXV_advsimd, //!< <a href="../target/aarch64/FMAXV_advsimd.html">FMAXV:Floating-point Maximum across Vector</a>
  AMED_AARCH64_PAGE_FMIN_advsimd, //!< <a href="../target/aarch64/FMIN_advsimd.html">FMIN (vector):Floating-point minimum (vector)</a>
  AMED_AARCH64_PAGE_FMIN_float, //!< <a href="../target/aarch64/FMIN_float.html">FMIN (scalar):Floating-point Minimum (scalar)</a>
  AMED_AARCH64_PAGE_FMINNM_advsimd, //!< <a href="../target/aarch64/FMINNM_advsimd.html">FMINNM (vector):Floating-point Minimum Number (vector)</a>
  AMED_AARCH64_PAGE_FMINNM_float, //!< <a href="../target/aarch64/FMINNM_float.html">FMINNM (scalar):Floating-point Minimum Number (scalar)</a>
  AMED_AARCH64_PAGE_FMINNMP_advsimd_pair, //!< <a href="../target/aarch64/FMINNMP_advsimd_pair.html">FMINNMP (scalar):Floating-point Minimum Number of Pair of elements (scalar)</a>
  AMED_AARCH64_PAGE_FMINNMP_advsimd_vec, //!< <a href="../target/aarch64/FMINNMP_advsimd_vec.html">FMINNMP (vector):Floating-point Minimum Number Pairwise (vector)</a>
  AMED_AARCH64_PAGE_FMINNMV_advsimd, //!< <a href="../target/aarch64/FMINNMV_advsimd.html">FMINNMV:Floating-point Minimum Number across Vector</a>
  AMED_AARCH64_PAGE_FMINP_advsimd_pair, //!< <a href="../target/aarch64/FMINP_advsimd_pair.html">FMINP (scalar):Floating-point Minimum of Pair of elements (scalar)</a>
  AMED_AARCH64_PAGE_FMINP_advsimd_vec, //!< <a href="../target/aarch64/FMINP_advsimd_vec.html">FMINP (vector):Floating-point Minimum Pairwise (vector)</a>
  AMED_AARCH64_PAGE_FMINV_advsimd, //!< <a href="../target/aarch64/FMINV_advsimd.html">FMINV:Floating-point Minimum across Vector</a>
  AMED_AARCH64_PAGE_FMLA_advsimd_elt, //!< <a href="../target/aarch64/FMLA_advsimd_elt.html">FMLA (by element):Floating-point fused Multiply-Add to accumulator (by element)</a>
  AMED_AARCH64_PAGE_FMLA_advsimd_vec, //!< <a href="../target/aarch64/FMLA_advsimd_vec.html">FMLA (vector):Floating-point fused Multiply-Add to accumulator (vector)</a>
  AMED_AARCH64_PAGE_FMLAL_advsimd_elt, //!< <a href="../target/aarch64/FMLAL_advsimd_elt.html">FMLAL, FMLAL2 (by element):Floating-point fused Multiply-Add Long to accumulator (by element)</a>
  AMED_AARCH64_PAGE_FMLAL_advsimd_vec, //!< <a href="../target/aarch64/FMLAL_advsimd_vec.html">FMLAL, FMLAL2 (vector):Floating-point fused Multiply-Add Long to accumulator (vector)</a>
  AMED_AARCH64_PAGE_FMLS_advsimd_elt, //!< <a href="../target/aarch64/FMLS_advsimd_elt.html">FMLS (by element):Floating-point fused Multiply-Subtract from accumulator (by element)</a>
  AMED_AARCH64_PAGE_FMLS_advsimd_vec, //!< <a href="../target/aarch64/FMLS_advsimd_vec.html">FMLS (vector):Floating-point fused Multiply-Subtract from accumulator (vector)</a>
  AMED_AARCH64_PAGE_FMLSL_advsimd_elt, //!< <a href="../target/aarch64/FMLSL_advsimd_elt.html">FMLSL, FMLSL2 (by element):Floating-point fused Multiply-Subtract Long from accumulator (by element)</a>
  AMED_AARCH64_PAGE_FMLSL_advsimd_vec, //!< <a href="../target/aarch64/FMLSL_advsimd_vec.html">FMLSL, FMLSL2 (vector):Floating-point fused Multiply-Subtract Long from accumulator (vector)</a>
  AMED_AARCH64_PAGE_FMOV_advsimd, //!< <a href="../target/aarch64/FMOV_advsimd.html">FMOV (vector, immediate):Floating-point move immediate (vector)</a>
  AMED_AARCH64_PAGE_FMOV_float, //!< <a href="../target/aarch64/FMOV_float.html">FMOV (register):Floating-point Move register without conversion</a>
  AMED_AARCH64_PAGE_FMOV_float_gen, //!< <a href="../target/aarch64/FMOV_float_gen.html">FMOV (general):Floating-point Move to or from general-purpose register without conversion</a>
  AMED_AARCH64_PAGE_FMOV_float_imm, //!< <a href="../target/aarch64/FMOV_float_imm.html">FMOV (scalar, immediate):Floating-point move immediate (scalar)</a>
  AMED_AARCH64_PAGE_FMSUB_float, //!< <a href="../target/aarch64/FMSUB_float.html">FMSUB:Floating-point Fused Multiply-Subtract (scalar)</a>
  AMED_AARCH64_PAGE_FMUL_advsimd_elt, //!< <a href="../target/aarch64/FMUL_advsimd_elt.html">FMUL (by element):Floating-point Multiply (by element)</a>
  AMED_AARCH64_PAGE_FMUL_advsimd_vec, //!< <a href="../target/aarch64/FMUL_advsimd_vec.html">FMUL (vector):Floating-point Multiply (vector)</a>
  AMED_AARCH64_PAGE_FMUL_float, //!< <a href="../target/aarch64/FMUL_float.html">FMUL (scalar):Floating-point Multiply (scalar)</a>
  AMED_AARCH64_PAGE_FMULX_advsimd_elt, //!< <a href="../target/aarch64/FMULX_advsimd_elt.html">FMULX (by element):Floating-point Multiply extended (by element)</a>
  AMED_AARCH64_PAGE_FMULX_advsimd_vec, //!< <a href="../target/aarch64/FMULX_advsimd_vec.html">FMULX:Floating-point Multiply extended</a>
  AMED_AARCH64_PAGE_FNEG_advsimd, //!< <a href="../target/aarch64/FNEG_advsimd.html">FNEG (vector):Floating-point Negate (vector)</a>
  AMED_AARCH64_PAGE_FNEG_float, //!< <a href="../target/aarch64/FNEG_float.html">FNEG (scalar):Floating-point Negate (scalar)</a>
  AMED_AARCH64_PAGE_FNMADD_float, //!< <a href="../target/aarch64/FNMADD_float.html">FNMADD:Floating-point Negated fused Multiply-Add (scalar)</a>
  AMED_AARCH64_PAGE_FNMSUB_float, //!< <a href="../target/aarch64/FNMSUB_float.html">FNMSUB:Floating-point Negated fused Multiply-Subtract (scalar)</a>
  AMED_AARCH64_PAGE_FNMUL_float, //!< <a href="../target/aarch64/FNMUL_float.html">FNMUL (scalar):Floating-point Multiply-Negate (scalar)</a>
  AMED_AARCH64_PAGE_FRECPE_advsimd, //!< <a href="../target/aarch64/FRECPE_advsimd.html">FRECPE:Floating-point Reciprocal Estimate</a>
  AMED_AARCH64_PAGE_FRECPS_advsimd, //!< <a href="../target/aarch64/FRECPS_advsimd.html">FRECPS:Floating-point Reciprocal Step</a>
  AMED_AARCH64_PAGE_FRECPX_advsimd, //!< <a href="../target/aarch64/FRECPX_advsimd.html">FRECPX:Floating-point Reciprocal exponent (scalar)</a>
  AMED_AARCH64_PAGE_FRINT32X_advsimd, //!< <a href="../target/aarch64/FRINT32X_advsimd.html">FRINT32X (vector):Floating-point Round to 32-bit Integer, using current rounding mode (vector)</a>
  AMED_AARCH64_PAGE_FRINT32X_float, //!< <a href="../target/aarch64/FRINT32X_float.html">FRINT32X (scalar):Floating-point Round to 32-bit Integer, using current rounding mode (scalar)</a>
  AMED_AARCH64_PAGE_FRINT32Z_advsimd, //!< <a href="../target/aarch64/FRINT32Z_advsimd.html">FRINT32Z (vector):Floating-point Round to 32-bit Integer toward Zero (vector)</a>
  AMED_AARCH64_PAGE_FRINT32Z_float, //!< <a href="../target/aarch64/FRINT32Z_float.html">FRINT32Z (scalar):Floating-point Round to 32-bit Integer toward Zero (scalar)</a>
  AMED_AARCH64_PAGE_FRINT64X_advsimd, //!< <a href="../target/aarch64/FRINT64X_advsimd.html">FRINT64X (vector):Floating-point Round to 64-bit Integer, using current rounding mode (vector)</a>
  AMED_AARCH64_PAGE_FRINT64X_float, //!< <a href="../target/aarch64/FRINT64X_float.html">FRINT64X (scalar):Floating-point Round to 64-bit Integer, using current rounding mode (scalar)</a>
  AMED_AARCH64_PAGE_FRINT64Z_advsimd, //!< <a href="../target/aarch64/FRINT64Z_advsimd.html">FRINT64Z (vector):Floating-point Round to 64-bit Integer toward Zero (vector)</a>
  AMED_AARCH64_PAGE_FRINT64Z_float, //!< <a href="../target/aarch64/FRINT64Z_float.html">FRINT64Z (scalar):Floating-point Round to 64-bit Integer toward Zero (scalar)</a>
  AMED_AARCH64_PAGE_FRINTA_advsimd, //!< <a href="../target/aarch64/FRINTA_advsimd.html">FRINTA (vector):Floating-point Round to Integral, to nearest with ties to Away (vector)</a>
  AMED_AARCH64_PAGE_FRINTA_float, //!< <a href="../target/aarch64/FRINTA_float.html">FRINTA (scalar):Floating-point Round to Integral, to nearest with ties to Away (scalar)</a>
  AMED_AARCH64_PAGE_FRINTI_advsimd, //!< <a href="../target/aarch64/FRINTI_advsimd.html">FRINTI (vector):Floating-point Round to Integral, using current rounding mode (vector)</a>
  AMED_AARCH64_PAGE_FRINTI_float, //!< <a href="../target/aarch64/FRINTI_float.html">FRINTI (scalar):Floating-point Round to Integral, using current rounding mode (scalar)</a>
  AMED_AARCH64_PAGE_FRINTM_advsimd, //!< <a href="../target/aarch64/FRINTM_advsimd.html">FRINTM (vector):Floating-point Round to Integral, toward Minus infinity (vector)</a>
  AMED_AARCH64_PAGE_FRINTM_float, //!< <a href="../target/aarch64/FRINTM_float.html">FRINTM (scalar):Floating-point Round to Integral, toward Minus infinity (scalar)</a>
  AMED_AARCH64_PAGE_FRINTN_advsimd, //!< <a href="../target/aarch64/FRINTN_advsimd.html">FRINTN (vector):Floating-point Round to Integral, to nearest with ties to even (vector)</a>
  AMED_AARCH64_PAGE_FRINTN_float, //!< <a href="../target/aarch64/FRINTN_float.html">FRINTN (scalar):Floating-point Round to Integral, to nearest with ties to even (scalar)</a>
  AMED_AARCH64_PAGE_FRINTP_advsimd, //!< <a href="../target/aarch64/FRINTP_advsimd.html">FRINTP (vector):Floating-point Round to Integral, toward Plus infinity (vector)</a>
  AMED_AARCH64_PAGE_FRINTP_float, //!< <a href="../target/aarch64/FRINTP_float.html">FRINTP (scalar):Floating-point Round to Integral, toward Plus infinity (scalar)</a>
  AMED_AARCH64_PAGE_FRINTX_advsimd, //!< <a href="../target/aarch64/FRINTX_advsimd.html">FRINTX (vector):Floating-point Round to Integral exact, using current rounding mode (vector)</a>
  AMED_AARCH64_PAGE_FRINTX_float, //!< <a href="../target/aarch64/FRINTX_float.html">FRINTX (scalar):Floating-point Round to Integral exact, using current rounding mode (scalar)</a>
  AMED_AARCH64_PAGE_FRINTZ_advsimd, //!< <a href="../target/aarch64/FRINTZ_advsimd.html">FRINTZ (vector):Floating-point Round to Integral, toward Zero (vector)</a>
  AMED_AARCH64_PAGE_FRINTZ_float, //!< <a href="../target/aarch64/FRINTZ_float.html">FRINTZ (scalar):Floating-point Round to Integral, toward Zero (scalar)</a>
  AMED_AARCH64_PAGE_FRSQRTE_advsimd, //!< <a href="../target/aarch64/FRSQRTE_advsimd.html">FRSQRTE:Floating-point Reciprocal Square Root Estimate</a>
  AMED_AARCH64_PAGE_FRSQRTS_advsimd, //!< <a href="../target/aarch64/FRSQRTS_advsimd.html">FRSQRTS:Floating-point Reciprocal Square Root Step</a>
  AMED_AARCH64_PAGE_FSQRT_advsimd, //!< <a href="../target/aarch64/FSQRT_advsimd.html">FSQRT (vector):Floating-point Square Root (vector)</a>
  AMED_AARCH64_PAGE_FSQRT_float, //!< <a href="../target/aarch64/FSQRT_float.html">FSQRT (scalar):Floating-point Square Root (scalar)</a>
  AMED_AARCH64_PAGE_FSUB_advsimd, //!< <a href="../target/aarch64/FSUB_advsimd.html">FSUB (vector):Floating-point Subtract (vector)</a>
  AMED_AARCH64_PAGE_FSUB_float, //!< <a href="../target/aarch64/FSUB_float.html">FSUB (scalar):Floating-point Subtract (scalar)</a>
  AMED_AARCH64_PAGE_INS_advsimd_elt, //!< <a href="../target/aarch64/INS_advsimd_elt.html">INS (element):Insert vector element from another vector element</a>
  AMED_AARCH64_PAGE_INS_advsimd_gen, //!< <a href="../target/aarch64/INS_advsimd_gen.html">INS (general):Insert vector element from general-purpose register</a>
  AMED_AARCH64_PAGE_LD1_advsimd_mult, //!< <a href="../target/aarch64/LD1_advsimd_mult.html">LD1 (multiple structures):Load multiple single-element structures to one, two, three, or four registers</a>
  AMED_AARCH64_PAGE_LD1_advsimd_sngl, //!< <a href="../target/aarch64/LD1_advsimd_sngl.html">LD1 (single structure):Load one single-element structure to one lane of one register</a>
  AMED_AARCH64_PAGE_LD1R_advsimd, //!< <a href="../target/aarch64/LD1R_advsimd.html">LD1R:Load one single-element structure and Replicate to all lanes (of one register)</a>
  AMED_AARCH64_PAGE_LD2_advsimd_mult, //!< <a href="../target/aarch64/LD2_advsimd_mult.html">LD2 (multiple structures):Load multiple 2-element structures to two registers</a>
  AMED_AARCH64_PAGE_LD2_advsimd_sngl, //!< <a href="../target/aarch64/LD2_advsimd_sngl.html">LD2 (single structure):Load single 2-element structure to one lane of two registers</a>
  AMED_AARCH64_PAGE_LD2R_advsimd, //!< <a href="../target/aarch64/LD2R_advsimd.html">LD2R:Load single 2-element structure and Replicate to all lanes of two registers</a>
  AMED_AARCH64_PAGE_LD3_advsimd_mult, //!< <a href="../target/aarch64/LD3_advsimd_mult.html">LD3 (multiple structures):Load multiple 3-element structures to three registers</a>
  AMED_AARCH64_PAGE_LD3_advsimd_sngl, //!< <a href="../target/aarch64/LD3_advsimd_sngl.html">LD3 (single structure):Load single 3-element structure to one lane of three registers)</a>
  AMED_AARCH64_PAGE_LD3R_advsimd, //!< <a href="../target/aarch64/LD3R_advsimd.html">LD3R:Load single 3-element structure and Replicate to all lanes of three registers</a>
  AMED_AARCH64_PAGE_LD4_advsimd_mult, //!< <a href="../target/aarch64/LD4_advsimd_mult.html">LD4 (multiple structures):Load multiple 4-element structures to four registers</a>
  AMED_AARCH64_PAGE_LD4_advsimd_sngl, //!< <a href="../target/aarch64/LD4_advsimd_sngl.html">LD4 (single structure):Load single 4-element structure to one lane of four registers</a>
  AMED_AARCH64_PAGE_LD4R_advsimd, //!< <a href="../target/aarch64/LD4R_advsimd.html">LD4R:Load single 4-element structure and Replicate to all lanes of four registers</a>
  AMED_AARCH64_PAGE_LDNP_fpsimd, //!< <a href="../target/aarch64/LDNP_fpsimd.html">LDNP (SIMD&FP):Load Pair of SIMD&FP registers, with Non-temporal hint</a>
  AMED_AARCH64_PAGE_LDP_fpsimd, //!< <a href="../target/aarch64/LDP_fpsimd.html">LDP (SIMD&FP):Load Pair of SIMD&FP registers</a>
  AMED_AARCH64_PAGE_LDR_imm_fpsimd, //!< <a href="../target/aarch64/LDR_imm_fpsimd.html">LDR (immediate, SIMD&FP):Load SIMD&FP Register (immediate offset)</a>
  AMED_AARCH64_PAGE_LDR_lit_fpsimd, //!< <a href="../target/aarch64/LDR_lit_fpsimd.html">LDR (literal, SIMD&FP):Load SIMD&FP Register (PC-relative literal)</a>
  AMED_AARCH64_PAGE_LDR_reg_fpsimd, //!< <a href="../target/aarch64/LDR_reg_fpsimd.html">LDR (register, SIMD&FP):Load SIMD&FP Register (register offset)</a>
  AMED_AARCH64_PAGE_LDUR_fpsimd, //!< <a href="../target/aarch64/LDUR_fpsimd.html">LDUR (SIMD&FP):Load SIMD&FP Register (unscaled offset)</a>
  AMED_AARCH64_PAGE_MLA_advsimd_elt, //!< <a href="../target/aarch64/MLA_advsimd_elt.html">MLA (by element):Multiply-Add to accumulator (vector, by element)</a>
  AMED_AARCH64_PAGE_MLA_advsimd_vec, //!< <a href="../target/aarch64/MLA_advsimd_vec.html">MLA (vector):Multiply-Add to accumulator (vector)</a>
  AMED_AARCH64_PAGE_MLS_advsimd_elt, //!< <a href="../target/aarch64/MLS_advsimd_elt.html">MLS (by element):Multiply-Subtract from accumulator (vector, by element)</a>
  AMED_AARCH64_PAGE_MLS_advsimd_vec, //!< <a href="../target/aarch64/MLS_advsimd_vec.html">MLS (vector):Multiply-Subtract from accumulator (vector)</a>
  AMED_AARCH64_PAGE_MOVI_advsimd, //!< <a href="../target/aarch64/MOVI_advsimd.html">MOVI:Move Immediate (vector)</a>
  AMED_AARCH64_PAGE_MUL_advsimd_elt, //!< <a href="../target/aarch64/MUL_advsimd_elt.html">MUL (by element):Multiply (vector, by element)</a>
  AMED_AARCH64_PAGE_MUL_advsimd_vec, //!< <a href="../target/aarch64/MUL_advsimd_vec.html">MUL (vector):Multiply (vector)</a>
  AMED_AARCH64_PAGE_MVNI_advsimd, //!< <a href="../target/aarch64/MVNI_advsimd.html">MVNI:Move inverted Immediate (vector)</a>
  AMED_AARCH64_PAGE_NEG_advsimd, //!< <a href="../target/aarch64/NEG_advsimd.html">NEG (vector):Negate (vector)</a>
  AMED_AARCH64_PAGE_NOT_advsimd, //!< <a href="../target/aarch64/NOT_advsimd.html">NOT:Bitwise NOT (vector)</a>
  AMED_AARCH64_PAGE_ORN_advsimd, //!< <a href="../target/aarch64/ORN_advsimd.html">ORN (vector):Bitwise inclusive OR NOT (vector)</a>
  AMED_AARCH64_PAGE_ORR_advsimd_imm, //!< <a href="../target/aarch64/ORR_advsimd_imm.html">ORR (vector, immediate):Bitwise inclusive OR (vector, immediate)</a>
  AMED_AARCH64_PAGE_ORR_advsimd_reg, //!< <a href="../target/aarch64/ORR_advsimd_reg.html">ORR (vector, register):Bitwise inclusive OR (vector, register)</a>
  AMED_AARCH64_PAGE_PMUL_advsimd, //!< <a href="../target/aarch64/PMUL_advsimd.html">PMUL:Polynomial Multiply</a>
  AMED_AARCH64_PAGE_PMULL_advsimd, //!< <a href="../target/aarch64/PMULL_advsimd.html">PMULL, PMULL2:Polynomial Multiply Long</a>
  AMED_AARCH64_PAGE_RADDHN_advsimd, //!< <a href="../target/aarch64/RADDHN_advsimd.html">RADDHN, RADDHN2:Rounding Add returning High Narrow</a>
  AMED_AARCH64_PAGE_RAX1_advsimd, //!< <a href="../target/aarch64/RAX1_advsimd.html">RAX1:Rotate and Exclusive OR</a>
  AMED_AARCH64_PAGE_RBIT_advsimd, //!< <a href="../target/aarch64/RBIT_advsimd.html">RBIT (vector):Reverse Bit order (vector)</a>
  AMED_AARCH64_PAGE_REV16_advsimd, //!< <a href="../target/aarch64/REV16_advsimd.html">REV16 (vector):Reverse elements in 16-bit halfwords (vector)</a>
  AMED_AARCH64_PAGE_REV32_advsimd, //!< <a href="../target/aarch64/REV32_advsimd.html">REV32 (vector):Reverse elements in 32-bit words (vector)</a>
  AMED_AARCH64_PAGE_REV64_advsimd, //!< <a href="../target/aarch64/REV64_advsimd.html">REV64:Reverse elements in 64-bit doublewords (vector)</a>
  AMED_AARCH64_PAGE_RSHRN_advsimd, //!< <a href="../target/aarch64/RSHRN_advsimd.html">RSHRN, RSHRN2:Rounding Shift Right Narrow (immediate)</a>
  AMED_AARCH64_PAGE_RSUBHN_advsimd, //!< <a href="../target/aarch64/RSUBHN_advsimd.html">RSUBHN, RSUBHN2:Rounding Subtract returning High Narrow</a>
  AMED_AARCH64_PAGE_SABA_advsimd, //!< <a href="../target/aarch64/SABA_advsimd.html">SABA:Signed Absolute difference and Accumulate</a>
  AMED_AARCH64_PAGE_SABAL_advsimd, //!< <a href="../target/aarch64/SABAL_advsimd.html">SABAL, SABAL2:Signed Absolute difference and Accumulate Long</a>
  AMED_AARCH64_PAGE_SABD_advsimd, //!< <a href="../target/aarch64/SABD_advsimd.html">SABD:Signed Absolute Difference</a>
  AMED_AARCH64_PAGE_SABDL_advsimd, //!< <a href="../target/aarch64/SABDL_advsimd.html">SABDL, SABDL2:Signed Absolute Difference Long</a>
  AMED_AARCH64_PAGE_SADALP_advsimd, //!< <a href="../target/aarch64/SADALP_advsimd.html">SADALP:Signed Add and Accumulate Long Pairwise</a>
  AMED_AARCH64_PAGE_SADDL_advsimd, //!< <a href="../target/aarch64/SADDL_advsimd.html">SADDL, SADDL2:Signed Add Long (vector)</a>
  AMED_AARCH64_PAGE_SADDLP_advsimd, //!< <a href="../target/aarch64/SADDLP_advsimd.html">SADDLP:Signed Add Long Pairwise</a>
  AMED_AARCH64_PAGE_SADDLV_advsimd, //!< <a href="../target/aarch64/SADDLV_advsimd.html">SADDLV:Signed Add Long across Vector</a>
  AMED_AARCH64_PAGE_SADDW_advsimd, //!< <a href="../target/aarch64/SADDW_advsimd.html">SADDW, SADDW2:Signed Add Wide</a>
  AMED_AARCH64_PAGE_SCVTF_advsimd_fix, //!< <a href="../target/aarch64/SCVTF_advsimd_fix.html">SCVTF (vector, fixed-point):Signed fixed-point Convert to Floating-point (vector)</a>
  AMED_AARCH64_PAGE_SCVTF_advsimd_int, //!< <a href="../target/aarch64/SCVTF_advsimd_int.html">SCVTF (vector, integer):Signed integer Convert to Floating-point (vector)</a>
  AMED_AARCH64_PAGE_SCVTF_float_fix, //!< <a href="../target/aarch64/SCVTF_float_fix.html">SCVTF (scalar, fixed-point):Signed fixed-point Convert to Floating-point (scalar)</a>
  AMED_AARCH64_PAGE_SCVTF_float_int, //!< <a href="../target/aarch64/SCVTF_float_int.html">SCVTF (scalar, integer):Signed integer Convert to Floating-point (scalar)</a>
  AMED_AARCH64_PAGE_SDOT_advsimd_elt, //!< <a href="../target/aarch64/SDOT_advsimd_elt.html">SDOT (by element):Dot Product signed arithmetic (vector, by element)</a>
  AMED_AARCH64_PAGE_SDOT_advsimd_vec, //!< <a href="../target/aarch64/SDOT_advsimd_vec.html">SDOT (vector):Dot Product signed arithmetic (vector)</a>
  AMED_AARCH64_PAGE_SHA1C_advsimd, //!< <a href="../target/aarch64/SHA1C_advsimd.html">SHA1C:SHA1 hash update (choose)</a>
  AMED_AARCH64_PAGE_SHA1H_advsimd, //!< <a href="../target/aarch64/SHA1H_advsimd.html">SHA1H:SHA1 fixed rotate</a>
  AMED_AARCH64_PAGE_SHA1M_advsimd, //!< <a href="../target/aarch64/SHA1M_advsimd.html">SHA1M:SHA1 hash update (majority)</a>
  AMED_AARCH64_PAGE_SHA1P_advsimd, //!< <a href="../target/aarch64/SHA1P_advsimd.html">SHA1P:SHA1 hash update (parity)</a>
  AMED_AARCH64_PAGE_SHA1SU0_advsimd, //!< <a href="../target/aarch64/SHA1SU0_advsimd.html">SHA1SU0:SHA1 schedule update 0</a>
  AMED_AARCH64_PAGE_SHA1SU1_advsimd, //!< <a href="../target/aarch64/SHA1SU1_advsimd.html">SHA1SU1:SHA1 schedule update 1</a>
  AMED_AARCH64_PAGE_SHA256H2_advsimd, //!< <a href="../target/aarch64/SHA256H2_advsimd.html">SHA256H2:SHA256 hash update (part 2)</a>
  AMED_AARCH64_PAGE_SHA256H_advsimd, //!< <a href="../target/aarch64/SHA256H_advsimd.html">SHA256H:SHA256 hash update (part 1)</a>
  AMED_AARCH64_PAGE_SHA256SU0_advsimd, //!< <a href="../target/aarch64/SHA256SU0_advsimd.html">SHA256SU0:SHA256 schedule update 0</a>
  AMED_AARCH64_PAGE_SHA256SU1_advsimd, //!< <a href="../target/aarch64/SHA256SU1_advsimd.html">SHA256SU1:SHA256 schedule update 1</a>
  AMED_AARCH64_PAGE_SHA512H2_advsimd, //!< <a href="../target/aarch64/SHA512H2_advsimd.html">SHA512H2:SHA512 Hash update part 2</a>
  AMED_AARCH64_PAGE_SHA512H_advsimd, //!< <a href="../target/aarch64/SHA512H_advsimd.html">SHA512H:SHA512 Hash update part 1</a>
  AMED_AARCH64_PAGE_SHA512SU0_advsimd, //!< <a href="../target/aarch64/SHA512SU0_advsimd.html">SHA512SU0:SHA512 Schedule Update 0</a>
  AMED_AARCH64_PAGE_SHA512SU1_advsimd, //!< <a href="../target/aarch64/SHA512SU1_advsimd.html">SHA512SU1:SHA512 Schedule Update 1</a>
  AMED_AARCH64_PAGE_SHADD_advsimd, //!< <a href="../target/aarch64/SHADD_advsimd.html">SHADD:Signed Halving Add</a>
  AMED_AARCH64_PAGE_SHL_advsimd, //!< <a href="../target/aarch64/SHL_advsimd.html">SHL:Shift Left (immediate)</a>
  AMED_AARCH64_PAGE_SHLL_advsimd, //!< <a href="../target/aarch64/SHLL_advsimd.html">SHLL, SHLL2:Shift Left Long (by element size)</a>
  AMED_AARCH64_PAGE_SHRN_advsimd, //!< <a href="../target/aarch64/SHRN_advsimd.html">SHRN, SHRN2:Shift Right Narrow (immediate)</a>
  AMED_AARCH64_PAGE_SHSUB_advsimd, //!< <a href="../target/aarch64/SHSUB_advsimd.html">SHSUB:Signed Halving Subtract</a>
  AMED_AARCH64_PAGE_SLI_advsimd, //!< <a href="../target/aarch64/SLI_advsimd.html">SLI:Shift Left and Insert (immediate)</a>
  AMED_AARCH64_PAGE_SM3PARTW1_advsimd, //!< <a href="../target/aarch64/SM3PARTW1_advsimd.html">SM3PARTW1:SM3PARTW1</a>
  AMED_AARCH64_PAGE_SM3PARTW2_advsimd, //!< <a href="../target/aarch64/SM3PARTW2_advsimd.html">SM3PARTW2:SM3PARTW2</a>
  AMED_AARCH64_PAGE_SM3SS1_advsimd, //!< <a href="../target/aarch64/SM3SS1_advsimd.html">SM3SS1:SM3SS1</a>
  AMED_AARCH64_PAGE_SM3TT1A_advsimd, //!< <a href="../target/aarch64/SM3TT1A_advsimd.html">SM3TT1A:SM3TT1A</a>
  AMED_AARCH64_PAGE_SM3TT1B_advsimd, //!< <a href="../target/aarch64/SM3TT1B_advsimd.html">SM3TT1B:SM3TT1B</a>
  AMED_AARCH64_PAGE_SM3TT2A_advsimd, //!< <a href="../target/aarch64/SM3TT2A_advsimd.html">SM3TT2A:SM3TT2A</a>
  AMED_AARCH64_PAGE_SM3TT2B_advsimd, //!< <a href="../target/aarch64/SM3TT2B_advsimd.html">SM3TT2B:SM3TT2B</a>
  AMED_AARCH64_PAGE_SM4E_advsimd, //!< <a href="../target/aarch64/SM4E_advsimd.html">SM4E:SM4 Encode</a>
  AMED_AARCH64_PAGE_SM4EKEY_advsimd, //!< <a href="../target/aarch64/SM4EKEY_advsimd.html">SM4EKEY:SM4 Key</a>
  AMED_AARCH64_PAGE_SMAX_advsimd, //!< <a href="../target/aarch64/SMAX_advsimd.html">SMAX:Signed Maximum (vector)</a>
  AMED_AARCH64_PAGE_SMAXP_advsimd, //!< <a href="../target/aarch64/SMAXP_advsimd.html">SMAXP:Signed Maximum Pairwise</a>
  AMED_AARCH64_PAGE_SMAXV_advsimd, //!< <a href="../target/aarch64/SMAXV_advsimd.html">SMAXV:Signed Maximum across Vector</a>
  AMED_AARCH64_PAGE_SMIN_advsimd, //!< <a href="../target/aarch64/SMIN_advsimd.html">SMIN:Signed Minimum (vector)</a>
  AMED_AARCH64_PAGE_SMINP_advsimd, //!< <a href="../target/aarch64/SMINP_advsimd.html">SMINP:Signed Minimum Pairwise</a>
  AMED_AARCH64_PAGE_SMINV_advsimd, //!< <a href="../target/aarch64/SMINV_advsimd.html">SMINV:Signed Minimum across Vector</a>
  AMED_AARCH64_PAGE_SMLAL_advsimd_elt, //!< <a href="../target/aarch64/SMLAL_advsimd_elt.html">SMLAL, SMLAL2 (by element):Signed Multiply-Add Long (vector, by element)</a>
  AMED_AARCH64_PAGE_SMLAL_advsimd_vec, //!< <a href="../target/aarch64/SMLAL_advsimd_vec.html">SMLAL, SMLAL2 (vector):Signed Multiply-Add Long (vector)</a>
  AMED_AARCH64_PAGE_SMLSL_advsimd_elt, //!< <a href="../target/aarch64/SMLSL_advsimd_elt.html">SMLSL, SMLSL2 (by element):Signed Multiply-Subtract Long (vector, by element)</a>
  AMED_AARCH64_PAGE_SMLSL_advsimd_vec, //!< <a href="../target/aarch64/SMLSL_advsimd_vec.html">SMLSL, SMLSL2 (vector):Signed Multiply-Subtract Long (vector)</a>
  AMED_AARCH64_PAGE_SMMLA_advsimd_vec, //!< <a href="../target/aarch64/SMMLA_advsimd_vec.html">SMMLA (vector):Signed 8-bit integer matrix multiply-accumulate (vector)</a>
  AMED_AARCH64_PAGE_SMOV_advsimd, //!< <a href="../target/aarch64/SMOV_advsimd.html">SMOV:Signed Move vector element to general-purpose register</a>
  AMED_AARCH64_PAGE_SMULL_advsimd_elt, //!< <a href="../target/aarch64/SMULL_advsimd_elt.html">SMULL, SMULL2 (by element):Signed Multiply Long (vector, by element)</a>
  AMED_AARCH64_PAGE_SMULL_advsimd_vec, //!< <a href="../target/aarch64/SMULL_advsimd_vec.html">SMULL, SMULL2 (vector):Signed Multiply Long (vector)</a>
  AMED_AARCH64_PAGE_SQABS_advsimd, //!< <a href="../target/aarch64/SQABS_advsimd.html">SQABS:Signed saturating Absolute value</a>
  AMED_AARCH64_PAGE_SQADD_advsimd, //!< <a href="../target/aarch64/SQADD_advsimd.html">SQADD:Signed saturating Add</a>
  AMED_AARCH64_PAGE_SQDMLAL_advsimd_elt, //!< <a href="../target/aarch64/SQDMLAL_advsimd_elt.html">SQDMLAL, SQDMLAL2 (by element):Signed saturating Doubling Multiply-Add Long (by element)</a>
  AMED_AARCH64_PAGE_SQDMLAL_advsimd_vec, //!< <a href="../target/aarch64/SQDMLAL_advsimd_vec.html">SQDMLAL, SQDMLAL2 (vector):Signed saturating Doubling Multiply-Add Long</a>
  AMED_AARCH64_PAGE_SQDMLSL_advsimd_elt, //!< <a href="../target/aarch64/SQDMLSL_advsimd_elt.html">SQDMLSL, SQDMLSL2 (by element):Signed saturating Doubling Multiply-Subtract Long (by element)</a>
  AMED_AARCH64_PAGE_SQDMLSL_advsimd_vec, //!< <a href="../target/aarch64/SQDMLSL_advsimd_vec.html">SQDMLSL, SQDMLSL2 (vector):Signed saturating Doubling Multiply-Subtract Long</a>
  AMED_AARCH64_PAGE_SQDMULH_advsimd_elt, //!< <a href="../target/aarch64/SQDMULH_advsimd_elt.html">SQDMULH (by element):Signed saturating Doubling Multiply returning High half (by element)</a>
  AMED_AARCH64_PAGE_SQDMULH_advsimd_vec, //!< <a href="../target/aarch64/SQDMULH_advsimd_vec.html">SQDMULH (vector):Signed saturating Doubling Multiply returning High half</a>
  AMED_AARCH64_PAGE_SQDMULL_advsimd_elt, //!< <a href="../target/aarch64/SQDMULL_advsimd_elt.html">SQDMULL, SQDMULL2 (by element):Signed saturating Doubling Multiply Long (by element)</a>
  AMED_AARCH64_PAGE_SQDMULL_advsimd_vec, //!< <a href="../target/aarch64/SQDMULL_advsimd_vec.html">SQDMULL, SQDMULL2 (vector):Signed saturating Doubling Multiply Long</a>
  AMED_AARCH64_PAGE_SQNEG_advsimd, //!< <a href="../target/aarch64/SQNEG_advsimd.html">SQNEG:Signed saturating Negate</a>
  AMED_AARCH64_PAGE_SQRDMLAH_advsimd_elt, //!< <a href="../target/aarch64/SQRDMLAH_advsimd_elt.html">SQRDMLAH (by element):Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (by element)</a>
  AMED_AARCH64_PAGE_SQRDMLAH_advsimd_vec, //!< <a href="../target/aarch64/SQRDMLAH_advsimd_vec.html">SQRDMLAH (vector):Signed Saturating Rounding Doubling Multiply Accumulate returning High Half (vector)</a>
  AMED_AARCH64_PAGE_SQRDMLSH_advsimd_elt, //!< <a href="../target/aarch64/SQRDMLSH_advsimd_elt.html">SQRDMLSH (by element):Signed Saturating Rounding Doubling Multiply Subtract returning High Half (by element)</a>
  AMED_AARCH64_PAGE_SQRDMLSH_advsimd_vec, //!< <a href="../target/aarch64/SQRDMLSH_advsimd_vec.html">SQRDMLSH (vector):Signed Saturating Rounding Doubling Multiply Subtract returning High Half (vector)</a>
  AMED_AARCH64_PAGE_SQRDMULH_advsimd_elt, //!< <a href="../target/aarch64/SQRDMULH_advsimd_elt.html">SQRDMULH (by element):Signed saturating Rounding Doubling Multiply returning High half (by element)</a>
  AMED_AARCH64_PAGE_SQRDMULH_advsimd_vec, //!< <a href="../target/aarch64/SQRDMULH_advsimd_vec.html">SQRDMULH (vector):Signed saturating Rounding Doubling Multiply returning High half</a>
  AMED_AARCH64_PAGE_SQRSHL_advsimd, //!< <a href="../target/aarch64/SQRSHL_advsimd.html">SQRSHL:Signed saturating Rounding Shift Left (register)</a>
  AMED_AARCH64_PAGE_SQRSHRN_advsimd, //!< <a href="../target/aarch64/SQRSHRN_advsimd.html">SQRSHRN, SQRSHRN2:Signed saturating Rounded Shift Right Narrow (immediate)</a>
  AMED_AARCH64_PAGE_SQRSHRUN_advsimd, //!< <a href="../target/aarch64/SQRSHRUN_advsimd.html">SQRSHRUN, SQRSHRUN2:Signed saturating Rounded Shift Right Unsigned Narrow (immediate)</a>
  AMED_AARCH64_PAGE_SQSHL_advsimd_imm, //!< <a href="../target/aarch64/SQSHL_advsimd_imm.html">SQSHL (immediate):Signed saturating Shift Left (immediate)</a>
  AMED_AARCH64_PAGE_SQSHL_advsimd_reg, //!< <a href="../target/aarch64/SQSHL_advsimd_reg.html">SQSHL (register):Signed saturating Shift Left (register)</a>
  AMED_AARCH64_PAGE_SQSHLU_advsimd, //!< <a href="../target/aarch64/SQSHLU_advsimd.html">SQSHLU:Signed saturating Shift Left Unsigned (immediate)</a>
  AMED_AARCH64_PAGE_SQSHRN_advsimd, //!< <a href="../target/aarch64/SQSHRN_advsimd.html">SQSHRN, SQSHRN2:Signed saturating Shift Right Narrow (immediate)</a>
  AMED_AARCH64_PAGE_SQSHRUN_advsimd, //!< <a href="../target/aarch64/SQSHRUN_advsimd.html">SQSHRUN, SQSHRUN2:Signed saturating Shift Right Unsigned Narrow (immediate)</a>
  AMED_AARCH64_PAGE_SQSUB_advsimd, //!< <a href="../target/aarch64/SQSUB_advsimd.html">SQSUB:Signed saturating Subtract</a>
  AMED_AARCH64_PAGE_SQXTN_advsimd, //!< <a href="../target/aarch64/SQXTN_advsimd.html">SQXTN, SQXTN2:Signed saturating extract Narrow</a>
  AMED_AARCH64_PAGE_SQXTUN_advsimd, //!< <a href="../target/aarch64/SQXTUN_advsimd.html">SQXTUN, SQXTUN2:Signed saturating extract Unsigned Narrow</a>
  AMED_AARCH64_PAGE_SRHADD_advsimd, //!< <a href="../target/aarch64/SRHADD_advsimd.html">SRHADD:Signed Rounding Halving Add</a>
  AMED_AARCH64_PAGE_SRI_advsimd, //!< <a href="../target/aarch64/SRI_advsimd.html">SRI:Shift Right and Insert (immediate)</a>
  AMED_AARCH64_PAGE_SRSHL_advsimd, //!< <a href="../target/aarch64/SRSHL_advsimd.html">SRSHL:Signed Rounding Shift Left (register)</a>
  AMED_AARCH64_PAGE_SRSHR_advsimd, //!< <a href="../target/aarch64/SRSHR_advsimd.html">SRSHR:Signed Rounding Shift Right (immediate)</a>
  AMED_AARCH64_PAGE_SRSRA_advsimd, //!< <a href="../target/aarch64/SRSRA_advsimd.html">SRSRA:Signed Rounding Shift Right and Accumulate (immediate)</a>
  AMED_AARCH64_PAGE_SSHL_advsimd, //!< <a href="../target/aarch64/SSHL_advsimd.html">SSHL:Signed Shift Left (register)</a>
  AMED_AARCH64_PAGE_SSHLL_advsimd, //!< <a href="../target/aarch64/SSHLL_advsimd.html">SSHLL, SSHLL2:Signed Shift Left Long (immediate)</a>
  AMED_AARCH64_PAGE_SSHR_advsimd, //!< <a href="../target/aarch64/SSHR_advsimd.html">SSHR:Signed Shift Right (immediate)</a>
  AMED_AARCH64_PAGE_SSRA_advsimd, //!< <a href="../target/aarch64/SSRA_advsimd.html">SSRA:Signed Shift Right and Accumulate (immediate)</a>
  AMED_AARCH64_PAGE_SSUBL_advsimd, //!< <a href="../target/aarch64/SSUBL_advsimd.html">SSUBL, SSUBL2:Signed Subtract Long</a>
  AMED_AARCH64_PAGE_SSUBW_advsimd, //!< <a href="../target/aarch64/SSUBW_advsimd.html">SSUBW, SSUBW2:Signed Subtract Wide</a>
  AMED_AARCH64_PAGE_ST1_advsimd_mult, //!< <a href="../target/aarch64/ST1_advsimd_mult.html">ST1 (multiple structures):Store multiple single-element structures from one, two, three, or four registers</a>
  AMED_AARCH64_PAGE_ST1_advsimd_sngl, //!< <a href="../target/aarch64/ST1_advsimd_sngl.html">ST1 (single structure):Store a single-element structure from one lane of one register</a>
  AMED_AARCH64_PAGE_ST2_advsimd_mult, //!< <a href="../target/aarch64/ST2_advsimd_mult.html">ST2 (multiple structures):Store multiple 2-element structures from two registers</a>
  AMED_AARCH64_PAGE_ST2_advsimd_sngl, //!< <a href="../target/aarch64/ST2_advsimd_sngl.html">ST2 (single structure):Store single 2-element structure from one lane of two registers</a>
  AMED_AARCH64_PAGE_ST3_advsimd_mult, //!< <a href="../target/aarch64/ST3_advsimd_mult.html">ST3 (multiple structures):Store multiple 3-element structures from three registers</a>
  AMED_AARCH64_PAGE_ST3_advsimd_sngl, //!< <a href="../target/aarch64/ST3_advsimd_sngl.html">ST3 (single structure):Store single 3-element structure from one lane of three registers</a>
  AMED_AARCH64_PAGE_ST4_advsimd_mult, //!< <a href="../target/aarch64/ST4_advsimd_mult.html">ST4 (multiple structures):Store multiple 4-element structures from four registers</a>
  AMED_AARCH64_PAGE_ST4_advsimd_sngl, //!< <a href="../target/aarch64/ST4_advsimd_sngl.html">ST4 (single structure):Store single 4-element structure from one lane of four registers</a>
  AMED_AARCH64_PAGE_STNP_fpsimd, //!< <a href="../target/aarch64/STNP_fpsimd.html">STNP (SIMD&FP):Store Pair of SIMD&FP registers, with Non-temporal hint</a>
  AMED_AARCH64_PAGE_STP_fpsimd, //!< <a href="../target/aarch64/STP_fpsimd.html">STP (SIMD&FP):Store Pair of SIMD&FP registers</a>
  AMED_AARCH64_PAGE_STR_imm_fpsimd, //!< <a href="../target/aarch64/STR_imm_fpsimd.html">STR (immediate, SIMD&FP):Store SIMD&FP register (immediate offset)</a>
  AMED_AARCH64_PAGE_STR_reg_fpsimd, //!< <a href="../target/aarch64/STR_reg_fpsimd.html">STR (register, SIMD&FP):Store SIMD&FP register (register offset)</a>
  AMED_AARCH64_PAGE_STUR_fpsimd, //!< <a href="../target/aarch64/STUR_fpsimd.html">STUR (SIMD&FP):Store SIMD&FP register (unscaled offset)</a>
  AMED_AARCH64_PAGE_SUB_advsimd, //!< <a href="../target/aarch64/SUB_advsimd.html">SUB (vector):Subtract (vector)</a>
  AMED_AARCH64_PAGE_SUBHN_advsimd, //!< <a href="../target/aarch64/SUBHN_advsimd.html">SUBHN, SUBHN2:Subtract returning High Narrow</a>
  AMED_AARCH64_PAGE_SUDOT_advsimd_elt, //!< <a href="../target/aarch64/SUDOT_advsimd_elt.html">SUDOT (by element):Dot product with signed and unsigned integers (vector, by element)</a>
  AMED_AARCH64_PAGE_SUQADD_advsimd, //!< <a href="../target/aarch64/SUQADD_advsimd.html">SUQADD:Signed saturating Accumulate of Unsigned value</a>
  AMED_AARCH64_PAGE_TBL_advsimd, //!< <a href="../target/aarch64/TBL_advsimd.html">TBL:Table vector Lookup</a>
  AMED_AARCH64_PAGE_TBX_advsimd, //!< <a href="../target/aarch64/TBX_advsimd.html">TBX:Table vector lookup extension</a>
  AMED_AARCH64_PAGE_TRN1_advsimd, //!< <a href="../target/aarch64/TRN1_advsimd.html">TRN1:Transpose vectors (primary)</a>
  AMED_AARCH64_PAGE_TRN2_advsimd, //!< <a href="../target/aarch64/TRN2_advsimd.html">TRN2:Transpose vectors (secondary)</a>
  AMED_AARCH64_PAGE_UABA_advsimd, //!< <a href="../target/aarch64/UABA_advsimd.html">UABA:Unsigned Absolute difference and Accumulate</a>
  AMED_AARCH64_PAGE_UABAL_advsimd, //!< <a href="../target/aarch64/UABAL_advsimd.html">UABAL, UABAL2:Unsigned Absolute difference and Accumulate Long</a>
  AMED_AARCH64_PAGE_UABD_advsimd, //!< <a href="../target/aarch64/UABD_advsimd.html">UABD:Unsigned Absolute Difference (vector)</a>
  AMED_AARCH64_PAGE_UABDL_advsimd, //!< <a href="../target/aarch64/UABDL_advsimd.html">UABDL, UABDL2:Unsigned Absolute Difference Long</a>
  AMED_AARCH64_PAGE_UADALP_advsimd, //!< <a href="../target/aarch64/UADALP_advsimd.html">UADALP:Unsigned Add and Accumulate Long Pairwise</a>
  AMED_AARCH64_PAGE_UADDL_advsimd, //!< <a href="../target/aarch64/UADDL_advsimd.html">UADDL, UADDL2:Unsigned Add Long (vector)</a>
  AMED_AARCH64_PAGE_UADDLP_advsimd, //!< <a href="../target/aarch64/UADDLP_advsimd.html">UADDLP:Unsigned Add Long Pairwise</a>
  AMED_AARCH64_PAGE_UADDLV_advsimd, //!< <a href="../target/aarch64/UADDLV_advsimd.html">UADDLV:Unsigned sum Long across Vector</a>
  AMED_AARCH64_PAGE_UADDW_advsimd, //!< <a href="../target/aarch64/UADDW_advsimd.html">UADDW, UADDW2:Unsigned Add Wide</a>
  AMED_AARCH64_PAGE_UCVTF_advsimd_fix, //!< <a href="../target/aarch64/UCVTF_advsimd_fix.html">UCVTF (vector, fixed-point):Unsigned fixed-point Convert to Floating-point (vector)</a>
  AMED_AARCH64_PAGE_UCVTF_advsimd_int, //!< <a href="../target/aarch64/UCVTF_advsimd_int.html">UCVTF (vector, integer):Unsigned integer Convert to Floating-point (vector)</a>
  AMED_AARCH64_PAGE_UCVTF_float_fix, //!< <a href="../target/aarch64/UCVTF_float_fix.html">UCVTF (scalar, fixed-point):Unsigned fixed-point Convert to Floating-point (scalar)</a>
  AMED_AARCH64_PAGE_UCVTF_float_int, //!< <a href="../target/aarch64/UCVTF_float_int.html">UCVTF (scalar, integer):Unsigned integer Convert to Floating-point (scalar)</a>
  AMED_AARCH64_PAGE_UDOT_advsimd_elt, //!< <a href="../target/aarch64/UDOT_advsimd_elt.html">UDOT (by element):Dot Product unsigned arithmetic (vector, by element)</a>
  AMED_AARCH64_PAGE_UDOT_advsimd_vec, //!< <a href="../target/aarch64/UDOT_advsimd_vec.html">UDOT (vector):Dot Product unsigned arithmetic (vector)</a>
  AMED_AARCH64_PAGE_UHADD_advsimd, //!< <a href="../target/aarch64/UHADD_advsimd.html">UHADD:Unsigned Halving Add</a>
  AMED_AARCH64_PAGE_UHSUB_advsimd, //!< <a href="../target/aarch64/UHSUB_advsimd.html">UHSUB:Unsigned Halving Subtract</a>
  AMED_AARCH64_PAGE_UMAX_advsimd, //!< <a href="../target/aarch64/UMAX_advsimd.html">UMAX:Unsigned Maximum (vector)</a>
  AMED_AARCH64_PAGE_UMAXP_advsimd, //!< <a href="../target/aarch64/UMAXP_advsimd.html">UMAXP:Unsigned Maximum Pairwise</a>
  AMED_AARCH64_PAGE_UMAXV_advsimd, //!< <a href="../target/aarch64/UMAXV_advsimd.html">UMAXV:Unsigned Maximum across Vector</a>
  AMED_AARCH64_PAGE_UMIN_advsimd, //!< <a href="../target/aarch64/UMIN_advsimd.html">UMIN:Unsigned Minimum (vector)</a>
  AMED_AARCH64_PAGE_UMINP_advsimd, //!< <a href="../target/aarch64/UMINP_advsimd.html">UMINP:Unsigned Minimum Pairwise</a>
  AMED_AARCH64_PAGE_UMINV_advsimd, //!< <a href="../target/aarch64/UMINV_advsimd.html">UMINV:Unsigned Minimum across Vector</a>
  AMED_AARCH64_PAGE_UMLAL_advsimd_elt, //!< <a href="../target/aarch64/UMLAL_advsimd_elt.html">UMLAL, UMLAL2 (by element):Unsigned Multiply-Add Long (vector, by element)</a>
  AMED_AARCH64_PAGE_UMLAL_advsimd_vec, //!< <a href="../target/aarch64/UMLAL_advsimd_vec.html">UMLAL, UMLAL2 (vector):Unsigned Multiply-Add Long (vector)</a>
  AMED_AARCH64_PAGE_UMLSL_advsimd_elt, //!< <a href="../target/aarch64/UMLSL_advsimd_elt.html">UMLSL, UMLSL2 (by element):Unsigned Multiply-Subtract Long (vector, by element)</a>
  AMED_AARCH64_PAGE_UMLSL_advsimd_vec, //!< <a href="../target/aarch64/UMLSL_advsimd_vec.html">UMLSL, UMLSL2 (vector):Unsigned Multiply-Subtract Long (vector)</a>
  AMED_AARCH64_PAGE_UMMLA_advsimd_vec, //!< <a href="../target/aarch64/UMMLA_advsimd_vec.html">UMMLA (vector):Unsigned 8-bit integer matrix multiply-accumulate (vector)</a>
  AMED_AARCH64_PAGE_UMOV_advsimd, //!< <a href="../target/aarch64/UMOV_advsimd.html">UMOV:Unsigned Move vector element to general-purpose register</a>
  AMED_AARCH64_PAGE_UMULL_advsimd_elt, //!< <a href="../target/aarch64/UMULL_advsimd_elt.html">UMULL, UMULL2 (by element):Unsigned Multiply Long (vector, by element)</a>
  AMED_AARCH64_PAGE_UMULL_advsimd_vec, //!< <a href="../target/aarch64/UMULL_advsimd_vec.html">UMULL, UMULL2 (vector):Unsigned Multiply long (vector)</a>
  AMED_AARCH64_PAGE_UQADD_advsimd, //!< <a href="../target/aarch64/UQADD_advsimd.html">UQADD:Unsigned saturating Add</a>
  AMED_AARCH64_PAGE_UQRSHL_advsimd, //!< <a href="../target/aarch64/UQRSHL_advsimd.html">UQRSHL:Unsigned saturating Rounding Shift Left (register)</a>
  AMED_AARCH64_PAGE_UQRSHRN_advsimd, //!< <a href="../target/aarch64/UQRSHRN_advsimd.html">UQRSHRN, UQRSHRN2:Unsigned saturating Rounded Shift Right Narrow (immediate)</a>
  AMED_AARCH64_PAGE_UQSHL_advsimd_imm, //!< <a href="../target/aarch64/UQSHL_advsimd_imm.html">UQSHL (immediate):Unsigned saturating Shift Left (immediate)</a>
  AMED_AARCH64_PAGE_UQSHL_advsimd_reg, //!< <a href="../target/aarch64/UQSHL_advsimd_reg.html">UQSHL (register):Unsigned saturating Shift Left (register)</a>
  AMED_AARCH64_PAGE_UQSHRN_advsimd, //!< <a href="../target/aarch64/UQSHRN_advsimd.html">UQSHRN, UQSHRN2:Unsigned saturating Shift Right Narrow (immediate)</a>
  AMED_AARCH64_PAGE_UQSUB_advsimd, //!< <a href="../target/aarch64/UQSUB_advsimd.html">UQSUB:Unsigned saturating Subtract</a>
  AMED_AARCH64_PAGE_UQXTN_advsimd, //!< <a href="../target/aarch64/UQXTN_advsimd.html">UQXTN, UQXTN2:Unsigned saturating extract Narrow</a>
  AMED_AARCH64_PAGE_URECPE_advsimd, //!< <a href="../target/aarch64/URECPE_advsimd.html">URECPE:Unsigned Reciprocal Estimate</a>
  AMED_AARCH64_PAGE_URHADD_advsimd, //!< <a href="../target/aarch64/URHADD_advsimd.html">URHADD:Unsigned Rounding Halving Add</a>
  AMED_AARCH64_PAGE_URSHL_advsimd, //!< <a href="../target/aarch64/URSHL_advsimd.html">URSHL:Unsigned Rounding Shift Left (register)</a>
  AMED_AARCH64_PAGE_URSHR_advsimd, //!< <a href="../target/aarch64/URSHR_advsimd.html">URSHR:Unsigned Rounding Shift Right (immediate)</a>
  AMED_AARCH64_PAGE_URSQRTE_advsimd, //!< <a href="../target/aarch64/URSQRTE_advsimd.html">URSQRTE:Unsigned Reciprocal Square Root Estimate</a>
  AMED_AARCH64_PAGE_URSRA_advsimd, //!< <a href="../target/aarch64/URSRA_advsimd.html">URSRA:Unsigned Rounding Shift Right and Accumulate (immediate)</a>
  AMED_AARCH64_PAGE_USDOT_advsimd_elt, //!< <a href="../target/aarch64/USDOT_advsimd_elt.html">USDOT (by element):Dot Product with unsigned and signed integers (vector, by element)</a>
  AMED_AARCH64_PAGE_USDOT_advsimd_vec, //!< <a href="../target/aarch64/USDOT_advsimd_vec.html">USDOT (vector):Dot Product with unsigned and signed integers (vector)</a>
  AMED_AARCH64_PAGE_USHL_advsimd, //!< <a href="../target/aarch64/USHL_advsimd.html">USHL:Unsigned Shift Left (register)</a>
  AMED_AARCH64_PAGE_USHLL_advsimd, //!< <a href="../target/aarch64/USHLL_advsimd.html">USHLL, USHLL2:Unsigned Shift Left Long (immediate)</a>
  AMED_AARCH64_PAGE_USHR_advsimd, //!< <a href="../target/aarch64/USHR_advsimd.html">USHR:Unsigned Shift Right (immediate)</a>
  AMED_AARCH64_PAGE_USMMLA_advsimd_vec, //!< <a href="../target/aarch64/USMMLA_advsimd_vec.html">USMMLA (vector):Unsigned and signed 8-bit integer matrix multiply-accumulate (vector)</a>
  AMED_AARCH64_PAGE_USQADD_advsimd, //!< <a href="../target/aarch64/USQADD_advsimd.html">USQADD:Unsigned saturating Accumulate of Signed value</a>
  AMED_AARCH64_PAGE_USRA_advsimd, //!< <a href="../target/aarch64/USRA_advsimd.html">USRA:Unsigned Shift Right and Accumulate (immediate)</a>
  AMED_AARCH64_PAGE_USUBL_advsimd, //!< <a href="../target/aarch64/USUBL_advsimd.html">USUBL, USUBL2:Unsigned Subtract Long</a>
  AMED_AARCH64_PAGE_USUBW_advsimd, //!< <a href="../target/aarch64/USUBW_advsimd.html">USUBW, USUBW2:Unsigned Subtract Wide</a>
  AMED_AARCH64_PAGE_UZP1_advsimd, //!< <a href="../target/aarch64/UZP1_advsimd.html">UZP1:Unzip vectors (primary)</a>
  AMED_AARCH64_PAGE_UZP2_advsimd, //!< <a href="../target/aarch64/UZP2_advsimd.html">UZP2:Unzip vectors (secondary)</a>
  AMED_AARCH64_PAGE_XAR_advsimd, //!< <a href="../target/aarch64/XAR_advsimd.html">XAR:Exclusive OR and Rotate</a>
  AMED_AARCH64_PAGE_XTN_advsimd, //!< <a href="../target/aarch64/XTN_advsimd.html">XTN, XTN2:Extract Narrow</a>
  AMED_AARCH64_PAGE_ZIP1_advsimd, //!< <a href="../target/aarch64/ZIP1_advsimd.html">ZIP1:Zip vectors (primary)</a>
  AMED_AARCH64_PAGE_ZIP2_advsimd, //!< <a href="../target/aarch64/ZIP2_advsimd.html">ZIP2:Zip vectors (secondary)</a>
  AMED_AARCH64_PAGE_MOV_DUP_advsimd_elt, //!< <a href="../target/aarch64/MOV_DUP_advsimd_elt.html">MOV (scalar):Move vector element to scalar</a>
  AMED_AARCH64_PAGE_MOV_INS_advsimd_elt, //!< <a href="../target/aarch64/MOV_INS_advsimd_elt.html">MOV (element):Move vector element to another vector element</a>
  AMED_AARCH64_PAGE_MOV_INS_advsimd_gen, //!< <a href="../target/aarch64/MOV_INS_advsimd_gen.html">MOV (from general):Move general-purpose register to a vector element</a>
  AMED_AARCH64_PAGE_MOV_ORR_advsimd_reg, //!< <a href="../target/aarch64/MOV_ORR_advsimd_reg.html">MOV (vector):Move vector</a>
  AMED_AARCH64_PAGE_MOV_UMOV_advsimd, //!< <a href="../target/aarch64/MOV_UMOV_advsimd.html">MOV (to general):Move vector element to general-purpose register</a>
  AMED_AARCH64_PAGE_MVN_NOT_advsimd, //!< <a href="../target/aarch64/MVN_NOT_advsimd.html">MVN:Bitwise NOT (vector)</a>
  AMED_AARCH64_PAGE_SXTL_SSHLL_advsimd, //!< <a href="../target/aarch64/SXTL_SSHLL_advsimd.html">SXTL, SXTL2:Signed extend Long</a>
  AMED_AARCH64_PAGE_UXTL_USHLL_advsimd, //!< <a href="../target/aarch64/UXTL_USHLL_advsimd.html">UXTL, UXTL2:Unsigned extend Long</a>
  AMED_AARCH64_PAGE_abs_z_p_z, //!< <a href="../target/aarch64/abs_z_p_z.html">ABS:Absolute value (predicated)</a>
  AMED_AARCH64_PAGE_adclb_z_zzz, //!< <a href="../target/aarch64/adclb_z_zzz.html">ADCLB:Add with carry long (bottom)</a>
  AMED_AARCH64_PAGE_adclt_z_zzz, //!< <a href="../target/aarch64/adclt_z_zzz.html">ADCLT:Add with carry long (top)</a>
  AMED_AARCH64_PAGE_add_z_p_zz, //!< <a href="../target/aarch64/add_z_p_zz.html">ADD (vectors, predicated):Add vectors (predicated)</a>
  AMED_AARCH64_PAGE_add_z_zi, //!< <a href="../target/aarch64/add_z_zi.html">ADD (immediate):Add immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_add_z_zz, //!< <a href="../target/aarch64/add_z_zz.html">ADD (vectors, unpredicated):Add vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_addhnb_z_zz, //!< <a href="../target/aarch64/addhnb_z_zz.html">ADDHNB:Add narrow high part (bottom)</a>
  AMED_AARCH64_PAGE_addhnt_z_zz, //!< <a href="../target/aarch64/addhnt_z_zz.html">ADDHNT:Add narrow high part (top)</a>
  AMED_AARCH64_PAGE_addp_z_p_zz, //!< <a href="../target/aarch64/addp_z_p_zz.html">ADDP:Add pairwise</a>
  AMED_AARCH64_PAGE_addpl_r_ri, //!< <a href="../target/aarch64/addpl_r_ri.html">ADDPL:Add multiple of predicate register size to scalar register</a>
  AMED_AARCH64_PAGE_addvl_r_ri, //!< <a href="../target/aarch64/addvl_r_ri.html">ADDVL:Add multiple of vector register size to scalar register</a>
  AMED_AARCH64_PAGE_adr_z_az, //!< <a href="../target/aarch64/adr_z_az.html">ADR:Compute vector address</a>
  AMED_AARCH64_PAGE_aesd_z_zz, //!< <a href="../target/aarch64/aesd_z_zz.html">AESD:AES single round decryption</a>
  AMED_AARCH64_PAGE_aese_z_zz, //!< <a href="../target/aarch64/aese_z_zz.html">AESE:AES single round encryption</a>
  AMED_AARCH64_PAGE_aesimc_z_z, //!< <a href="../target/aarch64/aesimc_z_z.html">AESIMC:AES inverse mix columns</a>
  AMED_AARCH64_PAGE_aesmc_z_z, //!< <a href="../target/aarch64/aesmc_z_z.html">AESMC:AES mix columns</a>
  AMED_AARCH64_PAGE_and_p_p_pp, //!< <a href="../target/aarch64/and_p_p_pp.html">AND, ANDS (predicates):Bitwise AND predicates</a>
  AMED_AARCH64_PAGE_and_z_p_zz, //!< <a href="../target/aarch64/and_z_p_zz.html">AND (vectors, predicated):Bitwise AND vectors (predicated)</a>
  AMED_AARCH64_PAGE_and_z_zi, //!< <a href="../target/aarch64/and_z_zi.html">AND (immediate):Bitwise AND with immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_and_z_zz, //!< <a href="../target/aarch64/and_z_zz.html">AND (vectors, unpredicated):Bitwise AND vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_andv_r_p_z, //!< <a href="../target/aarch64/andv_r_p_z.html">ANDV:Bitwise AND reduction to scalar</a>
  AMED_AARCH64_PAGE_asr_z_p_zi, //!< <a href="../target/aarch64/asr_z_p_zi.html">ASR (immediate, predicated):Arithmetic shift right by immediate (predicated)</a>
  AMED_AARCH64_PAGE_asr_z_p_zw, //!< <a href="../target/aarch64/asr_z_p_zw.html">ASR (wide elements, predicated):Arithmetic shift right by 64-bit wide elements (predicated)</a>
  AMED_AARCH64_PAGE_asr_z_p_zz, //!< <a href="../target/aarch64/asr_z_p_zz.html">ASR (vectors):Arithmetic shift right by vector (predicated)</a>
  AMED_AARCH64_PAGE_asr_z_zi, //!< <a href="../target/aarch64/asr_z_zi.html">ASR (immediate, unpredicated):Arithmetic shift right by immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_asr_z_zw, //!< <a href="../target/aarch64/asr_z_zw.html">ASR (wide elements, unpredicated):Arithmetic shift right by 64-bit wide elements (unpredicated)</a>
  AMED_AARCH64_PAGE_asrd_z_p_zi, //!< <a href="../target/aarch64/asrd_z_p_zi.html">ASRD:Arithmetic shift right for divide by immediate (predicated)</a>
  AMED_AARCH64_PAGE_asrr_z_p_zz, //!< <a href="../target/aarch64/asrr_z_p_zz.html">ASRR:Reversed arithmetic shift right by vector (predicated)</a>
  AMED_AARCH64_PAGE_bcax_z_zzz, //!< <a href="../target/aarch64/bcax_z_zzz.html">BCAX:Bitwise clear and exclusive OR</a>
  AMED_AARCH64_PAGE_bdep_z_zz, //!< <a href="../target/aarch64/bdep_z_zz.html">BDEP:Scatter lower bits into positions selected by bitmask</a>
  AMED_AARCH64_PAGE_bext_z_zz, //!< <a href="../target/aarch64/bext_z_zz.html">BEXT:Gather lower bits from positions selected by bitmask</a>
  AMED_AARCH64_PAGE_bfcvt_z_p_z, //!< <a href="../target/aarch64/bfcvt_z_p_z.html">BFCVT:Floating-point down convert to BFloat16 format (predicated)</a>
  AMED_AARCH64_PAGE_bfcvtnt_z_p_z, //!< <a href="../target/aarch64/bfcvtnt_z_p_z.html">BFCVTNT:Floating-point down convert and narrow to BFloat16 (top, predicated)</a>
  AMED_AARCH64_PAGE_bfdot_z_zzz, //!< <a href="../target/aarch64/bfdot_z_zzz.html">BFDOT (vectors):BFloat16 floating-point dot product</a>
  AMED_AARCH64_PAGE_bfdot_z_zzzi, //!< <a href="../target/aarch64/bfdot_z_zzzi.html">BFDOT (indexed):BFloat16 floating-point indexed dot product</a>
  AMED_AARCH64_PAGE_bfmlalb_z_zzz, //!< <a href="../target/aarch64/bfmlalb_z_zzz.html">BFMLALB (vectors):BFloat16 floating-point multiply-add long to single-precision (bottom)</a>
  AMED_AARCH64_PAGE_bfmlalb_z_zzzi, //!< <a href="../target/aarch64/bfmlalb_z_zzzi.html">BFMLALB (indexed):BFloat16 floating-point multiply-add long to single-precision (bottom, indexed)</a>
  AMED_AARCH64_PAGE_bfmlalt_z_zzz, //!< <a href="../target/aarch64/bfmlalt_z_zzz.html">BFMLALT (vectors):BFloat16 floating-point multiply-add long to single-precision (top)</a>
  AMED_AARCH64_PAGE_bfmlalt_z_zzzi, //!< <a href="../target/aarch64/bfmlalt_z_zzzi.html">BFMLALT (indexed):BFloat16 floating-point multiply-add long to single-precision (top, indexed)</a>
  AMED_AARCH64_PAGE_bfmmla_z_zzz, //!< <a href="../target/aarch64/bfmmla_z_zzz.html">BFMMLA:BFloat16 floating-point matrix multiply-accumulate</a>
  AMED_AARCH64_PAGE_bgrp_z_zz, //!< <a href="../target/aarch64/bgrp_z_zz.html">BGRP:Group bits to right or left as selected by bitmask</a>
  AMED_AARCH64_PAGE_bic_p_p_pp, //!< <a href="../target/aarch64/bic_p_p_pp.html">BIC, BICS (predicates):Bitwise clear predicates</a>
  AMED_AARCH64_PAGE_bic_z_p_zz, //!< <a href="../target/aarch64/bic_z_p_zz.html">BIC (vectors, predicated):Bitwise clear vectors (predicated)</a>
  AMED_AARCH64_PAGE_bic_z_zz, //!< <a href="../target/aarch64/bic_z_zz.html">BIC (vectors, unpredicated):Bitwise clear vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_brka_p_p_p, //!< <a href="../target/aarch64/brka_p_p_p.html">BRKA, BRKAS:Break after first true condition</a>
  AMED_AARCH64_PAGE_brkb_p_p_p, //!< <a href="../target/aarch64/brkb_p_p_p.html">BRKB, BRKBS:Break before first true condition</a>
  AMED_AARCH64_PAGE_brkn_p_p_pp, //!< <a href="../target/aarch64/brkn_p_p_pp.html">BRKN, BRKNS:Propagate break to next partition</a>
  AMED_AARCH64_PAGE_brkpa_p_p_pp, //!< <a href="../target/aarch64/brkpa_p_p_pp.html">BRKPA, BRKPAS:Break after first true condition, propagating from previous partition</a>
  AMED_AARCH64_PAGE_brkpb_p_p_pp, //!< <a href="../target/aarch64/brkpb_p_p_pp.html">BRKPB, BRKPBS:Break before first true condition, propagating from previous partition</a>
  AMED_AARCH64_PAGE_bsl1n_z_zzz, //!< <a href="../target/aarch64/bsl1n_z_zzz.html">BSL1N:Bitwise select with first input inverted</a>
  AMED_AARCH64_PAGE_bsl2n_z_zzz, //!< <a href="../target/aarch64/bsl2n_z_zzz.html">BSL2N:Bitwise select with second input inverted</a>
  AMED_AARCH64_PAGE_bsl_z_zzz, //!< <a href="../target/aarch64/bsl_z_zzz.html">BSL:Bitwise select</a>
  AMED_AARCH64_PAGE_cadd_z_zz, //!< <a href="../target/aarch64/cadd_z_zz.html">CADD:Complex integer add with rotate</a>
  AMED_AARCH64_PAGE_cdot_z_zzz, //!< <a href="../target/aarch64/cdot_z_zzz.html">CDOT (vectors):Complex integer dot product</a>
  AMED_AARCH64_PAGE_cdot_z_zzzi, //!< <a href="../target/aarch64/cdot_z_zzzi.html">CDOT (indexed):Complex integer dot product (indexed)</a>
  AMED_AARCH64_PAGE_clasta_r_p_z, //!< <a href="../target/aarch64/clasta_r_p_z.html">CLASTA (scalar):Conditionally extract element after last to general-purpose register</a>
  AMED_AARCH64_PAGE_clasta_v_p_z, //!< <a href="../target/aarch64/clasta_v_p_z.html">CLASTA (SIMD&FP scalar):Conditionally extract element after last to SIMD&FP scalar register</a>
  AMED_AARCH64_PAGE_clasta_z_p_zz, //!< <a href="../target/aarch64/clasta_z_p_zz.html">CLASTA (vectors):Conditionally extract element after last to vector register</a>
  AMED_AARCH64_PAGE_clastb_r_p_z, //!< <a href="../target/aarch64/clastb_r_p_z.html">CLASTB (scalar):Conditionally extract last element to general-purpose register</a>
  AMED_AARCH64_PAGE_clastb_v_p_z, //!< <a href="../target/aarch64/clastb_v_p_z.html">CLASTB (SIMD&FP scalar):Conditionally extract last element to SIMD&FP scalar register</a>
  AMED_AARCH64_PAGE_clastb_z_p_zz, //!< <a href="../target/aarch64/clastb_z_p_zz.html">CLASTB (vectors):Conditionally extract last element to vector register</a>
  AMED_AARCH64_PAGE_cls_z_p_z, //!< <a href="../target/aarch64/cls_z_p_z.html">CLS:Count leading sign bits (predicated)</a>
  AMED_AARCH64_PAGE_clz_z_p_z, //!< <a href="../target/aarch64/clz_z_p_z.html">CLZ:Count leading zero bits (predicated)</a>
  AMED_AARCH64_PAGE_cmla_z_zzz, //!< <a href="../target/aarch64/cmla_z_zzz.html">CMLA (vectors):Complex integer multiply-add with rotate</a>
  AMED_AARCH64_PAGE_cmla_z_zzzi, //!< <a href="../target/aarch64/cmla_z_zzzi.html">CMLA (indexed):Complex integer multiply-add with rotate (indexed)</a>
  AMED_AARCH64_PAGE_cmpeq_p_p_zi, //!< <a href="../target/aarch64/cmpeq_p_p_zi.html">CMP<cc> (immediate):Compare vector to immediate</a>
  AMED_AARCH64_PAGE_cmpeq_p_p_zw, //!< <a href="../target/aarch64/cmpeq_p_p_zw.html">CMP<cc> (wide elements):Compare vector to 64-bit wide elements</a>
  AMED_AARCH64_PAGE_cmpeq_p_p_zz, //!< <a href="../target/aarch64/cmpeq_p_p_zz.html">CMP<cc> (vectors):Compare vectors</a>
  AMED_AARCH64_PAGE_cnot_z_p_z, //!< <a href="../target/aarch64/cnot_z_p_z.html">CNOT:Logically invert boolean condition in vector (predicated)</a>
  AMED_AARCH64_PAGE_cnt_z_p_z, //!< <a href="../target/aarch64/cnt_z_p_z.html">CNT:Count non-zero bits (predicated)</a>
  AMED_AARCH64_PAGE_cntb_r_s, //!< <a href="../target/aarch64/cntb_r_s.html">CNTB, CNTD, CNTH, CNTW:Set scalar to multiple of predicate constraint element count</a>
  AMED_AARCH64_PAGE_cntp_r_p_p, //!< <a href="../target/aarch64/cntp_r_p_p.html">CNTP:Set scalar to count of true predicate elements</a>
  AMED_AARCH64_PAGE_compact_z_p_z, //!< <a href="../target/aarch64/compact_z_p_z.html">COMPACT:Shuffle active elements of vector to the right and fill with zero</a>
  AMED_AARCH64_PAGE_cpy_z_o_i, //!< <a href="../target/aarch64/cpy_z_o_i.html">CPY (immediate, zeroing):Copy signed integer immediate to vector elements (zeroing)</a>
  AMED_AARCH64_PAGE_cpy_z_p_i, //!< <a href="../target/aarch64/cpy_z_p_i.html">CPY (immediate, merging):Copy signed integer immediate to vector elements (merging)</a>
  AMED_AARCH64_PAGE_cpy_z_p_r, //!< <a href="../target/aarch64/cpy_z_p_r.html">CPY (scalar):Copy general-purpose register to vector elements (predicated)</a>
  AMED_AARCH64_PAGE_cpy_z_p_v, //!< <a href="../target/aarch64/cpy_z_p_v.html">CPY (SIMD&FP scalar):Copy SIMD&FP scalar register to vector elements (predicated)</a>
  AMED_AARCH64_PAGE_ctermeq_rr, //!< <a href="../target/aarch64/ctermeq_rr.html">CTERMEQ, CTERMNE:Compare and terminate loop</a>
  AMED_AARCH64_PAGE_decb_r_rs, //!< <a href="../target/aarch64/decb_r_rs.html">DECB, DECD, DECH, DECW (scalar):Decrement scalar by multiple of predicate constraint element count</a>
  AMED_AARCH64_PAGE_decd_z_zs, //!< <a href="../target/aarch64/decd_z_zs.html">DECD, DECH, DECW (vector):Decrement vector by multiple of predicate constraint element count</a>
  AMED_AARCH64_PAGE_decp_r_p_r, //!< <a href="../target/aarch64/decp_r_p_r.html">DECP (scalar):Decrement scalar by count of true predicate elements</a>
  AMED_AARCH64_PAGE_decp_z_p_z, //!< <a href="../target/aarch64/decp_z_p_z.html">DECP (vector):Decrement vector by count of true predicate elements</a>
  AMED_AARCH64_PAGE_dup_z_i, //!< <a href="../target/aarch64/dup_z_i.html">DUP (immediate):Broadcast signed immediate to vector elements (unpredicated)</a>
  AMED_AARCH64_PAGE_dup_z_r, //!< <a href="../target/aarch64/dup_z_r.html">DUP (scalar):Broadcast general-purpose register to vector elements (unpredicated)</a>
  AMED_AARCH64_PAGE_dup_z_zi, //!< <a href="../target/aarch64/dup_z_zi.html">DUP (indexed):Broadcast indexed element to vector (unpredicated)</a>
  AMED_AARCH64_PAGE_dupm_z_i, //!< <a href="../target/aarch64/dupm_z_i.html">DUPM:Broadcast logical bitmask immediate to vector (unpredicated)</a>
  AMED_AARCH64_PAGE_eor3_z_zzz, //!< <a href="../target/aarch64/eor3_z_zzz.html">EOR3:Bitwise exclusive OR of three vectors</a>
  AMED_AARCH64_PAGE_eor_p_p_pp, //!< <a href="../target/aarch64/eor_p_p_pp.html">EOR, EORS (predicates):Bitwise exclusive OR predicates</a>
  AMED_AARCH64_PAGE_eor_z_p_zz, //!< <a href="../target/aarch64/eor_z_p_zz.html">EOR (vectors, predicated):Bitwise exclusive OR vectors (predicated)</a>
  AMED_AARCH64_PAGE_eor_z_zi, //!< <a href="../target/aarch64/eor_z_zi.html">EOR (immediate):Bitwise exclusive OR with immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_eor_z_zz, //!< <a href="../target/aarch64/eor_z_zz.html">EOR (vectors, unpredicated):Bitwise exclusive OR vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_eorbt_z_zz, //!< <a href="../target/aarch64/eorbt_z_zz.html">EORBT:Interleaving exclusive OR (bottom, top)</a>
  AMED_AARCH64_PAGE_eortb_z_zz, //!< <a href="../target/aarch64/eortb_z_zz.html">EORTB:Interleaving exclusive OR (top, bottom)</a>
  AMED_AARCH64_PAGE_eorv_r_p_z, //!< <a href="../target/aarch64/eorv_r_p_z.html">EORV:Bitwise exclusive OR reduction to scalar</a>
  AMED_AARCH64_PAGE_ext_z_zi, //!< <a href="../target/aarch64/ext_z_zi.html">EXT:Extract vector from pair of vectors</a>
  AMED_AARCH64_PAGE_fabd_z_p_zz, //!< <a href="../target/aarch64/fabd_z_p_zz.html">FABD:Floating-point absolute difference (predicated)</a>
  AMED_AARCH64_PAGE_fabs_z_p_z, //!< <a href="../target/aarch64/fabs_z_p_z.html">FABS:Floating-point absolute value (predicated)</a>
  AMED_AARCH64_PAGE_facge_p_p_zz, //!< <a href="../target/aarch64/facge_p_p_zz.html">FAC<cc>:Floating-point absolute compare vectors</a>
  AMED_AARCH64_PAGE_fadd_z_p_zs, //!< <a href="../target/aarch64/fadd_z_p_zs.html">FADD (immediate):Floating-point add immediate (predicated)</a>
  AMED_AARCH64_PAGE_fadd_z_p_zz, //!< <a href="../target/aarch64/fadd_z_p_zz.html">FADD (vectors, predicated):Floating-point add vector (predicated)</a>
  AMED_AARCH64_PAGE_fadd_z_zz, //!< <a href="../target/aarch64/fadd_z_zz.html">FADD (vectors, unpredicated):Floating-point add vector (unpredicated)</a>
  AMED_AARCH64_PAGE_fadda_v_p_z, //!< <a href="../target/aarch64/fadda_v_p_z.html">FADDA:Floating-point add strictly-ordered reduction, accumulating in scalar</a>
  AMED_AARCH64_PAGE_faddp_z_p_zz, //!< <a href="../target/aarch64/faddp_z_p_zz.html">FADDP:Floating-point add pairwise</a>
  AMED_AARCH64_PAGE_faddv_v_p_z, //!< <a href="../target/aarch64/faddv_v_p_z.html">FADDV:Floating-point add recursive reduction to scalar</a>
  AMED_AARCH64_PAGE_fcadd_z_p_zz, //!< <a href="../target/aarch64/fcadd_z_p_zz.html">FCADD:Floating-point complex add with rotate (predicated)</a>
  AMED_AARCH64_PAGE_fcmeq_p_p_z0, //!< <a href="../target/aarch64/fcmeq_p_p_z0.html">FCM<cc> (zero):Floating-point compare vector with zero</a>
  AMED_AARCH64_PAGE_fcmeq_p_p_zz, //!< <a href="../target/aarch64/fcmeq_p_p_zz.html">FCM<cc> (vectors):Floating-point compare vectors</a>
  AMED_AARCH64_PAGE_fcmla_z_p_zzz, //!< <a href="../target/aarch64/fcmla_z_p_zzz.html">FCMLA (vectors):Floating-point complex multiply-add with rotate (predicated)</a>
  AMED_AARCH64_PAGE_fcmla_z_zzzi, //!< <a href="../target/aarch64/fcmla_z_zzzi.html">FCMLA (indexed):Floating-point complex multiply-add by indexed values with rotate</a>
  AMED_AARCH64_PAGE_fcpy_z_p_i, //!< <a href="../target/aarch64/fcpy_z_p_i.html">FCPY:Copy 8-bit floating-point immediate to vector elements (predicated)</a>
  AMED_AARCH64_PAGE_fcvt_z_p_z, //!< <a href="../target/aarch64/fcvt_z_p_z.html">FCVT:Floating-point convert precision (predicated)</a>
  AMED_AARCH64_PAGE_fcvtlt_z_p_z, //!< <a href="../target/aarch64/fcvtlt_z_p_z.html">FCVTLT:Floating-point up convert long (top, predicated)</a>
  AMED_AARCH64_PAGE_fcvtnt_z_p_z, //!< <a href="../target/aarch64/fcvtnt_z_p_z.html">FCVTNT:Floating-point down convert and narrow (top, predicated)</a>
  AMED_AARCH64_PAGE_fcvtx_z_p_z, //!< <a href="../target/aarch64/fcvtx_z_p_z.html">FCVTX:Floating-point down convert, rounding to odd (predicated)</a>
  AMED_AARCH64_PAGE_fcvtxnt_z_p_z, //!< <a href="../target/aarch64/fcvtxnt_z_p_z.html">FCVTXNT:Floating-point down convert, rounding to odd (top, predicated)</a>
  AMED_AARCH64_PAGE_fcvtzs_z_p_z, //!< <a href="../target/aarch64/fcvtzs_z_p_z.html">FCVTZS:Floating-point convert to signed integer, rounding toward zero (predicated)</a>
  AMED_AARCH64_PAGE_fcvtzu_z_p_z, //!< <a href="../target/aarch64/fcvtzu_z_p_z.html">FCVTZU:Floating-point convert to unsigned integer, rounding toward zero (predicated)</a>
  AMED_AARCH64_PAGE_fdiv_z_p_zz, //!< <a href="../target/aarch64/fdiv_z_p_zz.html">FDIV:Floating-point divide by vector (predicated)</a>
  AMED_AARCH64_PAGE_fdivr_z_p_zz, //!< <a href="../target/aarch64/fdivr_z_p_zz.html">FDIVR:Floating-point reversed divide by vector (predicated)</a>
  AMED_AARCH64_PAGE_fdup_z_i, //!< <a href="../target/aarch64/fdup_z_i.html">FDUP:Broadcast 8-bit floating-point immediate to vector elements (unpredicated)</a>
  AMED_AARCH64_PAGE_fexpa_z_z, //!< <a href="../target/aarch64/fexpa_z_z.html">FEXPA:Floating-point exponential accelerator</a>
  AMED_AARCH64_PAGE_flogb_z_p_z, //!< <a href="../target/aarch64/flogb_z_p_z.html">FLOGB:Floating-point base 2 logarithm as integer</a>
  AMED_AARCH64_PAGE_fmad_z_p_zzz, //!< <a href="../target/aarch64/fmad_z_p_zzz.html">FMAD:Floating-point fused multiply-add vectors (predicated), writing multiplicand [Zdn = Za + Zdn * Zm]</a>
  AMED_AARCH64_PAGE_fmax_z_p_zs, //!< <a href="../target/aarch64/fmax_z_p_zs.html">FMAX (immediate):Floating-point maximum with immediate (predicated)</a>
  AMED_AARCH64_PAGE_fmax_z_p_zz, //!< <a href="../target/aarch64/fmax_z_p_zz.html">FMAX (vectors):Floating-point maximum (predicated)</a>
  AMED_AARCH64_PAGE_fmaxnm_z_p_zs, //!< <a href="../target/aarch64/fmaxnm_z_p_zs.html">FMAXNM (immediate):Floating-point maximum number with immediate (predicated)</a>
  AMED_AARCH64_PAGE_fmaxnm_z_p_zz, //!< <a href="../target/aarch64/fmaxnm_z_p_zz.html">FMAXNM (vectors):Floating-point maximum number (predicated)</a>
  AMED_AARCH64_PAGE_fmaxnmp_z_p_zz, //!< <a href="../target/aarch64/fmaxnmp_z_p_zz.html">FMAXNMP:Floating-point maximum number pairwise</a>
  AMED_AARCH64_PAGE_fmaxnmv_v_p_z, //!< <a href="../target/aarch64/fmaxnmv_v_p_z.html">FMAXNMV:Floating-point maximum number recursive reduction to scalar</a>
  AMED_AARCH64_PAGE_fmaxp_z_p_zz, //!< <a href="../target/aarch64/fmaxp_z_p_zz.html">FMAXP:Floating-point maximum pairwise</a>
  AMED_AARCH64_PAGE_fmaxv_v_p_z, //!< <a href="../target/aarch64/fmaxv_v_p_z.html">FMAXV:Floating-point maximum recursive reduction to scalar</a>
  AMED_AARCH64_PAGE_fmin_z_p_zs, //!< <a href="../target/aarch64/fmin_z_p_zs.html">FMIN (immediate):Floating-point minimum with immediate (predicated)</a>
  AMED_AARCH64_PAGE_fmin_z_p_zz, //!< <a href="../target/aarch64/fmin_z_p_zz.html">FMIN (vectors):Floating-point minimum (predicated)</a>
  AMED_AARCH64_PAGE_fminnm_z_p_zs, //!< <a href="../target/aarch64/fminnm_z_p_zs.html">FMINNM (immediate):Floating-point minimum number with immediate (predicated)</a>
  AMED_AARCH64_PAGE_fminnm_z_p_zz, //!< <a href="../target/aarch64/fminnm_z_p_zz.html">FMINNM (vectors):Floating-point minimum number (predicated)</a>
  AMED_AARCH64_PAGE_fminnmp_z_p_zz, //!< <a href="../target/aarch64/fminnmp_z_p_zz.html">FMINNMP:Floating-point minimum number pairwise</a>
  AMED_AARCH64_PAGE_fminnmv_v_p_z, //!< <a href="../target/aarch64/fminnmv_v_p_z.html">FMINNMV:Floating-point minimum number recursive reduction to scalar</a>
  AMED_AARCH64_PAGE_fminp_z_p_zz, //!< <a href="../target/aarch64/fminp_z_p_zz.html">FMINP:Floating-point minimum pairwise</a>
  AMED_AARCH64_PAGE_fminv_v_p_z, //!< <a href="../target/aarch64/fminv_v_p_z.html">FMINV:Floating-point minimum recursive reduction to scalar</a>
  AMED_AARCH64_PAGE_fmla_z_p_zzz, //!< <a href="../target/aarch64/fmla_z_p_zzz.html">FMLA (vectors):Floating-point fused multiply-add vectors (predicated), writing addend [Zda = Zda + Zn * Zm]</a>
  AMED_AARCH64_PAGE_fmla_z_zzzi, //!< <a href="../target/aarch64/fmla_z_zzzi.html">FMLA (indexed):Floating-point fused multiply-add by indexed elements (Zda = Zda + Zn * Zm[indexed])</a>
  AMED_AARCH64_PAGE_fmlalb_z_zzz, //!< <a href="../target/aarch64/fmlalb_z_zzz.html">FMLALB (vectors):Half-precision floating-point multiply-add long to single-precision (bottom)</a>
  AMED_AARCH64_PAGE_fmlalb_z_zzzi, //!< <a href="../target/aarch64/fmlalb_z_zzzi.html">FMLALB (indexed):Half-precision floating-point multiply-add long to single-precision (bottom, indexed)</a>
  AMED_AARCH64_PAGE_fmlalt_z_zzz, //!< <a href="../target/aarch64/fmlalt_z_zzz.html">FMLALT (vectors):Half-precision floating-point multiply-add long to single-precision (top)</a>
  AMED_AARCH64_PAGE_fmlalt_z_zzzi, //!< <a href="../target/aarch64/fmlalt_z_zzzi.html">FMLALT (indexed):Half-precision floating-point multiply-add long to single-precision (top, indexed)</a>
  AMED_AARCH64_PAGE_fmls_z_p_zzz, //!< <a href="../target/aarch64/fmls_z_p_zzz.html">FMLS (vectors):Floating-point fused multiply-subtract vectors (predicated), writing addend [Zda = Zda + -Zn * Zm]</a>
  AMED_AARCH64_PAGE_fmls_z_zzzi, //!< <a href="../target/aarch64/fmls_z_zzzi.html">FMLS (indexed):Floating-point fused multiply-subtract by indexed elements (Zda = Zda + -Zn * Zm[indexed])</a>
  AMED_AARCH64_PAGE_fmlslb_z_zzz, //!< <a href="../target/aarch64/fmlslb_z_zzz.html">FMLSLB (vectors):Half-precision floating-point multiply-subtract long from single-precision (bottom)</a>
  AMED_AARCH64_PAGE_fmlslb_z_zzzi, //!< <a href="../target/aarch64/fmlslb_z_zzzi.html">FMLSLB (indexed):Half-precision floating-point multiply-subtract long from single-precision (bottom, indexed)</a>
  AMED_AARCH64_PAGE_fmlslt_z_zzz, //!< <a href="../target/aarch64/fmlslt_z_zzz.html">FMLSLT (vectors):Half-precision floating-point multiply-subtract long from single-precision (top)</a>
  AMED_AARCH64_PAGE_fmlslt_z_zzzi, //!< <a href="../target/aarch64/fmlslt_z_zzzi.html">FMLSLT (indexed):Half-precision floating-point multiply-subtract long from single-precision (top, indexed)</a>
  AMED_AARCH64_PAGE_fmmla_z_zzz, //!< <a href="../target/aarch64/fmmla_z_zzz.html">FMMLA:Floating-point matrix multiply-accumulate</a>
  AMED_AARCH64_PAGE_fmsb_z_p_zzz, //!< <a href="../target/aarch64/fmsb_z_p_zzz.html">FMSB:Floating-point fused multiply-subtract vectors (predicated), writing multiplicand [Zdn = Za + -Zdn * Zm]</a>
  AMED_AARCH64_PAGE_fmul_z_p_zs, //!< <a href="../target/aarch64/fmul_z_p_zs.html">FMUL (immediate):Floating-point multiply by immediate (predicated)</a>
  AMED_AARCH64_PAGE_fmul_z_p_zz, //!< <a href="../target/aarch64/fmul_z_p_zz.html">FMUL (vectors, predicated):Floating-point multiply vectors (predicated)</a>
  AMED_AARCH64_PAGE_fmul_z_zz, //!< <a href="../target/aarch64/fmul_z_zz.html">FMUL (vectors, unpredicated):Floating-point multiply vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_fmul_z_zzi, //!< <a href="../target/aarch64/fmul_z_zzi.html">FMUL (indexed):Floating-point multiply by indexed elements</a>
  AMED_AARCH64_PAGE_fmulx_z_p_zz, //!< <a href="../target/aarch64/fmulx_z_p_zz.html">FMULX:Floating-point multiply-extended vectors (predicated)</a>
  AMED_AARCH64_PAGE_fneg_z_p_z, //!< <a href="../target/aarch64/fneg_z_p_z.html">FNEG:Floating-point negate (predicated)</a>
  AMED_AARCH64_PAGE_fnmad_z_p_zzz, //!< <a href="../target/aarch64/fnmad_z_p_zzz.html">FNMAD:Floating-point negated fused multiply-add vectors (predicated), writing multiplicand [Zdn = -Za + -Zdn * Zm]</a>
  AMED_AARCH64_PAGE_fnmla_z_p_zzz, //!< <a href="../target/aarch64/fnmla_z_p_zzz.html">FNMLA:Floating-point negated fused multiply-add vectors (predicated), writing addend [Zda = -Zda + -Zn * Zm]</a>
  AMED_AARCH64_PAGE_fnmls_z_p_zzz, //!< <a href="../target/aarch64/fnmls_z_p_zzz.html">FNMLS:Floating-point negated fused multiply-subtract vectors (predicated), writing addend [Zda = -Zda + Zn * Zm]</a>
  AMED_AARCH64_PAGE_fnmsb_z_p_zzz, //!< <a href="../target/aarch64/fnmsb_z_p_zzz.html">FNMSB:Floating-point negated fused multiply-subtract vectors (predicated), writing multiplicand [Zdn = -Za + Zdn * Zm]</a>
  AMED_AARCH64_PAGE_frecpe_z_z, //!< <a href="../target/aarch64/frecpe_z_z.html">FRECPE:Floating-point reciprocal estimate (unpredicated)</a>
  AMED_AARCH64_PAGE_frecps_z_zz, //!< <a href="../target/aarch64/frecps_z_zz.html">FRECPS:Floating-point reciprocal step (unpredicated)</a>
  AMED_AARCH64_PAGE_frecpx_z_p_z, //!< <a href="../target/aarch64/frecpx_z_p_z.html">FRECPX:Floating-point reciprocal exponent (predicated)</a>
  AMED_AARCH64_PAGE_frinta_z_p_z, //!< <a href="../target/aarch64/frinta_z_p_z.html">FRINT<r>:Floating-point round to integral value (predicated)</a>
  AMED_AARCH64_PAGE_frsqrte_z_z, //!< <a href="../target/aarch64/frsqrte_z_z.html">FRSQRTE:Floating-point reciprocal square root estimate (unpredicated)</a>
  AMED_AARCH64_PAGE_frsqrts_z_zz, //!< <a href="../target/aarch64/frsqrts_z_zz.html">FRSQRTS:Floating-point reciprocal square root step (unpredicated)</a>
  AMED_AARCH64_PAGE_fscale_z_p_zz, //!< <a href="../target/aarch64/fscale_z_p_zz.html">FSCALE:Floating-point adjust exponent by vector (predicated)</a>
  AMED_AARCH64_PAGE_fsqrt_z_p_z, //!< <a href="../target/aarch64/fsqrt_z_p_z.html">FSQRT:Floating-point square root (predicated)</a>
  AMED_AARCH64_PAGE_fsub_z_p_zs, //!< <a href="../target/aarch64/fsub_z_p_zs.html">FSUB (immediate):Floating-point subtract immediate (predicated)</a>
  AMED_AARCH64_PAGE_fsub_z_p_zz, //!< <a href="../target/aarch64/fsub_z_p_zz.html">FSUB (vectors, predicated):Floating-point subtract vectors (predicated)</a>
  AMED_AARCH64_PAGE_fsub_z_zz, //!< <a href="../target/aarch64/fsub_z_zz.html">FSUB (vectors, unpredicated):Floating-point subtract vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_fsubr_z_p_zs, //!< <a href="../target/aarch64/fsubr_z_p_zs.html">FSUBR (immediate):Floating-point reversed subtract from immediate (predicated)</a>
  AMED_AARCH64_PAGE_fsubr_z_p_zz, //!< <a href="../target/aarch64/fsubr_z_p_zz.html">FSUBR (vectors):Floating-point reversed subtract vectors (predicated)</a>
  AMED_AARCH64_PAGE_ftmad_z_zzi, //!< <a href="../target/aarch64/ftmad_z_zzi.html">FTMAD:Floating-point trigonometric multiply-add coefficient</a>
  AMED_AARCH64_PAGE_ftsmul_z_zz, //!< <a href="../target/aarch64/ftsmul_z_zz.html">FTSMUL:Floating-point trigonometric starting value</a>
  AMED_AARCH64_PAGE_ftssel_z_zz, //!< <a href="../target/aarch64/ftssel_z_zz.html">FTSSEL:Floating-point trigonometric select coefficient</a>
  AMED_AARCH64_PAGE_histcnt_z_p_zz, //!< <a href="../target/aarch64/histcnt_z_p_zz.html">HISTCNT:Count matching elements in vector</a>
  AMED_AARCH64_PAGE_histseg_z_zz, //!< <a href="../target/aarch64/histseg_z_zz.html">HISTSEG:Count matching elements in vector segments</a>
  AMED_AARCH64_PAGE_incb_r_rs, //!< <a href="../target/aarch64/incb_r_rs.html">INCB, INCD, INCH, INCW (scalar):Increment scalar by multiple of predicate constraint element count</a>
  AMED_AARCH64_PAGE_incd_z_zs, //!< <a href="../target/aarch64/incd_z_zs.html">INCD, INCH, INCW (vector):Increment vector by multiple of predicate constraint element count</a>
  AMED_AARCH64_PAGE_incp_r_p_r, //!< <a href="../target/aarch64/incp_r_p_r.html">INCP (scalar):Increment scalar by count of true predicate elements</a>
  AMED_AARCH64_PAGE_incp_z_p_z, //!< <a href="../target/aarch64/incp_z_p_z.html">INCP (vector):Increment vector by count of true predicate elements</a>
  AMED_AARCH64_PAGE_index_z_ii, //!< <a href="../target/aarch64/index_z_ii.html">INDEX (immediates):Create index starting from and incremented by immediate</a>
  AMED_AARCH64_PAGE_index_z_ir, //!< <a href="../target/aarch64/index_z_ir.html">INDEX (immediate, scalar):Create index starting from immediate and incremented by general-purpose register</a>
  AMED_AARCH64_PAGE_index_z_ri, //!< <a href="../target/aarch64/index_z_ri.html">INDEX (scalar, immediate):Create index starting from general-purpose register and incremented by immediate</a>
  AMED_AARCH64_PAGE_index_z_rr, //!< <a href="../target/aarch64/index_z_rr.html">INDEX (scalars):Create index starting from and incremented by general-purpose register</a>
  AMED_AARCH64_PAGE_insr_z_r, //!< <a href="../target/aarch64/insr_z_r.html">INSR (scalar):Insert general-purpose register in shifted vector</a>
  AMED_AARCH64_PAGE_insr_z_v, //!< <a href="../target/aarch64/insr_z_v.html">INSR (SIMD&FP scalar):Insert SIMD&FP scalar register in shifted vector</a>
  AMED_AARCH64_PAGE_lasta_r_p_z, //!< <a href="../target/aarch64/lasta_r_p_z.html">LASTA (scalar):Extract element after last to general-purpose register</a>
  AMED_AARCH64_PAGE_lasta_v_p_z, //!< <a href="../target/aarch64/lasta_v_p_z.html">LASTA (SIMD&FP scalar):Extract element after last to SIMD&FP scalar register</a>
  AMED_AARCH64_PAGE_lastb_r_p_z, //!< <a href="../target/aarch64/lastb_r_p_z.html">LASTB (scalar):Extract last element to general-purpose register</a>
  AMED_AARCH64_PAGE_lastb_v_p_z, //!< <a href="../target/aarch64/lastb_v_p_z.html">LASTB (SIMD&FP scalar):Extract last element to SIMD&FP scalar register</a>
  AMED_AARCH64_PAGE_ld1b_z_p_ai, //!< <a href="../target/aarch64/ld1b_z_p_ai.html">LD1B (vector plus immediate):Gather load unsigned bytes to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1b_z_p_bi, //!< <a href="../target/aarch64/ld1b_z_p_bi.html">LD1B (scalar plus immediate):Contiguous load unsigned bytes to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1b_z_p_br, //!< <a href="../target/aarch64/ld1b_z_p_br.html">LD1B (scalar plus scalar):Contiguous load unsigned bytes to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ld1b_z_p_bz, //!< <a href="../target/aarch64/ld1b_z_p_bz.html">LD1B (scalar plus vector):Gather load unsigned bytes to vector (vector index)</a>
  AMED_AARCH64_PAGE_ld1d_z_p_ai, //!< <a href="../target/aarch64/ld1d_z_p_ai.html">LD1D (vector plus immediate):Gather load doublewords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1d_z_p_bi, //!< <a href="../target/aarch64/ld1d_z_p_bi.html">LD1D (scalar plus immediate):Contiguous load doublewords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1d_z_p_br, //!< <a href="../target/aarch64/ld1d_z_p_br.html">LD1D (scalar plus scalar):Contiguous load doublewords to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ld1d_z_p_bz, //!< <a href="../target/aarch64/ld1d_z_p_bz.html">LD1D (scalar plus vector):Gather load doublewords to vector (vector index)</a>
  AMED_AARCH64_PAGE_ld1h_z_p_ai, //!< <a href="../target/aarch64/ld1h_z_p_ai.html">LD1H (vector plus immediate):Gather load unsigned halfwords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1h_z_p_bi, //!< <a href="../target/aarch64/ld1h_z_p_bi.html">LD1H (scalar plus immediate):Contiguous load unsigned halfwords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1h_z_p_br, //!< <a href="../target/aarch64/ld1h_z_p_br.html">LD1H (scalar plus scalar):Contiguous load unsigned halfwords to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ld1h_z_p_bz, //!< <a href="../target/aarch64/ld1h_z_p_bz.html">LD1H (scalar plus vector):Gather load unsigned halfwords to vector (vector index)</a>
  AMED_AARCH64_PAGE_ld1rb_z_p_bi, //!< <a href="../target/aarch64/ld1rb_z_p_bi.html">LD1RB:Load and broadcast unsigned byte to vector</a>
  AMED_AARCH64_PAGE_ld1rd_z_p_bi, //!< <a href="../target/aarch64/ld1rd_z_p_bi.html">LD1RD:Load and broadcast doubleword to vector</a>
  AMED_AARCH64_PAGE_ld1rh_z_p_bi, //!< <a href="../target/aarch64/ld1rh_z_p_bi.html">LD1RH:Load and broadcast unsigned halfword to vector</a>
  AMED_AARCH64_PAGE_ld1rob_z_p_bi, //!< <a href="../target/aarch64/ld1rob_z_p_bi.html">LD1ROB (scalar plus immediate):Contiguous load and replicate thirty-two bytes (immediate index)</a>
  AMED_AARCH64_PAGE_ld1rob_z_p_br, //!< <a href="../target/aarch64/ld1rob_z_p_br.html">LD1ROB (scalar plus scalar):Contiguous load and replicate thirty-two bytes (scalar index)</a>
  AMED_AARCH64_PAGE_ld1rod_z_p_bi, //!< <a href="../target/aarch64/ld1rod_z_p_bi.html">LD1ROD (scalar plus immediate):Contiguous load and replicate four doublewords (immediate index)</a>
  AMED_AARCH64_PAGE_ld1rod_z_p_br, //!< <a href="../target/aarch64/ld1rod_z_p_br.html">LD1ROD (scalar plus scalar):Contiguous load and replicate four doublewords (scalar index)</a>
  AMED_AARCH64_PAGE_ld1roh_z_p_bi, //!< <a href="../target/aarch64/ld1roh_z_p_bi.html">LD1ROH (scalar plus immediate):Contiguous load and replicate sixteen halfwords (immediate index)</a>
  AMED_AARCH64_PAGE_ld1roh_z_p_br, //!< <a href="../target/aarch64/ld1roh_z_p_br.html">LD1ROH (scalar plus scalar):Contiguous load and replicate sixteen halfwords (scalar index)</a>
  AMED_AARCH64_PAGE_ld1row_z_p_bi, //!< <a href="../target/aarch64/ld1row_z_p_bi.html">LD1ROW (scalar plus immediate):Contiguous load and replicate eight words (immediate index)</a>
  AMED_AARCH64_PAGE_ld1row_z_p_br, //!< <a href="../target/aarch64/ld1row_z_p_br.html">LD1ROW (scalar plus scalar):Contiguous load and replicate eight words (scalar index)</a>
  AMED_AARCH64_PAGE_ld1rqb_z_p_bi, //!< <a href="../target/aarch64/ld1rqb_z_p_bi.html">LD1RQB (scalar plus immediate):Contiguous load and replicate sixteen bytes (immediate index)</a>
  AMED_AARCH64_PAGE_ld1rqb_z_p_br, //!< <a href="../target/aarch64/ld1rqb_z_p_br.html">LD1RQB (scalar plus scalar):Contiguous load and replicate sixteen bytes (scalar index)</a>
  AMED_AARCH64_PAGE_ld1rqd_z_p_bi, //!< <a href="../target/aarch64/ld1rqd_z_p_bi.html">LD1RQD (scalar plus immediate):Contiguous load and replicate two doublewords (immediate index)</a>
  AMED_AARCH64_PAGE_ld1rqd_z_p_br, //!< <a href="../target/aarch64/ld1rqd_z_p_br.html">LD1RQD (scalar plus scalar):Contiguous load and replicate two doublewords (scalar index)</a>
  AMED_AARCH64_PAGE_ld1rqh_z_p_bi, //!< <a href="../target/aarch64/ld1rqh_z_p_bi.html">LD1RQH (scalar plus immediate):Contiguous load and replicate eight halfwords (immediate index)</a>
  AMED_AARCH64_PAGE_ld1rqh_z_p_br, //!< <a href="../target/aarch64/ld1rqh_z_p_br.html">LD1RQH (scalar plus scalar):Contiguous load and replicate eight halfwords (scalar index)</a>
  AMED_AARCH64_PAGE_ld1rqw_z_p_bi, //!< <a href="../target/aarch64/ld1rqw_z_p_bi.html">LD1RQW (scalar plus immediate):Contiguous load and replicate four words (immediate index)</a>
  AMED_AARCH64_PAGE_ld1rqw_z_p_br, //!< <a href="../target/aarch64/ld1rqw_z_p_br.html">LD1RQW (scalar plus scalar):Contiguous load and replicate four words (scalar index)</a>
  AMED_AARCH64_PAGE_ld1rsb_z_p_bi, //!< <a href="../target/aarch64/ld1rsb_z_p_bi.html">LD1RSB:Load and broadcast signed byte to vector</a>
  AMED_AARCH64_PAGE_ld1rsh_z_p_bi, //!< <a href="../target/aarch64/ld1rsh_z_p_bi.html">LD1RSH:Load and broadcast signed halfword to vector</a>
  AMED_AARCH64_PAGE_ld1rsw_z_p_bi, //!< <a href="../target/aarch64/ld1rsw_z_p_bi.html">LD1RSW:Load and broadcast signed word to vector</a>
  AMED_AARCH64_PAGE_ld1rw_z_p_bi, //!< <a href="../target/aarch64/ld1rw_z_p_bi.html">LD1RW:Load and broadcast unsigned word to vector</a>
  AMED_AARCH64_PAGE_ld1sb_z_p_ai, //!< <a href="../target/aarch64/ld1sb_z_p_ai.html">LD1SB (vector plus immediate):Gather load signed bytes to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1sb_z_p_bi, //!< <a href="../target/aarch64/ld1sb_z_p_bi.html">LD1SB (scalar plus immediate):Contiguous load signed bytes to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1sb_z_p_br, //!< <a href="../target/aarch64/ld1sb_z_p_br.html">LD1SB (scalar plus scalar):Contiguous load signed bytes to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ld1sb_z_p_bz, //!< <a href="../target/aarch64/ld1sb_z_p_bz.html">LD1SB (scalar plus vector):Gather load signed bytes to vector (vector index)</a>
  AMED_AARCH64_PAGE_ld1sh_z_p_ai, //!< <a href="../target/aarch64/ld1sh_z_p_ai.html">LD1SH (vector plus immediate):Gather load signed halfwords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1sh_z_p_bi, //!< <a href="../target/aarch64/ld1sh_z_p_bi.html">LD1SH (scalar plus immediate):Contiguous load signed halfwords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1sh_z_p_br, //!< <a href="../target/aarch64/ld1sh_z_p_br.html">LD1SH (scalar plus scalar):Contiguous load signed halfwords to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ld1sh_z_p_bz, //!< <a href="../target/aarch64/ld1sh_z_p_bz.html">LD1SH (scalar plus vector):Gather load signed halfwords to vector (vector index)</a>
  AMED_AARCH64_PAGE_ld1sw_z_p_ai, //!< <a href="../target/aarch64/ld1sw_z_p_ai.html">LD1SW (vector plus immediate):Gather load signed words to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1sw_z_p_bi, //!< <a href="../target/aarch64/ld1sw_z_p_bi.html">LD1SW (scalar plus immediate):Contiguous load signed words to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1sw_z_p_br, //!< <a href="../target/aarch64/ld1sw_z_p_br.html">LD1SW (scalar plus scalar):Contiguous load signed words to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ld1sw_z_p_bz, //!< <a href="../target/aarch64/ld1sw_z_p_bz.html">LD1SW (scalar plus vector):Gather load signed words to vector (vector index)</a>
  AMED_AARCH64_PAGE_ld1w_z_p_ai, //!< <a href="../target/aarch64/ld1w_z_p_ai.html">LD1W (vector plus immediate):Gather load unsigned words to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1w_z_p_bi, //!< <a href="../target/aarch64/ld1w_z_p_bi.html">LD1W (scalar plus immediate):Contiguous load unsigned words to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ld1w_z_p_br, //!< <a href="../target/aarch64/ld1w_z_p_br.html">LD1W (scalar plus scalar):Contiguous load unsigned words to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ld1w_z_p_bz, //!< <a href="../target/aarch64/ld1w_z_p_bz.html">LD1W (scalar plus vector):Gather load unsigned words to vector (vector index)</a>
  AMED_AARCH64_PAGE_ld2b_z_p_bi, //!< <a href="../target/aarch64/ld2b_z_p_bi.html">LD2B (scalar plus immediate):Contiguous load two-byte structures to two vectors (immediate index)</a>
  AMED_AARCH64_PAGE_ld2b_z_p_br, //!< <a href="../target/aarch64/ld2b_z_p_br.html">LD2B (scalar plus scalar):Contiguous load two-byte structures to two vectors (scalar index)</a>
  AMED_AARCH64_PAGE_ld2d_z_p_bi, //!< <a href="../target/aarch64/ld2d_z_p_bi.html">LD2D (scalar plus immediate):Contiguous load two-doubleword structures to two vectors (immediate index)</a>
  AMED_AARCH64_PAGE_ld2d_z_p_br, //!< <a href="../target/aarch64/ld2d_z_p_br.html">LD2D (scalar plus scalar):Contiguous load two-doubleword structures to two vectors (scalar index)</a>
  AMED_AARCH64_PAGE_ld2h_z_p_bi, //!< <a href="../target/aarch64/ld2h_z_p_bi.html">LD2H (scalar plus immediate):Contiguous load two-halfword structures to two vectors (immediate index)</a>
  AMED_AARCH64_PAGE_ld2h_z_p_br, //!< <a href="../target/aarch64/ld2h_z_p_br.html">LD2H (scalar plus scalar):Contiguous load two-halfword structures to two vectors (scalar index)</a>
  AMED_AARCH64_PAGE_ld2w_z_p_bi, //!< <a href="../target/aarch64/ld2w_z_p_bi.html">LD2W (scalar plus immediate):Contiguous load two-word structures to two vectors (immediate index)</a>
  AMED_AARCH64_PAGE_ld2w_z_p_br, //!< <a href="../target/aarch64/ld2w_z_p_br.html">LD2W (scalar plus scalar):Contiguous load two-word structures to two vectors (scalar index)</a>
  AMED_AARCH64_PAGE_ld3b_z_p_bi, //!< <a href="../target/aarch64/ld3b_z_p_bi.html">LD3B (scalar plus immediate):Contiguous load three-byte structures to three vectors (immediate index)</a>
  AMED_AARCH64_PAGE_ld3b_z_p_br, //!< <a href="../target/aarch64/ld3b_z_p_br.html">LD3B (scalar plus scalar):Contiguous load three-byte structures to three vectors (scalar index)</a>
  AMED_AARCH64_PAGE_ld3d_z_p_bi, //!< <a href="../target/aarch64/ld3d_z_p_bi.html">LD3D (scalar plus immediate):Contiguous load three-doubleword structures to three vectors (immediate index)</a>
  AMED_AARCH64_PAGE_ld3d_z_p_br, //!< <a href="../target/aarch64/ld3d_z_p_br.html">LD3D (scalar plus scalar):Contiguous load three-doubleword structures to three vectors (scalar index)</a>
  AMED_AARCH64_PAGE_ld3h_z_p_bi, //!< <a href="../target/aarch64/ld3h_z_p_bi.html">LD3H (scalar plus immediate):Contiguous load three-halfword structures to three vectors (immediate index)</a>
  AMED_AARCH64_PAGE_ld3h_z_p_br, //!< <a href="../target/aarch64/ld3h_z_p_br.html">LD3H (scalar plus scalar):Contiguous load three-halfword structures to three vectors (scalar index)</a>
  AMED_AARCH64_PAGE_ld3w_z_p_bi, //!< <a href="../target/aarch64/ld3w_z_p_bi.html">LD3W (scalar plus immediate):Contiguous load three-word structures to three vectors (immediate index)</a>
  AMED_AARCH64_PAGE_ld3w_z_p_br, //!< <a href="../target/aarch64/ld3w_z_p_br.html">LD3W (scalar plus scalar):Contiguous load three-word structures to three vectors (scalar index)</a>
  AMED_AARCH64_PAGE_ld4b_z_p_bi, //!< <a href="../target/aarch64/ld4b_z_p_bi.html">LD4B (scalar plus immediate):Contiguous load four-byte structures to four vectors (immediate index)</a>
  AMED_AARCH64_PAGE_ld4b_z_p_br, //!< <a href="../target/aarch64/ld4b_z_p_br.html">LD4B (scalar plus scalar):Contiguous load four-byte structures to four vectors (scalar index)</a>
  AMED_AARCH64_PAGE_ld4d_z_p_bi, //!< <a href="../target/aarch64/ld4d_z_p_bi.html">LD4D (scalar plus immediate):Contiguous load four-doubleword structures to four vectors (immediate index)</a>
  AMED_AARCH64_PAGE_ld4d_z_p_br, //!< <a href="../target/aarch64/ld4d_z_p_br.html">LD4D (scalar plus scalar):Contiguous load four-doubleword structures to four vectors (scalar index)</a>
  AMED_AARCH64_PAGE_ld4h_z_p_bi, //!< <a href="../target/aarch64/ld4h_z_p_bi.html">LD4H (scalar plus immediate):Contiguous load four-halfword structures to four vectors (immediate index)</a>
  AMED_AARCH64_PAGE_ld4h_z_p_br, //!< <a href="../target/aarch64/ld4h_z_p_br.html">LD4H (scalar plus scalar):Contiguous load four-halfword structures to four vectors (scalar index)</a>
  AMED_AARCH64_PAGE_ld4w_z_p_bi, //!< <a href="../target/aarch64/ld4w_z_p_bi.html">LD4W (scalar plus immediate):Contiguous load four-word structures to four vectors (immediate index)</a>
  AMED_AARCH64_PAGE_ld4w_z_p_br, //!< <a href="../target/aarch64/ld4w_z_p_br.html">LD4W (scalar plus scalar):Contiguous load four-word structures to four vectors (scalar index)</a>
  AMED_AARCH64_PAGE_ldff1b_z_p_ai, //!< <a href="../target/aarch64/ldff1b_z_p_ai.html">LDFF1B (vector plus immediate):Gather load first-fault unsigned bytes to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldff1b_z_p_br, //!< <a href="../target/aarch64/ldff1b_z_p_br.html">LDFF1B (scalar plus scalar):Contiguous load first-fault unsigned bytes to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ldff1b_z_p_bz, //!< <a href="../target/aarch64/ldff1b_z_p_bz.html">LDFF1B (scalar plus vector):Gather load first-fault unsigned bytes to vector (vector index)</a>
  AMED_AARCH64_PAGE_ldff1d_z_p_ai, //!< <a href="../target/aarch64/ldff1d_z_p_ai.html">LDFF1D (vector plus immediate):Gather load first-fault doublewords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldff1d_z_p_br, //!< <a href="../target/aarch64/ldff1d_z_p_br.html">LDFF1D (scalar plus scalar):Contiguous load first-fault doublewords to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ldff1d_z_p_bz, //!< <a href="../target/aarch64/ldff1d_z_p_bz.html">LDFF1D (scalar plus vector):Gather load first-fault doublewords to vector (vector index)</a>
  AMED_AARCH64_PAGE_ldff1h_z_p_ai, //!< <a href="../target/aarch64/ldff1h_z_p_ai.html">LDFF1H (vector plus immediate):Gather load first-fault unsigned halfwords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldff1h_z_p_br, //!< <a href="../target/aarch64/ldff1h_z_p_br.html">LDFF1H (scalar plus scalar):Contiguous load first-fault unsigned halfwords to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ldff1h_z_p_bz, //!< <a href="../target/aarch64/ldff1h_z_p_bz.html">LDFF1H (scalar plus vector):Gather load first-fault unsigned halfwords to vector (vector index)</a>
  AMED_AARCH64_PAGE_ldff1sb_z_p_ai, //!< <a href="../target/aarch64/ldff1sb_z_p_ai.html">LDFF1SB (vector plus immediate):Gather load first-fault signed bytes to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldff1sb_z_p_br, //!< <a href="../target/aarch64/ldff1sb_z_p_br.html">LDFF1SB (scalar plus scalar):Contiguous load first-fault signed bytes to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ldff1sb_z_p_bz, //!< <a href="../target/aarch64/ldff1sb_z_p_bz.html">LDFF1SB (scalar plus vector):Gather load first-fault signed bytes to vector (vector index)</a>
  AMED_AARCH64_PAGE_ldff1sh_z_p_ai, //!< <a href="../target/aarch64/ldff1sh_z_p_ai.html">LDFF1SH (vector plus immediate):Gather load first-fault signed halfwords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldff1sh_z_p_br, //!< <a href="../target/aarch64/ldff1sh_z_p_br.html">LDFF1SH (scalar plus scalar):Contiguous load first-fault signed halfwords to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ldff1sh_z_p_bz, //!< <a href="../target/aarch64/ldff1sh_z_p_bz.html">LDFF1SH (scalar plus vector):Gather load first-fault signed halfwords to vector (vector index)</a>
  AMED_AARCH64_PAGE_ldff1sw_z_p_ai, //!< <a href="../target/aarch64/ldff1sw_z_p_ai.html">LDFF1SW (vector plus immediate):Gather load first-fault signed words to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldff1sw_z_p_br, //!< <a href="../target/aarch64/ldff1sw_z_p_br.html">LDFF1SW (scalar plus scalar):Contiguous load first-fault signed words to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ldff1sw_z_p_bz, //!< <a href="../target/aarch64/ldff1sw_z_p_bz.html">LDFF1SW (scalar plus vector):Gather load first-fault signed words to vector (vector index)</a>
  AMED_AARCH64_PAGE_ldff1w_z_p_ai, //!< <a href="../target/aarch64/ldff1w_z_p_ai.html">LDFF1W (vector plus immediate):Gather load first-fault unsigned words to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldff1w_z_p_br, //!< <a href="../target/aarch64/ldff1w_z_p_br.html">LDFF1W (scalar plus scalar):Contiguous load first-fault unsigned words to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ldff1w_z_p_bz, //!< <a href="../target/aarch64/ldff1w_z_p_bz.html">LDFF1W (scalar plus vector):Gather load first-fault unsigned words to vector (vector index)</a>
  AMED_AARCH64_PAGE_ldnf1b_z_p_bi, //!< <a href="../target/aarch64/ldnf1b_z_p_bi.html">LDNF1B:Contiguous load non-fault unsigned bytes to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldnf1d_z_p_bi, //!< <a href="../target/aarch64/ldnf1d_z_p_bi.html">LDNF1D:Contiguous load non-fault doublewords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldnf1h_z_p_bi, //!< <a href="../target/aarch64/ldnf1h_z_p_bi.html">LDNF1H:Contiguous load non-fault unsigned halfwords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldnf1sb_z_p_bi, //!< <a href="../target/aarch64/ldnf1sb_z_p_bi.html">LDNF1SB:Contiguous load non-fault signed bytes to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldnf1sh_z_p_bi, //!< <a href="../target/aarch64/ldnf1sh_z_p_bi.html">LDNF1SH:Contiguous load non-fault signed halfwords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldnf1sw_z_p_bi, //!< <a href="../target/aarch64/ldnf1sw_z_p_bi.html">LDNF1SW:Contiguous load non-fault signed words to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldnf1w_z_p_bi, //!< <a href="../target/aarch64/ldnf1w_z_p_bi.html">LDNF1W:Contiguous load non-fault unsigned words to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldnt1b_z_p_ar, //!< <a href="../target/aarch64/ldnt1b_z_p_ar.html">LDNT1B (vector plus scalar):Gather load non-temporal unsigned bytes</a>
  AMED_AARCH64_PAGE_ldnt1b_z_p_bi, //!< <a href="../target/aarch64/ldnt1b_z_p_bi.html">LDNT1B (scalar plus immediate):Contiguous load non-temporal bytes to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldnt1b_z_p_br, //!< <a href="../target/aarch64/ldnt1b_z_p_br.html">LDNT1B (scalar plus scalar):Contiguous load non-temporal bytes to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ldnt1d_z_p_ar, //!< <a href="../target/aarch64/ldnt1d_z_p_ar.html">LDNT1D (vector plus scalar):Gather load non-temporal unsigned doublewords</a>
  AMED_AARCH64_PAGE_ldnt1d_z_p_bi, //!< <a href="../target/aarch64/ldnt1d_z_p_bi.html">LDNT1D (scalar plus immediate):Contiguous load non-temporal doublewords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldnt1d_z_p_br, //!< <a href="../target/aarch64/ldnt1d_z_p_br.html">LDNT1D (scalar plus scalar):Contiguous load non-temporal doublewords to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ldnt1h_z_p_ar, //!< <a href="../target/aarch64/ldnt1h_z_p_ar.html">LDNT1H (vector plus scalar):Gather load non-temporal unsigned halfwords</a>
  AMED_AARCH64_PAGE_ldnt1h_z_p_bi, //!< <a href="../target/aarch64/ldnt1h_z_p_bi.html">LDNT1H (scalar plus immediate):Contiguous load non-temporal halfwords to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldnt1h_z_p_br, //!< <a href="../target/aarch64/ldnt1h_z_p_br.html">LDNT1H (scalar plus scalar):Contiguous load non-temporal halfwords to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ldnt1sb_z_p_ar, //!< <a href="../target/aarch64/ldnt1sb_z_p_ar.html">LDNT1SB:Gather load non-temporal signed bytes</a>
  AMED_AARCH64_PAGE_ldnt1sh_z_p_ar, //!< <a href="../target/aarch64/ldnt1sh_z_p_ar.html">LDNT1SH:Gather load non-temporal signed halfwords</a>
  AMED_AARCH64_PAGE_ldnt1sw_z_p_ar, //!< <a href="../target/aarch64/ldnt1sw_z_p_ar.html">LDNT1SW:Gather load non-temporal signed words</a>
  AMED_AARCH64_PAGE_ldnt1w_z_p_ar, //!< <a href="../target/aarch64/ldnt1w_z_p_ar.html">LDNT1W (vector plus scalar):Gather load non-temporal unsigned words</a>
  AMED_AARCH64_PAGE_ldnt1w_z_p_bi, //!< <a href="../target/aarch64/ldnt1w_z_p_bi.html">LDNT1W (scalar plus immediate):Contiguous load non-temporal words to vector (immediate index)</a>
  AMED_AARCH64_PAGE_ldnt1w_z_p_br, //!< <a href="../target/aarch64/ldnt1w_z_p_br.html">LDNT1W (scalar plus scalar):Contiguous load non-temporal words to vector (scalar index)</a>
  AMED_AARCH64_PAGE_ldr_p_bi, //!< <a href="../target/aarch64/ldr_p_bi.html">LDR (predicate):Load predicate register</a>
  AMED_AARCH64_PAGE_ldr_z_bi, //!< <a href="../target/aarch64/ldr_z_bi.html">LDR (vector):Load vector register</a>
  AMED_AARCH64_PAGE_lsl_z_p_zi, //!< <a href="../target/aarch64/lsl_z_p_zi.html">LSL (immediate, predicated):Logical shift left by immediate (predicated)</a>
  AMED_AARCH64_PAGE_lsl_z_p_zw, //!< <a href="../target/aarch64/lsl_z_p_zw.html">LSL (wide elements, predicated):Logical shift left by 64-bit wide elements (predicated)</a>
  AMED_AARCH64_PAGE_lsl_z_p_zz, //!< <a href="../target/aarch64/lsl_z_p_zz.html">LSL (vectors):Logical shift left by vector (predicated)</a>
  AMED_AARCH64_PAGE_lsl_z_zi, //!< <a href="../target/aarch64/lsl_z_zi.html">LSL (immediate, unpredicated):Logical shift left by immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_lsl_z_zw, //!< <a href="../target/aarch64/lsl_z_zw.html">LSL (wide elements, unpredicated):Logical shift left by 64-bit wide elements (unpredicated)</a>
  AMED_AARCH64_PAGE_lslr_z_p_zz, //!< <a href="../target/aarch64/lslr_z_p_zz.html">LSLR:Reversed logical shift left by vector (predicated)</a>
  AMED_AARCH64_PAGE_lsr_z_p_zi, //!< <a href="../target/aarch64/lsr_z_p_zi.html">LSR (immediate, predicated):Logical shift right by immediate (predicated)</a>
  AMED_AARCH64_PAGE_lsr_z_p_zw, //!< <a href="../target/aarch64/lsr_z_p_zw.html">LSR (wide elements, predicated):Logical shift right by 64-bit wide elements (predicated)</a>
  AMED_AARCH64_PAGE_lsr_z_p_zz, //!< <a href="../target/aarch64/lsr_z_p_zz.html">LSR (vectors):Logical shift right by vector (predicated)</a>
  AMED_AARCH64_PAGE_lsr_z_zi, //!< <a href="../target/aarch64/lsr_z_zi.html">LSR (immediate, unpredicated):Logical shift right by immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_lsr_z_zw, //!< <a href="../target/aarch64/lsr_z_zw.html">LSR (wide elements, unpredicated):Logical shift right by 64-bit wide elements (unpredicated)</a>
  AMED_AARCH64_PAGE_lsrr_z_p_zz, //!< <a href="../target/aarch64/lsrr_z_p_zz.html">LSRR:Reversed logical shift right by vector (predicated)</a>
  AMED_AARCH64_PAGE_mad_z_p_zzz, //!< <a href="../target/aarch64/mad_z_p_zzz.html">MAD:Multiply-add vectors (predicated), writing multiplicand [Zdn = Za + Zdn * Zm]</a>
  AMED_AARCH64_PAGE_match_p_p_zz, //!< <a href="../target/aarch64/match_p_p_zz.html">MATCH:Detect any matching elements, setting the condition flags</a>
  AMED_AARCH64_PAGE_mla_z_p_zzz, //!< <a href="../target/aarch64/mla_z_p_zzz.html">MLA (vectors):Multiply-add vectors (predicated), writing addend [Zda = Zda + Zn * Zm]</a>
  AMED_AARCH64_PAGE_mla_z_zzzi, //!< <a href="../target/aarch64/mla_z_zzzi.html">MLA (indexed):Multiply-add to accumulator (indexed)</a>
  AMED_AARCH64_PAGE_mls_z_p_zzz, //!< <a href="../target/aarch64/mls_z_p_zzz.html">MLS (vectors):Multiply-subtract vectors (predicated), writing addend [Zda = Zda - Zn * Zm]</a>
  AMED_AARCH64_PAGE_mls_z_zzzi, //!< <a href="../target/aarch64/mls_z_zzzi.html">MLS (indexed):Multiply-subtract from accumulator (indexed)</a>
  AMED_AARCH64_PAGE_movprfx_z_p_z, //!< <a href="../target/aarch64/movprfx_z_p_z.html">MOVPRFX (predicated):Move prefix (predicated)</a>
  AMED_AARCH64_PAGE_movprfx_z_z, //!< <a href="../target/aarch64/movprfx_z_z.html">MOVPRFX (unpredicated):Move prefix (unpredicated)</a>
  AMED_AARCH64_PAGE_msb_z_p_zzz, //!< <a href="../target/aarch64/msb_z_p_zzz.html">MSB:Multiply-subtract vectors (predicated), writing multiplicand [Zdn = Za - Zdn * Zm]</a>
  AMED_AARCH64_PAGE_mul_z_p_zz, //!< <a href="../target/aarch64/mul_z_p_zz.html">MUL (vectors, predicated):Multiply vectors (predicated)</a>
  AMED_AARCH64_PAGE_mul_z_zi, //!< <a href="../target/aarch64/mul_z_zi.html">MUL (immediate):Multiply by immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_mul_z_zz, //!< <a href="../target/aarch64/mul_z_zz.html">MUL (vectors, unpredicated):Multiply vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_mul_z_zzi, //!< <a href="../target/aarch64/mul_z_zzi.html">MUL (indexed):Multiply (indexed)</a>
  AMED_AARCH64_PAGE_nand_p_p_pp, //!< <a href="../target/aarch64/nand_p_p_pp.html">NAND, NANDS:Bitwise NAND predicates</a>
  AMED_AARCH64_PAGE_nbsl_z_zzz, //!< <a href="../target/aarch64/nbsl_z_zzz.html">NBSL:Bitwise inverted select</a>
  AMED_AARCH64_PAGE_neg_z_p_z, //!< <a href="../target/aarch64/neg_z_p_z.html">NEG:Negate (predicated)</a>
  AMED_AARCH64_PAGE_nmatch_p_p_zz, //!< <a href="../target/aarch64/nmatch_p_p_zz.html">NMATCH:Detect no matching elements, setting the condition flags</a>
  AMED_AARCH64_PAGE_nor_p_p_pp, //!< <a href="../target/aarch64/nor_p_p_pp.html">NOR, NORS:Bitwise NOR predicates</a>
  AMED_AARCH64_PAGE_not_z_p_z, //!< <a href="../target/aarch64/not_z_p_z.html">NOT (vector):Bitwise invert vector (predicated)</a>
  AMED_AARCH64_PAGE_orn_p_p_pp, //!< <a href="../target/aarch64/orn_p_p_pp.html">ORN, ORNS (predicates):Bitwise inclusive OR inverted predicate</a>
  AMED_AARCH64_PAGE_orr_p_p_pp, //!< <a href="../target/aarch64/orr_p_p_pp.html">ORR, ORRS (predicates):Bitwise inclusive OR predicate</a>
  AMED_AARCH64_PAGE_orr_z_p_zz, //!< <a href="../target/aarch64/orr_z_p_zz.html">ORR (vectors, predicated):Bitwise inclusive OR vectors (predicated)</a>
  AMED_AARCH64_PAGE_orr_z_zi, //!< <a href="../target/aarch64/orr_z_zi.html">ORR (immediate):Bitwise inclusive OR with immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_orr_z_zz, //!< <a href="../target/aarch64/orr_z_zz.html">ORR (vectors, unpredicated):Bitwise inclusive OR vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_orv_r_p_z, //!< <a href="../target/aarch64/orv_r_p_z.html">ORV:Bitwise inclusive OR reduction to scalar</a>
  AMED_AARCH64_PAGE_pfalse_p, //!< <a href="../target/aarch64/pfalse_p.html">PFALSE:Set all predicate elements to false</a>
  AMED_AARCH64_PAGE_pfirst_p_p_p, //!< <a href="../target/aarch64/pfirst_p_p_p.html">PFIRST:Set the first active predicate element to true</a>
  AMED_AARCH64_PAGE_pmul_z_zz, //!< <a href="../target/aarch64/pmul_z_zz.html">PMUL:Polynomial multiply vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_pmullb_z_zz, //!< <a href="../target/aarch64/pmullb_z_zz.html">PMULLB:Polynomial multiply long (bottom)</a>
  AMED_AARCH64_PAGE_pmullt_z_zz, //!< <a href="../target/aarch64/pmullt_z_zz.html">PMULLT:Polynomial multiply long (top)</a>
  AMED_AARCH64_PAGE_pnext_p_p_p, //!< <a href="../target/aarch64/pnext_p_p_p.html">PNEXT:Find next active predicate</a>
  AMED_AARCH64_PAGE_prfb_i_p_ai, //!< <a href="../target/aarch64/prfb_i_p_ai.html">PRFB (vector plus immediate):Gather prefetch bytes (vector plus immediate)</a>
  AMED_AARCH64_PAGE_prfb_i_p_bi, //!< <a href="../target/aarch64/prfb_i_p_bi.html">PRFB (scalar plus immediate):Contiguous prefetch bytes (immediate index)</a>
  AMED_AARCH64_PAGE_prfb_i_p_br, //!< <a href="../target/aarch64/prfb_i_p_br.html">PRFB (scalar plus scalar):Contiguous prefetch bytes (scalar index)</a>
  AMED_AARCH64_PAGE_prfb_i_p_bz, //!< <a href="../target/aarch64/prfb_i_p_bz.html">PRFB (scalar plus vector):Gather prefetch bytes (scalar plus vector)</a>
  AMED_AARCH64_PAGE_prfd_i_p_ai, //!< <a href="../target/aarch64/prfd_i_p_ai.html">PRFD (vector plus immediate):Gather prefetch doublewords (vector plus immediate)</a>
  AMED_AARCH64_PAGE_prfd_i_p_bi, //!< <a href="../target/aarch64/prfd_i_p_bi.html">PRFD (scalar plus immediate):Contiguous prefetch doublewords (immediate index)</a>
  AMED_AARCH64_PAGE_prfd_i_p_br, //!< <a href="../target/aarch64/prfd_i_p_br.html">PRFD (scalar plus scalar):Contiguous prefetch doublewords (scalar index)</a>
  AMED_AARCH64_PAGE_prfd_i_p_bz, //!< <a href="../target/aarch64/prfd_i_p_bz.html">PRFD (scalar plus vector):Gather prefetch doublewords (scalar plus vector)</a>
  AMED_AARCH64_PAGE_prfh_i_p_ai, //!< <a href="../target/aarch64/prfh_i_p_ai.html">PRFH (vector plus immediate):Gather prefetch halfwords (vector plus immediate)</a>
  AMED_AARCH64_PAGE_prfh_i_p_bi, //!< <a href="../target/aarch64/prfh_i_p_bi.html">PRFH (scalar plus immediate):Contiguous prefetch halfwords (immediate index)</a>
  AMED_AARCH64_PAGE_prfh_i_p_br, //!< <a href="../target/aarch64/prfh_i_p_br.html">PRFH (scalar plus scalar):Contiguous prefetch halfwords (scalar index)</a>
  AMED_AARCH64_PAGE_prfh_i_p_bz, //!< <a href="../target/aarch64/prfh_i_p_bz.html">PRFH (scalar plus vector):Gather prefetch halfwords (scalar plus vector)</a>
  AMED_AARCH64_PAGE_prfw_i_p_ai, //!< <a href="../target/aarch64/prfw_i_p_ai.html">PRFW (vector plus immediate):Gather prefetch words (vector plus immediate)</a>
  AMED_AARCH64_PAGE_prfw_i_p_bi, //!< <a href="../target/aarch64/prfw_i_p_bi.html">PRFW (scalar plus immediate):Contiguous prefetch words (immediate index)</a>
  AMED_AARCH64_PAGE_prfw_i_p_br, //!< <a href="../target/aarch64/prfw_i_p_br.html">PRFW (scalar plus scalar):Contiguous prefetch words (scalar index)</a>
  AMED_AARCH64_PAGE_prfw_i_p_bz, //!< <a href="../target/aarch64/prfw_i_p_bz.html">PRFW (scalar plus vector):Gather prefetch words (scalar plus vector)</a>
  AMED_AARCH64_PAGE_ptest_p_p, //!< <a href="../target/aarch64/ptest_p_p.html">PTEST:Set condition flags for predicate</a>
  AMED_AARCH64_PAGE_ptrue_p_s, //!< <a href="../target/aarch64/ptrue_p_s.html">PTRUE, PTRUES:Initialise predicate from named constraint</a>
  AMED_AARCH64_PAGE_punpkhi_p_p, //!< <a href="../target/aarch64/punpkhi_p_p.html">PUNPKHI, PUNPKLO:Unpack and widen half of predicate</a>
  AMED_AARCH64_PAGE_raddhnb_z_zz, //!< <a href="../target/aarch64/raddhnb_z_zz.html">RADDHNB:Rounding add narrow high part (bottom)</a>
  AMED_AARCH64_PAGE_raddhnt_z_zz, //!< <a href="../target/aarch64/raddhnt_z_zz.html">RADDHNT:Rounding add narrow high part (top)</a>
  AMED_AARCH64_PAGE_rax1_z_zz, //!< <a href="../target/aarch64/rax1_z_zz.html">RAX1:Bitwise rotate left by 1 and exclusive OR</a>
  AMED_AARCH64_PAGE_rbit_z_p_z, //!< <a href="../target/aarch64/rbit_z_p_z.html">RBIT:Reverse bits (predicated)</a>
  AMED_AARCH64_PAGE_rdffr_p_f, //!< <a href="../target/aarch64/rdffr_p_f.html">RDFFR (unpredicated):Read the first-fault register</a>
  AMED_AARCH64_PAGE_rdffr_p_p_f, //!< <a href="../target/aarch64/rdffr_p_p_f.html">RDFFR, RDFFRS (predicated):Return predicate of succesfully loaded elements</a>
  AMED_AARCH64_PAGE_rdvl_r_i, //!< <a href="../target/aarch64/rdvl_r_i.html">RDVL:Read multiple of vector register size to scalar register</a>
  AMED_AARCH64_PAGE_rev_p_p, //!< <a href="../target/aarch64/rev_p_p.html">REV (predicate):Reverse all elements in a predicate</a>
  AMED_AARCH64_PAGE_rev_z_z, //!< <a href="../target/aarch64/rev_z_z.html">REV (vector):Reverse all elements in a vector (unpredicated)</a>
  AMED_AARCH64_PAGE_revb_z_z, //!< <a href="../target/aarch64/revb_z_z.html">REVB, REVH, REVW:Reverse bytes / halfwords / words within elements (predicated)</a>
  AMED_AARCH64_PAGE_rshrnb_z_zi, //!< <a href="../target/aarch64/rshrnb_z_zi.html">RSHRNB:Rounding shift right narrow by immediate (bottom)</a>
  AMED_AARCH64_PAGE_rshrnt_z_zi, //!< <a href="../target/aarch64/rshrnt_z_zi.html">RSHRNT:Rounding shift right narrow by immediate (top)</a>
  AMED_AARCH64_PAGE_rsubhnb_z_zz, //!< <a href="../target/aarch64/rsubhnb_z_zz.html">RSUBHNB:Rounding subtract narrow high part (bottom)</a>
  AMED_AARCH64_PAGE_rsubhnt_z_zz, //!< <a href="../target/aarch64/rsubhnt_z_zz.html">RSUBHNT:Rounding subtract narrow high part (top)</a>
  AMED_AARCH64_PAGE_saba_z_zzz, //!< <a href="../target/aarch64/saba_z_zzz.html">SABA:Signed absolute difference and accumulate</a>
  AMED_AARCH64_PAGE_sabalb_z_zzz, //!< <a href="../target/aarch64/sabalb_z_zzz.html">SABALB:Signed absolute difference and accumulate long (bottom)</a>
  AMED_AARCH64_PAGE_sabalt_z_zzz, //!< <a href="../target/aarch64/sabalt_z_zzz.html">SABALT:Signed absolute difference and accumulate long (top)</a>
  AMED_AARCH64_PAGE_sabd_z_p_zz, //!< <a href="../target/aarch64/sabd_z_p_zz.html">SABD:Signed absolute difference (predicated)</a>
  AMED_AARCH64_PAGE_sabdlb_z_zz, //!< <a href="../target/aarch64/sabdlb_z_zz.html">SABDLB:Signed absolute difference long (bottom)</a>
  AMED_AARCH64_PAGE_sabdlt_z_zz, //!< <a href="../target/aarch64/sabdlt_z_zz.html">SABDLT:Signed absolute difference long (top)</a>
  AMED_AARCH64_PAGE_sadalp_z_p_z, //!< <a href="../target/aarch64/sadalp_z_p_z.html">SADALP:Signed add and accumulate long pairwise</a>
  AMED_AARCH64_PAGE_saddlb_z_zz, //!< <a href="../target/aarch64/saddlb_z_zz.html">SADDLB:Signed add long (bottom)</a>
  AMED_AARCH64_PAGE_saddlbt_z_zz, //!< <a href="../target/aarch64/saddlbt_z_zz.html">SADDLBT:Signed add long (bottom + top)</a>
  AMED_AARCH64_PAGE_saddlt_z_zz, //!< <a href="../target/aarch64/saddlt_z_zz.html">SADDLT:Signed add long (top)</a>
  AMED_AARCH64_PAGE_saddv_r_p_z, //!< <a href="../target/aarch64/saddv_r_p_z.html">SADDV:Signed add reduction to scalar</a>
  AMED_AARCH64_PAGE_saddwb_z_zz, //!< <a href="../target/aarch64/saddwb_z_zz.html">SADDWB:Signed add wide (bottom)</a>
  AMED_AARCH64_PAGE_saddwt_z_zz, //!< <a href="../target/aarch64/saddwt_z_zz.html">SADDWT:Signed add wide (top)</a>
  AMED_AARCH64_PAGE_sbclb_z_zzz, //!< <a href="../target/aarch64/sbclb_z_zzz.html">SBCLB:Subtract with carry long (bottom)</a>
  AMED_AARCH64_PAGE_sbclt_z_zzz, //!< <a href="../target/aarch64/sbclt_z_zzz.html">SBCLT:Subtract with carry long (top)</a>
  AMED_AARCH64_PAGE_scvtf_z_p_z, //!< <a href="../target/aarch64/scvtf_z_p_z.html">SCVTF:Signed integer convert to floating-point (predicated)</a>
  AMED_AARCH64_PAGE_sdiv_z_p_zz, //!< <a href="../target/aarch64/sdiv_z_p_zz.html">SDIV:Signed divide (predicated)</a>
  AMED_AARCH64_PAGE_sdivr_z_p_zz, //!< <a href="../target/aarch64/sdivr_z_p_zz.html">SDIVR:Signed reversed divide (predicated)</a>
  AMED_AARCH64_PAGE_sdot_z_zzz, //!< <a href="../target/aarch64/sdot_z_zzz.html">SDOT (vectors):Signed integer dot product</a>
  AMED_AARCH64_PAGE_sdot_z_zzzi, //!< <a href="../target/aarch64/sdot_z_zzzi.html">SDOT (indexed):Signed integer indexed dot product</a>
  AMED_AARCH64_PAGE_sel_p_p_pp, //!< <a href="../target/aarch64/sel_p_p_pp.html">SEL (predicates):Conditionally select elements from two predicates</a>
  AMED_AARCH64_PAGE_sel_z_p_zz, //!< <a href="../target/aarch64/sel_z_p_zz.html">SEL (vectors):Conditionally select elements from two vectors</a>
  AMED_AARCH64_PAGE_setffr_f, //!< <a href="../target/aarch64/setffr_f.html">SETFFR:Initialise the first-fault register to all true</a>
  AMED_AARCH64_PAGE_shadd_z_p_zz, //!< <a href="../target/aarch64/shadd_z_p_zz.html">SHADD:Signed halving addition</a>
  AMED_AARCH64_PAGE_shrnb_z_zi, //!< <a href="../target/aarch64/shrnb_z_zi.html">SHRNB:Shift right narrow by immediate (bottom)</a>
  AMED_AARCH64_PAGE_shrnt_z_zi, //!< <a href="../target/aarch64/shrnt_z_zi.html">SHRNT:Shift right narrow by immediate (top)</a>
  AMED_AARCH64_PAGE_shsub_z_p_zz, //!< <a href="../target/aarch64/shsub_z_p_zz.html">SHSUB:Signed halving subtract</a>
  AMED_AARCH64_PAGE_shsubr_z_p_zz, //!< <a href="../target/aarch64/shsubr_z_p_zz.html">SHSUBR:Signed halving subtract reversed vectors</a>
  AMED_AARCH64_PAGE_sli_z_zzi, //!< <a href="../target/aarch64/sli_z_zzi.html">SLI:Shift left and insert (immediate)</a>
  AMED_AARCH64_PAGE_sm4e_z_zz, //!< <a href="../target/aarch64/sm4e_z_zz.html">SM4E:SM4 encryption and decryption</a>
  AMED_AARCH64_PAGE_sm4ekey_z_zz, //!< <a href="../target/aarch64/sm4ekey_z_zz.html">SM4EKEY:SM4 key updates</a>
  AMED_AARCH64_PAGE_smax_z_p_zz, //!< <a href="../target/aarch64/smax_z_p_zz.html">SMAX (vectors):Signed maximum vectors (predicated)</a>
  AMED_AARCH64_PAGE_smax_z_zi, //!< <a href="../target/aarch64/smax_z_zi.html">SMAX (immediate):Signed maximum with immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_smaxp_z_p_zz, //!< <a href="../target/aarch64/smaxp_z_p_zz.html">SMAXP:Signed maximum pairwise</a>
  AMED_AARCH64_PAGE_smaxv_r_p_z, //!< <a href="../target/aarch64/smaxv_r_p_z.html">SMAXV:Signed maximum reduction to scalar</a>
  AMED_AARCH64_PAGE_smin_z_p_zz, //!< <a href="../target/aarch64/smin_z_p_zz.html">SMIN (vectors):Signed minimum vectors (predicated)</a>
  AMED_AARCH64_PAGE_smin_z_zi, //!< <a href="../target/aarch64/smin_z_zi.html">SMIN (immediate):Signed minimum with immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_sminp_z_p_zz, //!< <a href="../target/aarch64/sminp_z_p_zz.html">SMINP:Signed minimum pairwise</a>
  AMED_AARCH64_PAGE_sminv_r_p_z, //!< <a href="../target/aarch64/sminv_r_p_z.html">SMINV:Signed minimum reduction to scalar</a>
  AMED_AARCH64_PAGE_smlalb_z_zzz, //!< <a href="../target/aarch64/smlalb_z_zzz.html">SMLALB (vectors):Signed multiply-add long to accumulator (bottom)</a>
  AMED_AARCH64_PAGE_smlalb_z_zzzi, //!< <a href="../target/aarch64/smlalb_z_zzzi.html">SMLALB (indexed):Signed multiply-add long to accumulator (bottom, indexed)</a>
  AMED_AARCH64_PAGE_smlalt_z_zzz, //!< <a href="../target/aarch64/smlalt_z_zzz.html">SMLALT (vectors):Signed multiply-add long to accumulator (top)</a>
  AMED_AARCH64_PAGE_smlalt_z_zzzi, //!< <a href="../target/aarch64/smlalt_z_zzzi.html">SMLALT (indexed):Signed multiply-add long to accumulator (top, indexed)</a>
  AMED_AARCH64_PAGE_smlslb_z_zzz, //!< <a href="../target/aarch64/smlslb_z_zzz.html">SMLSLB (vectors):Signed multiply-subtract long from accumulator (bottom)</a>
  AMED_AARCH64_PAGE_smlslb_z_zzzi, //!< <a href="../target/aarch64/smlslb_z_zzzi.html">SMLSLB (indexed):Signed multiply-subtract long from accumulator (bottom, indexed)</a>
  AMED_AARCH64_PAGE_smlslt_z_zzz, //!< <a href="../target/aarch64/smlslt_z_zzz.html">SMLSLT (vectors):Signed multiply-subtract long from accumulator (top)</a>
  AMED_AARCH64_PAGE_smlslt_z_zzzi, //!< <a href="../target/aarch64/smlslt_z_zzzi.html">SMLSLT (indexed):Signed multiply-subtract long from accumulator (top, indexed)</a>
  AMED_AARCH64_PAGE_smmla_z_zzz, //!< <a href="../target/aarch64/smmla_z_zzz.html">SMMLA:Signed integer matrix multiply-accumulate</a>
  AMED_AARCH64_PAGE_smulh_z_p_zz, //!< <a href="../target/aarch64/smulh_z_p_zz.html">SMULH (predicated):Signed multiply returning high half (predicated)</a>
  AMED_AARCH64_PAGE_smulh_z_zz, //!< <a href="../target/aarch64/smulh_z_zz.html">SMULH (unpredicated):Signed multiply returning high half (unpredicated)</a>
  AMED_AARCH64_PAGE_smullb_z_zz, //!< <a href="../target/aarch64/smullb_z_zz.html">SMULLB (vectors):Signed multiply long (bottom)</a>
  AMED_AARCH64_PAGE_smullb_z_zzi, //!< <a href="../target/aarch64/smullb_z_zzi.html">SMULLB (indexed):Signed multiply long (bottom, indexed)</a>
  AMED_AARCH64_PAGE_smullt_z_zz, //!< <a href="../target/aarch64/smullt_z_zz.html">SMULLT (vectors):Signed multiply long (top)</a>
  AMED_AARCH64_PAGE_smullt_z_zzi, //!< <a href="../target/aarch64/smullt_z_zzi.html">SMULLT (indexed):Signed multiply long (top, indexed)</a>
  AMED_AARCH64_PAGE_splice_z_p_zz, //!< <a href="../target/aarch64/splice_z_p_zz.html">SPLICE:Splice two vectors under predicate control</a>
  AMED_AARCH64_PAGE_sqabs_z_p_z, //!< <a href="../target/aarch64/sqabs_z_p_z.html">SQABS:Signed saturating absolute value</a>
  AMED_AARCH64_PAGE_sqadd_z_p_zz, //!< <a href="../target/aarch64/sqadd_z_p_zz.html">SQADD (vectors, predicated):Signed saturating addition (predicated)</a>
  AMED_AARCH64_PAGE_sqadd_z_zi, //!< <a href="../target/aarch64/sqadd_z_zi.html">SQADD (immediate):Signed saturating add immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_sqadd_z_zz, //!< <a href="../target/aarch64/sqadd_z_zz.html">SQADD (vectors, unpredicated):Signed saturating add vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_sqcadd_z_zz, //!< <a href="../target/aarch64/sqcadd_z_zz.html">SQCADD:Saturating complex integer add with rotate</a>
  AMED_AARCH64_PAGE_sqdecb_r_rs, //!< <a href="../target/aarch64/sqdecb_r_rs.html">SQDECB:Signed saturating decrement scalar by multiple of 8-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqdecd_r_rs, //!< <a href="../target/aarch64/sqdecd_r_rs.html">SQDECD (scalar):Signed saturating decrement scalar by multiple of 64-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqdecd_z_zs, //!< <a href="../target/aarch64/sqdecd_z_zs.html">SQDECD (vector):Signed saturating decrement vector by multiple of 64-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqdech_r_rs, //!< <a href="../target/aarch64/sqdech_r_rs.html">SQDECH (scalar):Signed saturating decrement scalar by multiple of 16-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqdech_z_zs, //!< <a href="../target/aarch64/sqdech_z_zs.html">SQDECH (vector):Signed saturating decrement vector by multiple of 16-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqdecp_r_p_r, //!< <a href="../target/aarch64/sqdecp_r_p_r.html">SQDECP (scalar):Signed saturating decrement scalar by count of true predicate elements</a>
  AMED_AARCH64_PAGE_sqdecp_z_p_z, //!< <a href="../target/aarch64/sqdecp_z_p_z.html">SQDECP (vector):Signed saturating decrement vector by count of true predicate elements</a>
  AMED_AARCH64_PAGE_sqdecw_r_rs, //!< <a href="../target/aarch64/sqdecw_r_rs.html">SQDECW (scalar):Signed saturating decrement scalar by multiple of 32-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqdecw_z_zs, //!< <a href="../target/aarch64/sqdecw_z_zs.html">SQDECW (vector):Signed saturating decrement vector by multiple of 32-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqdmlalb_z_zzz, //!< <a href="../target/aarch64/sqdmlalb_z_zzz.html">SQDMLALB (vectors):Signed saturating doubling multiply-add long to accumulator (bottom)</a>
  AMED_AARCH64_PAGE_sqdmlalb_z_zzzi, //!< <a href="../target/aarch64/sqdmlalb_z_zzzi.html">SQDMLALB (indexed):Signed saturating doubling multiply-add long to accumulator (bottom, indexed)</a>
  AMED_AARCH64_PAGE_sqdmlalbt_z_zzz, //!< <a href="../target/aarch64/sqdmlalbt_z_zzz.html">SQDMLALBT:Signed saturating doubling multiply-add long to accumulator (bottom x top)</a>
  AMED_AARCH64_PAGE_sqdmlalt_z_zzz, //!< <a href="../target/aarch64/sqdmlalt_z_zzz.html">SQDMLALT (vectors):Signed saturating doubling multiply-add long to accumulator (top)</a>
  AMED_AARCH64_PAGE_sqdmlalt_z_zzzi, //!< <a href="../target/aarch64/sqdmlalt_z_zzzi.html">SQDMLALT (indexed):Signed saturating doubling multiply-add long to accumulator (top, indexed)</a>
  AMED_AARCH64_PAGE_sqdmlslb_z_zzz, //!< <a href="../target/aarch64/sqdmlslb_z_zzz.html">SQDMLSLB (vectors):Signed saturating doubling multiply-subtract long from accumulator (bottom)</a>
  AMED_AARCH64_PAGE_sqdmlslb_z_zzzi, //!< <a href="../target/aarch64/sqdmlslb_z_zzzi.html">SQDMLSLB (indexed):Signed saturating doubling multiply-subtract long from accumulator (bottom, indexed)</a>
  AMED_AARCH64_PAGE_sqdmlslbt_z_zzz, //!< <a href="../target/aarch64/sqdmlslbt_z_zzz.html">SQDMLSLBT:Signed saturating doubling multiply-subtract long from accumulator (bottom x top)</a>
  AMED_AARCH64_PAGE_sqdmlslt_z_zzz, //!< <a href="../target/aarch64/sqdmlslt_z_zzz.html">SQDMLSLT (vectors):Signed saturating doubling multiply-subtract long from accumulator (top)</a>
  AMED_AARCH64_PAGE_sqdmlslt_z_zzzi, //!< <a href="../target/aarch64/sqdmlslt_z_zzzi.html">SQDMLSLT (indexed):Signed saturating doubling multiply-subtract long from accumulator (top, indexed)</a>
  AMED_AARCH64_PAGE_sqdmulh_z_zz, //!< <a href="../target/aarch64/sqdmulh_z_zz.html">SQDMULH (vectors):Signed saturating doubling multiply high (unpredicated)</a>
  AMED_AARCH64_PAGE_sqdmulh_z_zzi, //!< <a href="../target/aarch64/sqdmulh_z_zzi.html">SQDMULH (indexed):Signed saturating doubling multiply high (indexed)</a>
  AMED_AARCH64_PAGE_sqdmullb_z_zz, //!< <a href="../target/aarch64/sqdmullb_z_zz.html">SQDMULLB (vectors):Signed saturating doubling multiply long (bottom)</a>
  AMED_AARCH64_PAGE_sqdmullb_z_zzi, //!< <a href="../target/aarch64/sqdmullb_z_zzi.html">SQDMULLB (indexed):Signed saturating doubling multiply long (bottom, indexed)</a>
  AMED_AARCH64_PAGE_sqdmullt_z_zz, //!< <a href="../target/aarch64/sqdmullt_z_zz.html">SQDMULLT (vectors):Signed saturating doubling multiply long (top)</a>
  AMED_AARCH64_PAGE_sqdmullt_z_zzi, //!< <a href="../target/aarch64/sqdmullt_z_zzi.html">SQDMULLT (indexed):Signed saturating doubling multiply long (top, indexed)</a>
  AMED_AARCH64_PAGE_sqincb_r_rs, //!< <a href="../target/aarch64/sqincb_r_rs.html">SQINCB:Signed saturating increment scalar by multiple of 8-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqincd_r_rs, //!< <a href="../target/aarch64/sqincd_r_rs.html">SQINCD (scalar):Signed saturating increment scalar by multiple of 64-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqincd_z_zs, //!< <a href="../target/aarch64/sqincd_z_zs.html">SQINCD (vector):Signed saturating increment vector by multiple of 64-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqinch_r_rs, //!< <a href="../target/aarch64/sqinch_r_rs.html">SQINCH (scalar):Signed saturating increment scalar by multiple of 16-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqinch_z_zs, //!< <a href="../target/aarch64/sqinch_z_zs.html">SQINCH (vector):Signed saturating increment vector by multiple of 16-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqincp_r_p_r, //!< <a href="../target/aarch64/sqincp_r_p_r.html">SQINCP (scalar):Signed saturating increment scalar by count of true predicate elements</a>
  AMED_AARCH64_PAGE_sqincp_z_p_z, //!< <a href="../target/aarch64/sqincp_z_p_z.html">SQINCP (vector):Signed saturating increment vector by count of true predicate elements</a>
  AMED_AARCH64_PAGE_sqincw_r_rs, //!< <a href="../target/aarch64/sqincw_r_rs.html">SQINCW (scalar):Signed saturating increment scalar by multiple of 32-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqincw_z_zs, //!< <a href="../target/aarch64/sqincw_z_zs.html">SQINCW (vector):Signed saturating increment vector by multiple of 32-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_sqneg_z_p_z, //!< <a href="../target/aarch64/sqneg_z_p_z.html">SQNEG:Signed saturating negate</a>
  AMED_AARCH64_PAGE_sqrdcmlah_z_zzz, //!< <a href="../target/aarch64/sqrdcmlah_z_zzz.html">SQRDCMLAH (vectors):Saturating rounding doubling complex integer multiply-add high with rotate</a>
  AMED_AARCH64_PAGE_sqrdcmlah_z_zzzi, //!< <a href="../target/aarch64/sqrdcmlah_z_zzzi.html">SQRDCMLAH (indexed):Saturating rounding doubling complex integer multiply-add high with rotate (indexed)</a>
  AMED_AARCH64_PAGE_sqrdmlah_z_zzz, //!< <a href="../target/aarch64/sqrdmlah_z_zzz.html">SQRDMLAH (vectors):Signed saturating rounding doubling multiply-add high to accumulator (unpredicated)</a>
  AMED_AARCH64_PAGE_sqrdmlah_z_zzzi, //!< <a href="../target/aarch64/sqrdmlah_z_zzzi.html">SQRDMLAH (indexed):Signed saturating rounding doubling multiply-add high to accumulator (indexed)</a>
  AMED_AARCH64_PAGE_sqrdmlsh_z_zzz, //!< <a href="../target/aarch64/sqrdmlsh_z_zzz.html">SQRDMLSH (vectors):Signed saturating rounding doubling multiply-subtract high from accumulator (unpredicated)</a>
  AMED_AARCH64_PAGE_sqrdmlsh_z_zzzi, //!< <a href="../target/aarch64/sqrdmlsh_z_zzzi.html">SQRDMLSH (indexed):Signed saturating rounding doubling multiply-subtract high from accumulator (indexed)</a>
  AMED_AARCH64_PAGE_sqrdmulh_z_zz, //!< <a href="../target/aarch64/sqrdmulh_z_zz.html">SQRDMULH (vectors):Signed saturating rounding doubling multiply high (unpredicated)</a>
  AMED_AARCH64_PAGE_sqrdmulh_z_zzi, //!< <a href="../target/aarch64/sqrdmulh_z_zzi.html">SQRDMULH (indexed):Signed saturating rounding doubling multiply high (indexed)</a>
  AMED_AARCH64_PAGE_sqrshl_z_p_zz, //!< <a href="../target/aarch64/sqrshl_z_p_zz.html">SQRSHL:Signed saturating rounding shift left by vector (predicated)</a>
  AMED_AARCH64_PAGE_sqrshlr_z_p_zz, //!< <a href="../target/aarch64/sqrshlr_z_p_zz.html">SQRSHLR:Signed saturating rounding shift left reversed vectors (predicated)</a>
  AMED_AARCH64_PAGE_sqrshrnb_z_zi, //!< <a href="../target/aarch64/sqrshrnb_z_zi.html">SQRSHRNB:Signed saturating rounding shift right narrow by immediate (bottom)</a>
  AMED_AARCH64_PAGE_sqrshrnt_z_zi, //!< <a href="../target/aarch64/sqrshrnt_z_zi.html">SQRSHRNT:Signed saturating rounding shift right narrow by immediate (top)</a>
  AMED_AARCH64_PAGE_sqrshrunb_z_zi, //!< <a href="../target/aarch64/sqrshrunb_z_zi.html">SQRSHRUNB:Signed saturating rounding shift right unsigned narrow by immediate (bottom)</a>
  AMED_AARCH64_PAGE_sqrshrunt_z_zi, //!< <a href="../target/aarch64/sqrshrunt_z_zi.html">SQRSHRUNT:Signed saturating rounding shift right unsigned narrow by immediate (top)</a>
  AMED_AARCH64_PAGE_sqshl_z_p_zi, //!< <a href="../target/aarch64/sqshl_z_p_zi.html">SQSHL (immediate):Signed saturating shift left by immediate</a>
  AMED_AARCH64_PAGE_sqshl_z_p_zz, //!< <a href="../target/aarch64/sqshl_z_p_zz.html">SQSHL (vectors):Signed saturating shift left by vector (predicated)</a>
  AMED_AARCH64_PAGE_sqshlr_z_p_zz, //!< <a href="../target/aarch64/sqshlr_z_p_zz.html">SQSHLR:Signed saturating shift left reversed vectors (predicated)</a>
  AMED_AARCH64_PAGE_sqshlu_z_p_zi, //!< <a href="../target/aarch64/sqshlu_z_p_zi.html">SQSHLU:Signed saturating shift left unsigned by immediate</a>
  AMED_AARCH64_PAGE_sqshrnb_z_zi, //!< <a href="../target/aarch64/sqshrnb_z_zi.html">SQSHRNB:Signed saturating shift right narrow by immediate (bottom)</a>
  AMED_AARCH64_PAGE_sqshrnt_z_zi, //!< <a href="../target/aarch64/sqshrnt_z_zi.html">SQSHRNT:Signed saturating shift right narrow by immediate (top)</a>
  AMED_AARCH64_PAGE_sqshrunb_z_zi, //!< <a href="../target/aarch64/sqshrunb_z_zi.html">SQSHRUNB:Signed saturating shift right unsigned narrow by immediate (bottom)</a>
  AMED_AARCH64_PAGE_sqshrunt_z_zi, //!< <a href="../target/aarch64/sqshrunt_z_zi.html">SQSHRUNT:Signed saturating shift right unsigned narrow by immediate (top)</a>
  AMED_AARCH64_PAGE_sqsub_z_p_zz, //!< <a href="../target/aarch64/sqsub_z_p_zz.html">SQSUB (vectors, predicated):Signed saturating subtraction (predicated)</a>
  AMED_AARCH64_PAGE_sqsub_z_zi, //!< <a href="../target/aarch64/sqsub_z_zi.html">SQSUB (immediate):Signed saturating subtract immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_sqsub_z_zz, //!< <a href="../target/aarch64/sqsub_z_zz.html">SQSUB (vectors, unpredicated):Signed saturating subtract vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_sqsubr_z_p_zz, //!< <a href="../target/aarch64/sqsubr_z_p_zz.html">SQSUBR:Signed saturating subtraction reversed vectors (predicated)</a>
  AMED_AARCH64_PAGE_sqxtnb_z_zz, //!< <a href="../target/aarch64/sqxtnb_z_zz.html">SQXTNB:Signed saturating extract narrow (bottom)</a>
  AMED_AARCH64_PAGE_sqxtnt_z_zz, //!< <a href="../target/aarch64/sqxtnt_z_zz.html">SQXTNT:Signed saturating extract narrow (top)</a>
  AMED_AARCH64_PAGE_sqxtunb_z_zz, //!< <a href="../target/aarch64/sqxtunb_z_zz.html">SQXTUNB:Signed saturating unsigned extract narrow (bottom)</a>
  AMED_AARCH64_PAGE_sqxtunt_z_zz, //!< <a href="../target/aarch64/sqxtunt_z_zz.html">SQXTUNT:Signed saturating unsigned extract narrow (top)</a>
  AMED_AARCH64_PAGE_srhadd_z_p_zz, //!< <a href="../target/aarch64/srhadd_z_p_zz.html">SRHADD:Signed rounding halving addition</a>
  AMED_AARCH64_PAGE_sri_z_zzi, //!< <a href="../target/aarch64/sri_z_zzi.html">SRI:Shift right and insert (immediate)</a>
  AMED_AARCH64_PAGE_srshl_z_p_zz, //!< <a href="../target/aarch64/srshl_z_p_zz.html">SRSHL:Signed rounding shift left by vector (predicated)</a>
  AMED_AARCH64_PAGE_srshlr_z_p_zz, //!< <a href="../target/aarch64/srshlr_z_p_zz.html">SRSHLR:Signed rounding shift left reversed vectors (predicated)</a>
  AMED_AARCH64_PAGE_srshr_z_p_zi, //!< <a href="../target/aarch64/srshr_z_p_zi.html">SRSHR:Signed rounding shift right by immediate</a>
  AMED_AARCH64_PAGE_srsra_z_zi, //!< <a href="../target/aarch64/srsra_z_zi.html">SRSRA:Signed rounding shift right and accumulate (immediate)</a>
  AMED_AARCH64_PAGE_sshllb_z_zi, //!< <a href="../target/aarch64/sshllb_z_zi.html">SSHLLB:Signed shift left long by immediate (bottom)</a>
  AMED_AARCH64_PAGE_sshllt_z_zi, //!< <a href="../target/aarch64/sshllt_z_zi.html">SSHLLT:Signed shift left long by immediate (top)</a>
  AMED_AARCH64_PAGE_ssra_z_zi, //!< <a href="../target/aarch64/ssra_z_zi.html">SSRA:Signed shift right and accumulate (immediate)</a>
  AMED_AARCH64_PAGE_ssublb_z_zz, //!< <a href="../target/aarch64/ssublb_z_zz.html">SSUBLB:Signed subtract long (bottom)</a>
  AMED_AARCH64_PAGE_ssublbt_z_zz, //!< <a href="../target/aarch64/ssublbt_z_zz.html">SSUBLBT:Signed subtract long (bottom - top)</a>
  AMED_AARCH64_PAGE_ssublt_z_zz, //!< <a href="../target/aarch64/ssublt_z_zz.html">SSUBLT:Signed subtract long (top)</a>
  AMED_AARCH64_PAGE_ssubltb_z_zz, //!< <a href="../target/aarch64/ssubltb_z_zz.html">SSUBLTB:Signed subtract long (top - bottom)</a>
  AMED_AARCH64_PAGE_ssubwb_z_zz, //!< <a href="../target/aarch64/ssubwb_z_zz.html">SSUBWB:Signed subtract wide (bottom)</a>
  AMED_AARCH64_PAGE_ssubwt_z_zz, //!< <a href="../target/aarch64/ssubwt_z_zz.html">SSUBWT:Signed subtract wide (top)</a>
  AMED_AARCH64_PAGE_st1b_z_p_ai, //!< <a href="../target/aarch64/st1b_z_p_ai.html">ST1B (vector plus immediate):Scatter store bytes from a vector (immediate index)</a>
  AMED_AARCH64_PAGE_st1b_z_p_bi, //!< <a href="../target/aarch64/st1b_z_p_bi.html">ST1B (scalar plus immediate):Contiguous store bytes from vector (immediate index)</a>
  AMED_AARCH64_PAGE_st1b_z_p_br, //!< <a href="../target/aarch64/st1b_z_p_br.html">ST1B (scalar plus scalar):Contiguous store bytes from vector (scalar index)</a>
  AMED_AARCH64_PAGE_st1b_z_p_bz, //!< <a href="../target/aarch64/st1b_z_p_bz.html">ST1B (scalar plus vector):Scatter store bytes from a vector (vector index)</a>
  AMED_AARCH64_PAGE_st1d_z_p_ai, //!< <a href="../target/aarch64/st1d_z_p_ai.html">ST1D (vector plus immediate):Scatter store doublewords from a vector (immediate index)</a>
  AMED_AARCH64_PAGE_st1d_z_p_bi, //!< <a href="../target/aarch64/st1d_z_p_bi.html">ST1D (scalar plus immediate):Contiguous store doublewords from vector (immediate index)</a>
  AMED_AARCH64_PAGE_st1d_z_p_br, //!< <a href="../target/aarch64/st1d_z_p_br.html">ST1D (scalar plus scalar):Contiguous store doublewords from vector (scalar index)</a>
  AMED_AARCH64_PAGE_st1d_z_p_bz, //!< <a href="../target/aarch64/st1d_z_p_bz.html">ST1D (scalar plus vector):Scatter store doublewords from a vector (vector index)</a>
  AMED_AARCH64_PAGE_st1h_z_p_ai, //!< <a href="../target/aarch64/st1h_z_p_ai.html">ST1H (vector plus immediate):Scatter store halfwords from a vector (immediate index)</a>
  AMED_AARCH64_PAGE_st1h_z_p_bi, //!< <a href="../target/aarch64/st1h_z_p_bi.html">ST1H (scalar plus immediate):Contiguous store halfwords from vector (immediate index)</a>
  AMED_AARCH64_PAGE_st1h_z_p_br, //!< <a href="../target/aarch64/st1h_z_p_br.html">ST1H (scalar plus scalar):Contiguous store halfwords from vector (scalar index)</a>
  AMED_AARCH64_PAGE_st1h_z_p_bz, //!< <a href="../target/aarch64/st1h_z_p_bz.html">ST1H (scalar plus vector):Scatter store halfwords from a vector (vector index)</a>
  AMED_AARCH64_PAGE_st1w_z_p_ai, //!< <a href="../target/aarch64/st1w_z_p_ai.html">ST1W (vector plus immediate):Scatter store words from a vector (immediate index)</a>
  AMED_AARCH64_PAGE_st1w_z_p_bi, //!< <a href="../target/aarch64/st1w_z_p_bi.html">ST1W (scalar plus immediate):Contiguous store words from vector (immediate index)</a>
  AMED_AARCH64_PAGE_st1w_z_p_br, //!< <a href="../target/aarch64/st1w_z_p_br.html">ST1W (scalar plus scalar):Contiguous store words from vector (scalar index)</a>
  AMED_AARCH64_PAGE_st1w_z_p_bz, //!< <a href="../target/aarch64/st1w_z_p_bz.html">ST1W (scalar plus vector):Scatter store words from a vector (vector index)</a>
  AMED_AARCH64_PAGE_st2b_z_p_bi, //!< <a href="../target/aarch64/st2b_z_p_bi.html">ST2B (scalar plus immediate):Contiguous store two-byte structures from two vectors (immediate index)</a>
  AMED_AARCH64_PAGE_st2b_z_p_br, //!< <a href="../target/aarch64/st2b_z_p_br.html">ST2B (scalar plus scalar):Contiguous store two-byte structures from two vectors (scalar index)</a>
  AMED_AARCH64_PAGE_st2d_z_p_bi, //!< <a href="../target/aarch64/st2d_z_p_bi.html">ST2D (scalar plus immediate):Contiguous store two-doubleword structures from two vectors (immediate index)</a>
  AMED_AARCH64_PAGE_st2d_z_p_br, //!< <a href="../target/aarch64/st2d_z_p_br.html">ST2D (scalar plus scalar):Contiguous store two-doubleword structures from two vectors (scalar index)</a>
  AMED_AARCH64_PAGE_st2h_z_p_bi, //!< <a href="../target/aarch64/st2h_z_p_bi.html">ST2H (scalar plus immediate):Contiguous store two-halfword structures from two vectors (immediate index)</a>
  AMED_AARCH64_PAGE_st2h_z_p_br, //!< <a href="../target/aarch64/st2h_z_p_br.html">ST2H (scalar plus scalar):Contiguous store two-halfword structures from two vectors (scalar index)</a>
  AMED_AARCH64_PAGE_st2w_z_p_bi, //!< <a href="../target/aarch64/st2w_z_p_bi.html">ST2W (scalar plus immediate):Contiguous store two-word structures from two vectors (immediate index)</a>
  AMED_AARCH64_PAGE_st2w_z_p_br, //!< <a href="../target/aarch64/st2w_z_p_br.html">ST2W (scalar plus scalar):Contiguous store two-word structures from two vectors (scalar index)</a>
  AMED_AARCH64_PAGE_st3b_z_p_bi, //!< <a href="../target/aarch64/st3b_z_p_bi.html">ST3B (scalar plus immediate):Contiguous store three-byte structures from three vectors (immediate index)</a>
  AMED_AARCH64_PAGE_st3b_z_p_br, //!< <a href="../target/aarch64/st3b_z_p_br.html">ST3B (scalar plus scalar):Contiguous store three-byte structures from three vectors (scalar index)</a>
  AMED_AARCH64_PAGE_st3d_z_p_bi, //!< <a href="../target/aarch64/st3d_z_p_bi.html">ST3D (scalar plus immediate):Contiguous store three-doubleword structures from three vectors (immediate index)</a>
  AMED_AARCH64_PAGE_st3d_z_p_br, //!< <a href="../target/aarch64/st3d_z_p_br.html">ST3D (scalar plus scalar):Contiguous store three-doubleword structures from three vectors (scalar index)</a>
  AMED_AARCH64_PAGE_st3h_z_p_bi, //!< <a href="../target/aarch64/st3h_z_p_bi.html">ST3H (scalar plus immediate):Contiguous store three-halfword structures from three vectors (immediate index)</a>
  AMED_AARCH64_PAGE_st3h_z_p_br, //!< <a href="../target/aarch64/st3h_z_p_br.html">ST3H (scalar plus scalar):Contiguous store three-halfword structures from three vectors (scalar index)</a>
  AMED_AARCH64_PAGE_st3w_z_p_bi, //!< <a href="../target/aarch64/st3w_z_p_bi.html">ST3W (scalar plus immediate):Contiguous store three-word structures from three vectors (immediate index)</a>
  AMED_AARCH64_PAGE_st3w_z_p_br, //!< <a href="../target/aarch64/st3w_z_p_br.html">ST3W (scalar plus scalar):Contiguous store three-word structures from three vectors (scalar index)</a>
  AMED_AARCH64_PAGE_st4b_z_p_bi, //!< <a href="../target/aarch64/st4b_z_p_bi.html">ST4B (scalar plus immediate):Contiguous store four-byte structures from four vectors (immediate index)</a>
  AMED_AARCH64_PAGE_st4b_z_p_br, //!< <a href="../target/aarch64/st4b_z_p_br.html">ST4B (scalar plus scalar):Contiguous store four-byte structures from four vectors (scalar index)</a>
  AMED_AARCH64_PAGE_st4d_z_p_bi, //!< <a href="../target/aarch64/st4d_z_p_bi.html">ST4D (scalar plus immediate):Contiguous store four-doubleword structures from four vectors (immediate index)</a>
  AMED_AARCH64_PAGE_st4d_z_p_br, //!< <a href="../target/aarch64/st4d_z_p_br.html">ST4D (scalar plus scalar):Contiguous store four-doubleword structures from four vectors (scalar index)</a>
  AMED_AARCH64_PAGE_st4h_z_p_bi, //!< <a href="../target/aarch64/st4h_z_p_bi.html">ST4H (scalar plus immediate):Contiguous store four-halfword structures from four vectors (immediate index)</a>
  AMED_AARCH64_PAGE_st4h_z_p_br, //!< <a href="../target/aarch64/st4h_z_p_br.html">ST4H (scalar plus scalar):Contiguous store four-halfword structures from four vectors (scalar index)</a>
  AMED_AARCH64_PAGE_st4w_z_p_bi, //!< <a href="../target/aarch64/st4w_z_p_bi.html">ST4W (scalar plus immediate):Contiguous store four-word structures from four vectors (immediate index)</a>
  AMED_AARCH64_PAGE_st4w_z_p_br, //!< <a href="../target/aarch64/st4w_z_p_br.html">ST4W (scalar plus scalar):Contiguous store four-word structures from four vectors (scalar index)</a>
  AMED_AARCH64_PAGE_stnt1b_z_p_ar, //!< <a href="../target/aarch64/stnt1b_z_p_ar.html">STNT1B (vector plus scalar):Scatter store non-temporal bytes</a>
  AMED_AARCH64_PAGE_stnt1b_z_p_bi, //!< <a href="../target/aarch64/stnt1b_z_p_bi.html">STNT1B (scalar plus immediate):Contiguous store non-temporal bytes from vector (immediate index)</a>
  AMED_AARCH64_PAGE_stnt1b_z_p_br, //!< <a href="../target/aarch64/stnt1b_z_p_br.html">STNT1B (scalar plus scalar):Contiguous store non-temporal bytes from vector (scalar index)</a>
  AMED_AARCH64_PAGE_stnt1d_z_p_ar, //!< <a href="../target/aarch64/stnt1d_z_p_ar.html">STNT1D (vector plus scalar):Scatter store non-temporal doublewords</a>
  AMED_AARCH64_PAGE_stnt1d_z_p_bi, //!< <a href="../target/aarch64/stnt1d_z_p_bi.html">STNT1D (scalar plus immediate):Contiguous store non-temporal doublewords from vector (immediate index)</a>
  AMED_AARCH64_PAGE_stnt1d_z_p_br, //!< <a href="../target/aarch64/stnt1d_z_p_br.html">STNT1D (scalar plus scalar):Contiguous store non-temporal doublewords from vector (scalar index)</a>
  AMED_AARCH64_PAGE_stnt1h_z_p_ar, //!< <a href="../target/aarch64/stnt1h_z_p_ar.html">STNT1H (vector plus scalar):Scatter store non-temporal halfwords</a>
  AMED_AARCH64_PAGE_stnt1h_z_p_bi, //!< <a href="../target/aarch64/stnt1h_z_p_bi.html">STNT1H (scalar plus immediate):Contiguous store non-temporal halfwords from vector (immediate index)</a>
  AMED_AARCH64_PAGE_stnt1h_z_p_br, //!< <a href="../target/aarch64/stnt1h_z_p_br.html">STNT1H (scalar plus scalar):Contiguous store non-temporal halfwords from vector (scalar index)</a>
  AMED_AARCH64_PAGE_stnt1w_z_p_ar, //!< <a href="../target/aarch64/stnt1w_z_p_ar.html">STNT1W (vector plus scalar):Scatter store non-temporal words</a>
  AMED_AARCH64_PAGE_stnt1w_z_p_bi, //!< <a href="../target/aarch64/stnt1w_z_p_bi.html">STNT1W (scalar plus immediate):Contiguous store non-temporal words from vector (immediate index)</a>
  AMED_AARCH64_PAGE_stnt1w_z_p_br, //!< <a href="../target/aarch64/stnt1w_z_p_br.html">STNT1W (scalar plus scalar):Contiguous store non-temporal words from vector (scalar index)</a>
  AMED_AARCH64_PAGE_str_p_bi, //!< <a href="../target/aarch64/str_p_bi.html">STR (predicate):Store predicate register</a>
  AMED_AARCH64_PAGE_str_z_bi, //!< <a href="../target/aarch64/str_z_bi.html">STR (vector):Store vector register</a>
  AMED_AARCH64_PAGE_sub_z_p_zz, //!< <a href="../target/aarch64/sub_z_p_zz.html">SUB (vectors, predicated):Subtract vectors (predicated)</a>
  AMED_AARCH64_PAGE_sub_z_zi, //!< <a href="../target/aarch64/sub_z_zi.html">SUB (immediate):Subtract immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_sub_z_zz, //!< <a href="../target/aarch64/sub_z_zz.html">SUB (vectors, unpredicated):Subtract vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_subhnb_z_zz, //!< <a href="../target/aarch64/subhnb_z_zz.html">SUBHNB:Subtract narrow high part (bottom)</a>
  AMED_AARCH64_PAGE_subhnt_z_zz, //!< <a href="../target/aarch64/subhnt_z_zz.html">SUBHNT:Subtract narrow high part (top)</a>
  AMED_AARCH64_PAGE_subr_z_p_zz, //!< <a href="../target/aarch64/subr_z_p_zz.html">SUBR (vectors):Reversed subtract vectors (predicated)</a>
  AMED_AARCH64_PAGE_subr_z_zi, //!< <a href="../target/aarch64/subr_z_zi.html">SUBR (immediate):Reversed subtract from immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_sudot_z_zzzi, //!< <a href="../target/aarch64/sudot_z_zzzi.html">SUDOT:Signed by unsigned integer indexed dot product</a>
  AMED_AARCH64_PAGE_sunpkhi_z_z, //!< <a href="../target/aarch64/sunpkhi_z_z.html">SUNPKHI, SUNPKLO:Signed unpack and extend half of vector</a>
  AMED_AARCH64_PAGE_suqadd_z_p_zz, //!< <a href="../target/aarch64/suqadd_z_p_zz.html">SUQADD:Signed saturating addition of unsigned value</a>
  AMED_AARCH64_PAGE_sxtb_z_p_z, //!< <a href="../target/aarch64/sxtb_z_p_z.html">SXTB, SXTH, SXTW:Signed byte / halfword / word extend (predicated)</a>
  AMED_AARCH64_PAGE_tbl_z_zz, //!< <a href="../target/aarch64/tbl_z_zz.html">TBL:Programmable table lookup in one or two vector table (zeroing)</a>
  AMED_AARCH64_PAGE_tbx_z_zz, //!< <a href="../target/aarch64/tbx_z_zz.html">TBX:Programmable table lookup in single vector table (merging)</a>
  AMED_AARCH64_PAGE_trn1_p_pp, //!< <a href="../target/aarch64/trn1_p_pp.html">TRN1, TRN2 (predicates):Interleave even or odd elements from two predicates</a>
  AMED_AARCH64_PAGE_trn1_z_zz, //!< <a href="../target/aarch64/trn1_z_zz.html">TRN1, TRN2 (vectors):Interleave even or odd elements from two vectors</a>
  AMED_AARCH64_PAGE_uaba_z_zzz, //!< <a href="../target/aarch64/uaba_z_zzz.html">UABA:Unsigned absolute difference and accumulate</a>
  AMED_AARCH64_PAGE_uabalb_z_zzz, //!< <a href="../target/aarch64/uabalb_z_zzz.html">UABALB:Unsigned absolute difference and accumulate long (bottom)</a>
  AMED_AARCH64_PAGE_uabalt_z_zzz, //!< <a href="../target/aarch64/uabalt_z_zzz.html">UABALT:Unsigned absolute difference and accumulate long (top)</a>
  AMED_AARCH64_PAGE_uabd_z_p_zz, //!< <a href="../target/aarch64/uabd_z_p_zz.html">UABD:Unsigned absolute difference (predicated)</a>
  AMED_AARCH64_PAGE_uabdlb_z_zz, //!< <a href="../target/aarch64/uabdlb_z_zz.html">UABDLB:Unsigned absolute difference long (bottom)</a>
  AMED_AARCH64_PAGE_uabdlt_z_zz, //!< <a href="../target/aarch64/uabdlt_z_zz.html">UABDLT:Unsigned absolute difference long (top)</a>
  AMED_AARCH64_PAGE_uadalp_z_p_z, //!< <a href="../target/aarch64/uadalp_z_p_z.html">UADALP:Unsigned add and accumulate long pairwise</a>
  AMED_AARCH64_PAGE_uaddlb_z_zz, //!< <a href="../target/aarch64/uaddlb_z_zz.html">UADDLB:Unsigned add long (bottom)</a>
  AMED_AARCH64_PAGE_uaddlt_z_zz, //!< <a href="../target/aarch64/uaddlt_z_zz.html">UADDLT:Unsigned add long (top)</a>
  AMED_AARCH64_PAGE_uaddv_r_p_z, //!< <a href="../target/aarch64/uaddv_r_p_z.html">UADDV:Unsigned add reduction to scalar</a>
  AMED_AARCH64_PAGE_uaddwb_z_zz, //!< <a href="../target/aarch64/uaddwb_z_zz.html">UADDWB:Unsigned add wide (bottom)</a>
  AMED_AARCH64_PAGE_uaddwt_z_zz, //!< <a href="../target/aarch64/uaddwt_z_zz.html">UADDWT:Unsigned add wide (top)</a>
  AMED_AARCH64_PAGE_ucvtf_z_p_z, //!< <a href="../target/aarch64/ucvtf_z_p_z.html">UCVTF:Unsigned integer convert to floating-point (predicated)</a>
  AMED_AARCH64_PAGE_udiv_z_p_zz, //!< <a href="../target/aarch64/udiv_z_p_zz.html">UDIV:Unsigned divide (predicated)</a>
  AMED_AARCH64_PAGE_udivr_z_p_zz, //!< <a href="../target/aarch64/udivr_z_p_zz.html">UDIVR:Unsigned reversed divide (predicated)</a>
  AMED_AARCH64_PAGE_udot_z_zzz, //!< <a href="../target/aarch64/udot_z_zzz.html">UDOT (vectors):Unsigned integer dot product</a>
  AMED_AARCH64_PAGE_udot_z_zzzi, //!< <a href="../target/aarch64/udot_z_zzzi.html">UDOT (indexed):Unsigned integer indexed dot product</a>
  AMED_AARCH64_PAGE_uhadd_z_p_zz, //!< <a href="../target/aarch64/uhadd_z_p_zz.html">UHADD:Unsigned halving addition</a>
  AMED_AARCH64_PAGE_uhsub_z_p_zz, //!< <a href="../target/aarch64/uhsub_z_p_zz.html">UHSUB:Unsigned halving subtract</a>
  AMED_AARCH64_PAGE_uhsubr_z_p_zz, //!< <a href="../target/aarch64/uhsubr_z_p_zz.html">UHSUBR:Unsigned halving subtract reversed vectors</a>
  AMED_AARCH64_PAGE_umax_z_p_zz, //!< <a href="../target/aarch64/umax_z_p_zz.html">UMAX (vectors):Unsigned maximum vectors (predicated)</a>
  AMED_AARCH64_PAGE_umax_z_zi, //!< <a href="../target/aarch64/umax_z_zi.html">UMAX (immediate):Unsigned maximum with immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_umaxp_z_p_zz, //!< <a href="../target/aarch64/umaxp_z_p_zz.html">UMAXP:Unsigned maximum pairwise</a>
  AMED_AARCH64_PAGE_umaxv_r_p_z, //!< <a href="../target/aarch64/umaxv_r_p_z.html">UMAXV:Unsigned maximum reduction to scalar</a>
  AMED_AARCH64_PAGE_umin_z_p_zz, //!< <a href="../target/aarch64/umin_z_p_zz.html">UMIN (vectors):Unsigned minimum vectors (predicated)</a>
  AMED_AARCH64_PAGE_umin_z_zi, //!< <a href="../target/aarch64/umin_z_zi.html">UMIN (immediate):Unsigned minimum with immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_uminp_z_p_zz, //!< <a href="../target/aarch64/uminp_z_p_zz.html">UMINP:Unsigned minimum pairwise</a>
  AMED_AARCH64_PAGE_uminv_r_p_z, //!< <a href="../target/aarch64/uminv_r_p_z.html">UMINV:Unsigned minimum reduction to scalar</a>
  AMED_AARCH64_PAGE_umlalb_z_zzz, //!< <a href="../target/aarch64/umlalb_z_zzz.html">UMLALB (vectors):Unsigned multiply-add long to accumulator (bottom)</a>
  AMED_AARCH64_PAGE_umlalb_z_zzzi, //!< <a href="../target/aarch64/umlalb_z_zzzi.html">UMLALB (indexed):Unsigned multiply-add long to accumulator (bottom, indexed)</a>
  AMED_AARCH64_PAGE_umlalt_z_zzz, //!< <a href="../target/aarch64/umlalt_z_zzz.html">UMLALT (vectors):Unsigned multiply-add long to accumulator (top)</a>
  AMED_AARCH64_PAGE_umlalt_z_zzzi, //!< <a href="../target/aarch64/umlalt_z_zzzi.html">UMLALT (indexed):Unsigned multiply-add long to accumulator (top, indexed)</a>
  AMED_AARCH64_PAGE_umlslb_z_zzz, //!< <a href="../target/aarch64/umlslb_z_zzz.html">UMLSLB (vectors):Unsigned multiply-subtract long from accumulator (bottom)</a>
  AMED_AARCH64_PAGE_umlslb_z_zzzi, //!< <a href="../target/aarch64/umlslb_z_zzzi.html">UMLSLB (indexed):Unsigned multiply-subtract long from accumulator (bottom, indexed)</a>
  AMED_AARCH64_PAGE_umlslt_z_zzz, //!< <a href="../target/aarch64/umlslt_z_zzz.html">UMLSLT (vectors):Unsigned multiply-subtract long from accumulator (top)</a>
  AMED_AARCH64_PAGE_umlslt_z_zzzi, //!< <a href="../target/aarch64/umlslt_z_zzzi.html">UMLSLT (indexed):Unsigned multiply-subtract long from accumulator (top, indexed)</a>
  AMED_AARCH64_PAGE_ummla_z_zzz, //!< <a href="../target/aarch64/ummla_z_zzz.html">UMMLA:Unsigned integer matrix multiply-accumulate</a>
  AMED_AARCH64_PAGE_umulh_z_p_zz, //!< <a href="../target/aarch64/umulh_z_p_zz.html">UMULH (predicated):Unsigned multiply returning high half (predicated)</a>
  AMED_AARCH64_PAGE_umulh_z_zz, //!< <a href="../target/aarch64/umulh_z_zz.html">UMULH (unpredicated):Unsigned multiply returning high half (unpredicated)</a>
  AMED_AARCH64_PAGE_umullb_z_zz, //!< <a href="../target/aarch64/umullb_z_zz.html">UMULLB (vectors):Unsigned multiply long (bottom)</a>
  AMED_AARCH64_PAGE_umullb_z_zzi, //!< <a href="../target/aarch64/umullb_z_zzi.html">UMULLB (indexed):Unsigned multiply long (bottom, indexed)</a>
  AMED_AARCH64_PAGE_umullt_z_zz, //!< <a href="../target/aarch64/umullt_z_zz.html">UMULLT (vectors):Unsigned multiply long (top)</a>
  AMED_AARCH64_PAGE_umullt_z_zzi, //!< <a href="../target/aarch64/umullt_z_zzi.html">UMULLT (indexed):Unsigned multiply long (top, indexed)</a>
  AMED_AARCH64_PAGE_uqadd_z_p_zz, //!< <a href="../target/aarch64/uqadd_z_p_zz.html">UQADD (vectors, predicated):Unsigned saturating addition (predicated)</a>
  AMED_AARCH64_PAGE_uqadd_z_zi, //!< <a href="../target/aarch64/uqadd_z_zi.html">UQADD (immediate):Unsigned saturating add immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_uqadd_z_zz, //!< <a href="../target/aarch64/uqadd_z_zz.html">UQADD (vectors, unpredicated):Unsigned saturating add vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_uqdecb_r_rs, //!< <a href="../target/aarch64/uqdecb_r_rs.html">UQDECB:Unsigned saturating decrement scalar by multiple of 8-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqdecd_r_rs, //!< <a href="../target/aarch64/uqdecd_r_rs.html">UQDECD (scalar):Unsigned saturating decrement scalar by multiple of 64-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqdecd_z_zs, //!< <a href="../target/aarch64/uqdecd_z_zs.html">UQDECD (vector):Unsigned saturating decrement vector by multiple of 64-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqdech_r_rs, //!< <a href="../target/aarch64/uqdech_r_rs.html">UQDECH (scalar):Unsigned saturating decrement scalar by multiple of 16-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqdech_z_zs, //!< <a href="../target/aarch64/uqdech_z_zs.html">UQDECH (vector):Unsigned saturating decrement vector by multiple of 16-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqdecp_r_p_r, //!< <a href="../target/aarch64/uqdecp_r_p_r.html">UQDECP (scalar):Unsigned saturating decrement scalar by count of true predicate elements</a>
  AMED_AARCH64_PAGE_uqdecp_z_p_z, //!< <a href="../target/aarch64/uqdecp_z_p_z.html">UQDECP (vector):Unsigned saturating decrement vector by count of true predicate elements</a>
  AMED_AARCH64_PAGE_uqdecw_r_rs, //!< <a href="../target/aarch64/uqdecw_r_rs.html">UQDECW (scalar):Unsigned saturating decrement scalar by multiple of 32-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqdecw_z_zs, //!< <a href="../target/aarch64/uqdecw_z_zs.html">UQDECW (vector):Unsigned saturating decrement vector by multiple of 32-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqincb_r_rs, //!< <a href="../target/aarch64/uqincb_r_rs.html">UQINCB:Unsigned saturating increment scalar by multiple of 8-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqincd_r_rs, //!< <a href="../target/aarch64/uqincd_r_rs.html">UQINCD (scalar):Unsigned saturating increment scalar by multiple of 64-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqincd_z_zs, //!< <a href="../target/aarch64/uqincd_z_zs.html">UQINCD (vector):Unsigned saturating increment vector by multiple of 64-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqinch_r_rs, //!< <a href="../target/aarch64/uqinch_r_rs.html">UQINCH (scalar):Unsigned saturating increment scalar by multiple of 16-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqinch_z_zs, //!< <a href="../target/aarch64/uqinch_z_zs.html">UQINCH (vector):Unsigned saturating increment vector by multiple of 16-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqincp_r_p_r, //!< <a href="../target/aarch64/uqincp_r_p_r.html">UQINCP (scalar):Unsigned saturating increment scalar by count of true predicate elements</a>
  AMED_AARCH64_PAGE_uqincp_z_p_z, //!< <a href="../target/aarch64/uqincp_z_p_z.html">UQINCP (vector):Unsigned saturating increment vector by count of true predicate elements</a>
  AMED_AARCH64_PAGE_uqincw_r_rs, //!< <a href="../target/aarch64/uqincw_r_rs.html">UQINCW (scalar):Unsigned saturating increment scalar by multiple of 32-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqincw_z_zs, //!< <a href="../target/aarch64/uqincw_z_zs.html">UQINCW (vector):Unsigned saturating increment vector by multiple of 32-bit predicate constraint element count</a>
  AMED_AARCH64_PAGE_uqrshl_z_p_zz, //!< <a href="../target/aarch64/uqrshl_z_p_zz.html">UQRSHL:Unsigned saturating rounding shift left by vector (predicated)</a>
  AMED_AARCH64_PAGE_uqrshlr_z_p_zz, //!< <a href="../target/aarch64/uqrshlr_z_p_zz.html">UQRSHLR:Unsigned saturating rounding shift left reversed vectors (predicated)</a>
  AMED_AARCH64_PAGE_uqrshrnb_z_zi, //!< <a href="../target/aarch64/uqrshrnb_z_zi.html">UQRSHRNB:Unsigned saturating rounding shift right narrow by immediate (bottom)</a>
  AMED_AARCH64_PAGE_uqrshrnt_z_zi, //!< <a href="../target/aarch64/uqrshrnt_z_zi.html">UQRSHRNT:Unsigned saturating rounding shift right narrow by immediate (top)</a>
  AMED_AARCH64_PAGE_uqshl_z_p_zi, //!< <a href="../target/aarch64/uqshl_z_p_zi.html">UQSHL (immediate):Unsigned saturating shift left by immediate</a>
  AMED_AARCH64_PAGE_uqshl_z_p_zz, //!< <a href="../target/aarch64/uqshl_z_p_zz.html">UQSHL (vectors):Unsigned saturating shift left by vector (predicated)</a>
  AMED_AARCH64_PAGE_uqshlr_z_p_zz, //!< <a href="../target/aarch64/uqshlr_z_p_zz.html">UQSHLR:Unsigned saturating shift left reversed vectors (predicated)</a>
  AMED_AARCH64_PAGE_uqshrnb_z_zi, //!< <a href="../target/aarch64/uqshrnb_z_zi.html">UQSHRNB:Unsigned saturating shift right narrow by immediate (bottom)</a>
  AMED_AARCH64_PAGE_uqshrnt_z_zi, //!< <a href="../target/aarch64/uqshrnt_z_zi.html">UQSHRNT:Unsigned saturating shift right narrow by immediate (top)</a>
  AMED_AARCH64_PAGE_uqsub_z_p_zz, //!< <a href="../target/aarch64/uqsub_z_p_zz.html">UQSUB (vectors, predicated):Unsigned saturating subtraction (predicated)</a>
  AMED_AARCH64_PAGE_uqsub_z_zi, //!< <a href="../target/aarch64/uqsub_z_zi.html">UQSUB (immediate):Unsigned saturating subtract immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_uqsub_z_zz, //!< <a href="../target/aarch64/uqsub_z_zz.html">UQSUB (vectors, unpredicated):Unsigned saturating subtract vectors (unpredicated)</a>
  AMED_AARCH64_PAGE_uqsubr_z_p_zz, //!< <a href="../target/aarch64/uqsubr_z_p_zz.html">UQSUBR:Unsigned saturating subtraction reversed vectors (predicated)</a>
  AMED_AARCH64_PAGE_uqxtnb_z_zz, //!< <a href="../target/aarch64/uqxtnb_z_zz.html">UQXTNB:Unsigned saturating extract narrow (bottom)</a>
  AMED_AARCH64_PAGE_uqxtnt_z_zz, //!< <a href="../target/aarch64/uqxtnt_z_zz.html">UQXTNT:Unsigned saturating extract narrow (top)</a>
  AMED_AARCH64_PAGE_urecpe_z_p_z, //!< <a href="../target/aarch64/urecpe_z_p_z.html">URECPE:Unsigned reciprocal estimate (predicated)</a>
  AMED_AARCH64_PAGE_urhadd_z_p_zz, //!< <a href="../target/aarch64/urhadd_z_p_zz.html">URHADD:Unsigned rounding halving addition</a>
  AMED_AARCH64_PAGE_urshl_z_p_zz, //!< <a href="../target/aarch64/urshl_z_p_zz.html">URSHL:Unsigned rounding shift left by vector (predicated)</a>
  AMED_AARCH64_PAGE_urshlr_z_p_zz, //!< <a href="../target/aarch64/urshlr_z_p_zz.html">URSHLR:Unsigned rounding shift left reversed vectors (predicated)</a>
  AMED_AARCH64_PAGE_urshr_z_p_zi, //!< <a href="../target/aarch64/urshr_z_p_zi.html">URSHR:Unsigned rounding shift right by immediate</a>
  AMED_AARCH64_PAGE_ursqrte_z_p_z, //!< <a href="../target/aarch64/ursqrte_z_p_z.html">URSQRTE:Unsigned reciprocal square root estimate (predicated)</a>
  AMED_AARCH64_PAGE_ursra_z_zi, //!< <a href="../target/aarch64/ursra_z_zi.html">URSRA:Unsigned rounding shift right and accumulate (immediate)</a>
  AMED_AARCH64_PAGE_usdot_z_zzz, //!< <a href="../target/aarch64/usdot_z_zzz.html">USDOT (vectors):Unsigned by signed integer dot product</a>
  AMED_AARCH64_PAGE_usdot_z_zzzi, //!< <a href="../target/aarch64/usdot_z_zzzi.html">USDOT (indexed):Unsigned by signed integer indexed dot product</a>
  AMED_AARCH64_PAGE_ushllb_z_zi, //!< <a href="../target/aarch64/ushllb_z_zi.html">USHLLB:Unsigned shift left long by immediate (bottom)</a>
  AMED_AARCH64_PAGE_ushllt_z_zi, //!< <a href="../target/aarch64/ushllt_z_zi.html">USHLLT:Unsigned shift left long by immediate (top)</a>
  AMED_AARCH64_PAGE_usmmla_z_zzz, //!< <a href="../target/aarch64/usmmla_z_zzz.html">USMMLA:Unsigned by signed integer matrix multiply-accumulate</a>
  AMED_AARCH64_PAGE_usqadd_z_p_zz, //!< <a href="../target/aarch64/usqadd_z_p_zz.html">USQADD:Unsigned saturating addition of signed value</a>
  AMED_AARCH64_PAGE_usra_z_zi, //!< <a href="../target/aarch64/usra_z_zi.html">USRA:Unsigned shift right and accumulate (immediate)</a>
  AMED_AARCH64_PAGE_usublb_z_zz, //!< <a href="../target/aarch64/usublb_z_zz.html">USUBLB:Unsigned subtract long (bottom)</a>
  AMED_AARCH64_PAGE_usublt_z_zz, //!< <a href="../target/aarch64/usublt_z_zz.html">USUBLT:Unsigned subtract long (top)</a>
  AMED_AARCH64_PAGE_usubwb_z_zz, //!< <a href="../target/aarch64/usubwb_z_zz.html">USUBWB:Unsigned subtract wide (bottom)</a>
  AMED_AARCH64_PAGE_usubwt_z_zz, //!< <a href="../target/aarch64/usubwt_z_zz.html">USUBWT:Unsigned subtract wide (top)</a>
  AMED_AARCH64_PAGE_uunpkhi_z_z, //!< <a href="../target/aarch64/uunpkhi_z_z.html">UUNPKHI, UUNPKLO:Unsigned unpack and extend half of vector</a>
  AMED_AARCH64_PAGE_uxtb_z_p_z, //!< <a href="../target/aarch64/uxtb_z_p_z.html">UXTB, UXTH, UXTW:Unsigned byte / halfword / word extend (predicated)</a>
  AMED_AARCH64_PAGE_uzp1_p_pp, //!< <a href="../target/aarch64/uzp1_p_pp.html">UZP1, UZP2 (predicates):Concatenate even or odd elements from two predicates</a>
  AMED_AARCH64_PAGE_uzp1_z_zz, //!< <a href="../target/aarch64/uzp1_z_zz.html">UZP1, UZP2 (vectors):Concatenate even or odd elements from two vectors</a>
  AMED_AARCH64_PAGE_whilege_p_p_rr, //!< <a href="../target/aarch64/whilege_p_p_rr.html">WHILEGE:While decrementing signed scalar greater than or equal to scalar</a>
  AMED_AARCH64_PAGE_whilegt_p_p_rr, //!< <a href="../target/aarch64/whilegt_p_p_rr.html">WHILEGT:While decrementing signed scalar greater than scalar</a>
  AMED_AARCH64_PAGE_whilehi_p_p_rr, //!< <a href="../target/aarch64/whilehi_p_p_rr.html">WHILEHI:While decrementing unsigned scalar higher than scalar</a>
  AMED_AARCH64_PAGE_whilehs_p_p_rr, //!< <a href="../target/aarch64/whilehs_p_p_rr.html">WHILEHS:While decrementing unsigned scalar higher or same as scalar</a>
  AMED_AARCH64_PAGE_whilele_p_p_rr, //!< <a href="../target/aarch64/whilele_p_p_rr.html">WHILELE:While incrementing signed scalar less than or equal to scalar</a>
  AMED_AARCH64_PAGE_whilelo_p_p_rr, //!< <a href="../target/aarch64/whilelo_p_p_rr.html">WHILELO:While incrementing unsigned scalar lower than scalar</a>
  AMED_AARCH64_PAGE_whilels_p_p_rr, //!< <a href="../target/aarch64/whilels_p_p_rr.html">WHILELS:While incrementing unsigned scalar lower or same as scalar</a>
  AMED_AARCH64_PAGE_whilelt_p_p_rr, //!< <a href="../target/aarch64/whilelt_p_p_rr.html">WHILELT:While incrementing signed scalar less than scalar</a>
  AMED_AARCH64_PAGE_whilerw_p_rr, //!< <a href="../target/aarch64/whilerw_p_rr.html">WHILERW:While free of read-after-write conflicts</a>
  AMED_AARCH64_PAGE_whilewr_p_rr, //!< <a href="../target/aarch64/whilewr_p_rr.html">WHILEWR:While free of write-after-read/write conflicts</a>
  AMED_AARCH64_PAGE_wrffr_f_p, //!< <a href="../target/aarch64/wrffr_f_p.html">WRFFR:Write the first-fault register</a>
  AMED_AARCH64_PAGE_xar_z_zzi, //!< <a href="../target/aarch64/xar_z_zzi.html">XAR:Bitwise exclusive OR and rotate right by immediate</a>
  AMED_AARCH64_PAGE_zip1_p_pp, //!< <a href="../target/aarch64/zip1_p_pp.html">ZIP1, ZIP2 (predicates):Interleave elements from two half predicates</a>
  AMED_AARCH64_PAGE_zip1_z_zz, //!< <a href="../target/aarch64/zip1_z_zz.html">ZIP1, ZIP2 (vectors):Interleave elements from two half vectors</a>
  AMED_AARCH64_PAGE_BIC_and_z_zi, //!< <a href="../target/aarch64/BIC_and_z_zi.html">BIC (immediate):Bitwise clear bits using immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_CMPLE_cmpeq_p_p_zz, //!< <a href="../target/aarch64/CMPLE_cmpeq_p_p_zz.html">CMPLE (vectors):Compare signed less than or equal to vector, setting the condition flags</a>
  AMED_AARCH64_PAGE_CMPLO_cmpeq_p_p_zz, //!< <a href="../target/aarch64/CMPLO_cmpeq_p_p_zz.html">CMPLO (vectors):Compare unsigned lower than vector, setting the condition flags</a>
  AMED_AARCH64_PAGE_CMPLS_cmpeq_p_p_zz, //!< <a href="../target/aarch64/CMPLS_cmpeq_p_p_zz.html">CMPLS (vectors):Compare unsigned lower or same as vector, setting the condition flags</a>
  AMED_AARCH64_PAGE_CMPLT_cmpeq_p_p_zz, //!< <a href="../target/aarch64/CMPLT_cmpeq_p_p_zz.html">CMPLT (vectors):Compare signed less than vector, setting the condition flags</a>
  AMED_AARCH64_PAGE_EON_eor_z_zi, //!< <a href="../target/aarch64/EON_eor_z_zi.html">EON:Bitwise exclusive OR with inverted immediate (unpredicated)</a>
  AMED_AARCH64_PAGE_FACLE_facge_p_p_zz, //!< <a href="../target/aarch64/FACLE_facge_p_p_zz.html">FACLE:Floating-point absolute compare less than or equal</a>
  AMED_AARCH64_PAGE_FACLT_facge_p_p_zz, //!< <a href="../target/aarch64/FACLT_facge_p_p_zz.html">FACLT:Floating-point absolute compare less than</a>
  AMED_AARCH64_PAGE_FCMLE_fcmeq_p_p_zz, //!< <a href="../target/aarch64/FCMLE_fcmeq_p_p_zz.html">FCMLE (vectors):Floating-point compare less than or equal to vector</a>
  AMED_AARCH64_PAGE_FCMLT_fcmeq_p_p_zz, //!< <a href="../target/aarch64/FCMLT_fcmeq_p_p_zz.html">FCMLT (vectors):Floating-point compare less than vector</a>
  AMED_AARCH64_PAGE_FMOV_cpy_z_p_i, //!< <a href="../target/aarch64/FMOV_cpy_z_p_i.html">FMOV (zero, predicated):Move floating-point +0.0 to vector elements (predicated)</a>
  AMED_AARCH64_PAGE_FMOV_dup_z_i, //!< <a href="../target/aarch64/FMOV_dup_z_i.html">FMOV (zero, unpredicated):Move floating-point +0.0 to vector elements (unpredicated)</a>
  AMED_AARCH64_PAGE_FMOV_fcpy_z_p_i, //!< <a href="../target/aarch64/FMOV_fcpy_z_p_i.html">FMOV (immediate, predicated):Move 8-bit floating-point immediate to vector elements (predicated)</a>
  AMED_AARCH64_PAGE_FMOV_fdup_z_i, //!< <a href="../target/aarch64/FMOV_fdup_z_i.html">FMOV (immediate, unpredicated):Move 8-bit floating-point immediate to vector elements (unpredicated)</a>
  AMED_AARCH64_PAGE_MOV_and_p_p_pp, //!< <a href="../target/aarch64/MOV_and_p_p_pp.html">MOV (predicate, predicated, zeroing):Move predicates (zeroing)</a>
  AMED_AARCH64_PAGE_MOV_cpy_z_o_i, //!< <a href="../target/aarch64/MOV_cpy_z_o_i.html">MOV (immediate, predicated, zeroing):Move signed integer immediate to vector elements (zeroing)</a>
  AMED_AARCH64_PAGE_MOV_cpy_z_p_i, //!< <a href="../target/aarch64/MOV_cpy_z_p_i.html">MOV (immediate, predicated, merging):Move signed integer immediate to vector elements (merging)</a>
  AMED_AARCH64_PAGE_MOV_cpy_z_p_r, //!< <a href="../target/aarch64/MOV_cpy_z_p_r.html">MOV (scalar, predicated):Move general-purpose register to vector elements (predicated)</a>
  AMED_AARCH64_PAGE_MOV_cpy_z_p_v, //!< <a href="../target/aarch64/MOV_cpy_z_p_v.html">MOV (SIMD&FP scalar, predicated):Move SIMD&FP scalar register to vector elements (predicated)</a>
  AMED_AARCH64_PAGE_MOV_dup_z_i, //!< <a href="../target/aarch64/MOV_dup_z_i.html">MOV (immediate, unpredicated):Move signed immediate to vector elements (unpredicated)</a>
  AMED_AARCH64_PAGE_MOV_dup_z_r, //!< <a href="../target/aarch64/MOV_dup_z_r.html">MOV (scalar, unpredicated):Move general-purpose register to vector elements (unpredicated)</a>
  AMED_AARCH64_PAGE_MOV_dup_z_zi, //!< <a href="../target/aarch64/MOV_dup_z_zi.html">MOV (SIMD&FP scalar, unpredicated):Move indexed element or SIMD&FP scalar to vector (unpredicated)</a>
  AMED_AARCH64_PAGE_MOV_dupm_z_i, //!< <a href="../target/aarch64/MOV_dupm_z_i.html">MOV (bitmask immediate):Move logical bitmask immediate to vector (unpredicated)</a>
  AMED_AARCH64_PAGE_MOV_orr_p_p_pp, //!< <a href="../target/aarch64/MOV_orr_p_p_pp.html">MOV (predicate, unpredicated):Move predicate (unpredicated)</a>
  AMED_AARCH64_PAGE_MOV_orr_z_zz, //!< <a href="../target/aarch64/MOV_orr_z_zz.html">MOV (vector, unpredicated):Move vector register (unpredicated)</a>
  AMED_AARCH64_PAGE_MOV_sel_p_p_pp, //!< <a href="../target/aarch64/MOV_sel_p_p_pp.html">MOV (predicate, predicated, merging):Move predicates (merging)</a>
  AMED_AARCH64_PAGE_MOV_sel_z_p_zz, //!< <a href="../target/aarch64/MOV_sel_z_p_zz.html">MOV (vector, predicated):Move vector elements (predicated)</a>
  AMED_AARCH64_PAGE_MOVS_and_p_p_pp, //!< <a href="../target/aarch64/MOVS_and_p_p_pp.html">MOVS (predicated):Move predicates (zeroing), setting the condition flags</a>
  AMED_AARCH64_PAGE_MOVS_orr_p_p_pp, //!< <a href="../target/aarch64/MOVS_orr_p_p_pp.html">MOVS (unpredicated):Move predicate (unpredicated), setting the condition flags</a>
  AMED_AARCH64_PAGE_NOT_eor_p_p_pp, //!< <a href="../target/aarch64/NOT_eor_p_p_pp.html">NOT (predicate):Bitwise invert predicate</a>
  AMED_AARCH64_PAGE_NOTS_eor_p_p_pp, //!< <a href="../target/aarch64/NOTS_eor_p_p_pp.html">NOTS:Bitwise invert predicate, setting the condition flags</a>
  AMED_AARCH64_PAGE_ORN_orr_z_zi, //!< <a href="../target/aarch64/ORN_orr_z_zi.html">ORN (immediate):Bitwise inclusive OR with inverted immediate (unpredicated)</a>
} amed_aarch64_page;

#define AMED_AARCH64_EXCEPTION_MAX_TEXT_LENGTH (19 + 1)

typedef enum _amed_aarch64_exception
{
  AMED_AARCH64_EXCEPTION_NONE,
  AMED_AARCH64_EXCEPTION_ADVSIMDFPACCESSTRAP,
  AMED_AARCH64_EXCEPTION_ALIGNMENT,
  AMED_AARCH64_EXCEPTION_DATAABORT,
  AMED_AARCH64_EXCEPTION_ERETTRAP,
  AMED_AARCH64_EXCEPTION_FP,
  AMED_AARCH64_EXCEPTION_HYPERVISORCALL,
  AMED_AARCH64_EXCEPTION_MONITORCALL,
  AMED_AARCH64_EXCEPTION_PACFAIL,
  AMED_AARCH64_EXCEPTION_PACTRAP,
  AMED_AARCH64_EXCEPTION_SPALIGNMENT,
  AMED_AARCH64_EXCEPTION_SVEACCESSTRAP,
  AMED_AARCH64_EXCEPTION_SOFTWAREBREAKPOINT,
  AMED_AARCH64_EXCEPTION_SUPERVISORCALL,
  AMED_AARCH64_EXCEPTION_TSTARTACCESSTRAP,
  AMED_AARCH64_EXCEPTION_UNCATEGORIZED,
  AMED_AARCH64_EXCEPTION_WFXTRAP,
} amed_aarch64_exception;

#define AMED_AARCH64_EXTENSION_MAX_TEXT_LENGTH (23 + 1)

typedef enum _amed_aarch64_extension
{
  AMED_AARCH64_EXTENSION_NONE,
  AMED_AARCH64_EXTENSION_AES,
  AMED_AARCH64_EXTENSION_ATOMIC,
  AMED_AARCH64_EXTENSION_BF16,
  AMED_AARCH64_EXTENSION_BTI,
  AMED_AARCH64_EXTENSION_BIT128PMULL,
  AMED_AARCH64_EXTENSION_CRC,
  AMED_AARCH64_EXTENSION_DGH,
  AMED_AARCH64_EXTENSION_DIT,
  AMED_AARCH64_EXTENSION_DOTP,
  AMED_AARCH64_EXTENSION_FCADD,
  AMED_AARCH64_EXTENSION_FJCVTZS,
  AMED_AARCH64_EXTENSION_FP16,
  AMED_AARCH64_EXTENSION_FP16MULNOROUNDINGTOFP32,
  AMED_AARCH64_EXTENSION_FLAGFORMAT,
  AMED_AARCH64_EXTENSION_FLAGMANIPULATE,
  AMED_AARCH64_EXTENSION_FRINT,
  AMED_AARCH64_EXTENSION_INT8MATMUL,
  AMED_AARCH64_EXTENSION_MTE,
  AMED_AARCH64_EXTENSION_PAC,
  AMED_AARCH64_EXTENSION_PAN,
  AMED_AARCH64_EXTENSION_QRDMLAH,
  AMED_AARCH64_EXTENSION_RAS,
  AMED_AARCH64_EXTENSION_SB,
  AMED_AARCH64_EXTENSION_SHA1,
  AMED_AARCH64_EXTENSION_SHA256,
  AMED_AARCH64_EXTENSION_SHA3,
  AMED_AARCH64_EXTENSION_SHA512,
  AMED_AARCH64_EXTENSION_SM3,
  AMED_AARCH64_EXTENSION_SM4,
  AMED_AARCH64_EXTENSION_SSBS,
  AMED_AARCH64_EXTENSION_SVE,
  AMED_AARCH64_EXTENSION_SVE2,
  AMED_AARCH64_EXTENSION_SVE2AES,
  AMED_AARCH64_EXTENSION_SVE2BITPERM,
  AMED_AARCH64_EXTENSION_SVE2PMULL128,
  AMED_AARCH64_EXTENSION_SVE2SHA3,
  AMED_AARCH64_EXTENSION_SVE2SM4,
  AMED_AARCH64_EXTENSION_SVEFP32MATMUL,
  AMED_AARCH64_EXTENSION_SVEFP64MATMUL,
  AMED_AARCH64_EXTENSION_UAO,
} amed_aarch64_extension;

#define AMED_AARCH64_ICLASS_MAX_TEXT_LENGTH (35 + 1)

typedef enum _amed_aarch64_iclass
{
  AMED_AARCH64_ICLASS_NONE,
  AMED_AARCH64_ICLASS_invalid, //!< invalid
  AMED_AARCH64_ICLASS_addsub_carry, //!< Add/subtract (with carry)
  AMED_AARCH64_ICLASS_addsub_ext, //!< Add/subtract (extended register)
  AMED_AARCH64_ICLASS_addsub_imm, //!< Add/subtract (immediate)
  AMED_AARCH64_ICLASS_addsub_immtags, //!< Add/subtract (immediate, with tags)
  AMED_AARCH64_ICLASS_addsub_shift, //!< Add/subtract (shifted register)
  AMED_AARCH64_ICLASS_barriers, //!< Barriers
  AMED_AARCH64_ICLASS_bitfield, //!< Bitfield
  AMED_AARCH64_ICLASS_branch_imm, //!< Unconditional branch (immediate)
  AMED_AARCH64_ICLASS_branch_reg, //!< Unconditional branch (register)
  AMED_AARCH64_ICLASS_compbranch, //!< Compare and branch (immediate)
  AMED_AARCH64_ICLASS_condbranch, //!< Conditional branch (immediate)
  AMED_AARCH64_ICLASS_condcmp_imm, //!< Conditional compare (immediate)
  AMED_AARCH64_ICLASS_condcmp_reg, //!< Conditional compare (register)
  AMED_AARCH64_ICLASS_condsel, //!< Conditional select
  AMED_AARCH64_ICLASS_dp_1src, //!< Data-processing (1 source)
  AMED_AARCH64_ICLASS_dp_2src, //!< Data-processing (2 source)
  AMED_AARCH64_ICLASS_dp_3src, //!< Data-processing (3 source)
  AMED_AARCH64_ICLASS_exception, //!< Exception generation
  AMED_AARCH64_ICLASS_extract, //!< Extract
  AMED_AARCH64_ICLASS_hints, //!< Hints
  AMED_AARCH64_ICLASS_ldapstl_unscaled, //!< LDAPR/STLR (unscaled immediate)
  AMED_AARCH64_ICLASS_ldst_pac, //!< Load/store register (pac)
  AMED_AARCH64_ICLASS_ldst_unpriv, //!< Load/store register (unprivileged)
  AMED_AARCH64_ICLASS_ldstexcl, //!< Load/store exclusive
  AMED_AARCH64_ICLASS_ldsttags, //!< Load/store memory tags
  AMED_AARCH64_ICLASS_log_imm, //!< Logical (immediate)
  AMED_AARCH64_ICLASS_log_shift, //!< Logical (shifted register)
  AMED_AARCH64_ICLASS_memop, //!< Atomic memory operations
  AMED_AARCH64_ICLASS_movewide, //!< Move wide (immediate)
  AMED_AARCH64_ICLASS_pcreladdr, //!< PC-rel. addressing
  AMED_AARCH64_ICLASS_perm_undef, //!< Reserved
  AMED_AARCH64_ICLASS_pstate, //!< PSTATE
  AMED_AARCH64_ICLASS_rmif, //!< Rotate right into flags
  AMED_AARCH64_ICLASS_setf, //!< Evaluate into flags
  AMED_AARCH64_ICLASS_systeminstrs, //!< System instructions
  AMED_AARCH64_ICLASS_systemmove, //!< System register move
  AMED_AARCH64_ICLASS_systemresult, //!< System with result
  AMED_AARCH64_ICLASS_testbranch, //!< Test and branch (immediate)
  AMED_AARCH64_ICLASS_asimdall, //!< Advanced SIMD across lanes
  AMED_AARCH64_ICLASS_asimddiff, //!< Advanced SIMD three different
  AMED_AARCH64_ICLASS_asimdelem, //!< Advanced SIMD vector x indexed element
  AMED_AARCH64_ICLASS_asimdext, //!< Advanced SIMD extract
  AMED_AARCH64_ICLASS_asimdimm, //!< Advanced SIMD modified immediate
  AMED_AARCH64_ICLASS_asimdins, //!< Advanced SIMD copy
  AMED_AARCH64_ICLASS_asimdmisc, //!< Advanced SIMD two-register miscellaneous
  AMED_AARCH64_ICLASS_asimdmiscfp16, //!< Advanced SIMD two-register miscellaneous (FP16)
  AMED_AARCH64_ICLASS_asimdperm, //!< Advanced SIMD permute
  AMED_AARCH64_ICLASS_asimdsame, //!< Advanced SIMD three same
  AMED_AARCH64_ICLASS_asimdsame2, //!< Advanced SIMD three-register extension
  AMED_AARCH64_ICLASS_asimdsamefp16, //!< Advanced SIMD three same (FP16)
  AMED_AARCH64_ICLASS_asimdshf, //!< Advanced SIMD shift by immediate
  AMED_AARCH64_ICLASS_asimdtbl, //!< Advanced SIMD table lookup
  AMED_AARCH64_ICLASS_asisddiff, //!< Advanced SIMD scalar three different
  AMED_AARCH64_ICLASS_asisdelem, //!< Advanced SIMD scalar x indexed element
  AMED_AARCH64_ICLASS_asisdlse, //!< Advanced SIMD load/store multiple structures
  AMED_AARCH64_ICLASS_asisdlsep, //!< Advanced SIMD load/store multiple structures (post-indexed)
  AMED_AARCH64_ICLASS_asisdlso, //!< Advanced SIMD load/store single structure
  AMED_AARCH64_ICLASS_asisdlsop, //!< Advanced SIMD load/store single structure (post-indexed)
  AMED_AARCH64_ICLASS_asisdmisc, //!< Advanced SIMD scalar two-register miscellaneous
  AMED_AARCH64_ICLASS_asisdmiscfp16, //!< Advanced SIMD scalar two-register miscellaneous FP16
  AMED_AARCH64_ICLASS_asisdone, //!< Advanced SIMD scalar copy
  AMED_AARCH64_ICLASS_asisdpair, //!< Advanced SIMD scalar pairwise
  AMED_AARCH64_ICLASS_asisdsame, //!< Advanced SIMD scalar three same
  AMED_AARCH64_ICLASS_asisdsame2, //!< Advanced SIMD scalar three same extra
  AMED_AARCH64_ICLASS_asisdsamefp16, //!< Advanced SIMD scalar three same FP16
  AMED_AARCH64_ICLASS_asisdshf, //!< Advanced SIMD scalar shift by immediate
  AMED_AARCH64_ICLASS_crypto3_imm2, //!< Cryptographic three-register, imm2
  AMED_AARCH64_ICLASS_crypto3_imm6, //!< Cryptographic three-register, imm6
  AMED_AARCH64_ICLASS_crypto4, //!< Cryptographic four-register
  AMED_AARCH64_ICLASS_cryptoaes, //!< Cryptographic AES
  AMED_AARCH64_ICLASS_cryptosha2, //!< Cryptographic two-register SHA
  AMED_AARCH64_ICLASS_cryptosha3, //!< Cryptographic three-register SHA
  AMED_AARCH64_ICLASS_cryptosha512_2, //!< Cryptographic two-register SHA 512
  AMED_AARCH64_ICLASS_cryptosha512_3, //!< Cryptographic three-register SHA 512
  AMED_AARCH64_ICLASS_float2fix, //!< Conversion between floating-point and fixed-point
  AMED_AARCH64_ICLASS_float2int, //!< Conversion between floating-point and integer
  AMED_AARCH64_ICLASS_floatccmp, //!< Floating-point conditional compare
  AMED_AARCH64_ICLASS_floatcmp, //!< Floating-point compare
  AMED_AARCH64_ICLASS_floatdp1, //!< Floating-point data-processing (1 source)
  AMED_AARCH64_ICLASS_floatdp2, //!< Floating-point data-processing (2 source)
  AMED_AARCH64_ICLASS_floatdp3, //!< Floating-point data-processing (3 source)
  AMED_AARCH64_ICLASS_floatimm, //!< Floating-point immediate
  AMED_AARCH64_ICLASS_floatsel, //!< Floating-point conditional select
  AMED_AARCH64_ICLASS_ldst_immpost, //!< Load/store register (immediate post-indexed)
  AMED_AARCH64_ICLASS_ldst_immpre, //!< Load/store register (immediate pre-indexed)
  AMED_AARCH64_ICLASS_ldst_pos, //!< Load/store register (unsigned immediate)
  AMED_AARCH64_ICLASS_ldst_regoff, //!< Load/store register (register offset)
  AMED_AARCH64_ICLASS_ldst_unscaled, //!< Load/store register (unscaled immediate)
  AMED_AARCH64_ICLASS_ldstnapair_offs, //!< Load/store no-allocate pair (offset)
  AMED_AARCH64_ICLASS_ldstpair_off, //!< Load/store register pair (offset)
  AMED_AARCH64_ICLASS_ldstpair_post, //!< Load/store register pair (post-indexed)
  AMED_AARCH64_ICLASS_ldstpair_pre, //!< Load/store register pair (pre-indexed)
  AMED_AARCH64_ICLASS_loadlit, //!< Load register (literal)
  AMED_AARCH64_ICLASS_sve_crypto_binary_const, //!< SVE2 crypto constructive binary operations
  AMED_AARCH64_ICLASS_sve_crypto_binary_dest, //!< SVE2 crypto destructive binary operations
  AMED_AARCH64_ICLASS_sve_crypto_unary, //!< SVE2 crypto unary operations
  AMED_AARCH64_ICLASS_sve_fp_2op_i_p_zds, //!< SVE floating-point arithmetic with immediate (predicated)
  AMED_AARCH64_ICLASS_sve_fp_2op_p_pd, //!< SVE floating-point compare with zero
  AMED_AARCH64_ICLASS_sve_fp_2op_p_vd, //!< SVE floating-point serial reduction (predicated)
  AMED_AARCH64_ICLASS_sve_fp_2op_p_zd_a, //!< SVE floating-point round to integral value
  AMED_AARCH64_ICLASS_sve_fp_2op_p_zd_b_0, //!< SVE floating-point convert precision
  AMED_AARCH64_ICLASS_sve_fp_2op_p_zd_b_1, //!< SVE floating-point unary operations
  AMED_AARCH64_ICLASS_sve_fp_2op_p_zd_c, //!< SVE integer convert to floating-point
  AMED_AARCH64_ICLASS_sve_fp_2op_p_zd_d, //!< SVE floating-point convert to integer
  AMED_AARCH64_ICLASS_sve_fp_2op_p_zds, //!< SVE floating-point arithmetic (predicated)
  AMED_AARCH64_ICLASS_sve_fp_2op_u_zd, //!< SVE floating-point reciprocal estimate (unpredicated)
  AMED_AARCH64_ICLASS_sve_fp_3op_p_pd, //!< SVE floating-point compare vectors
  AMED_AARCH64_ICLASS_sve_fp_3op_p_zds_a, //!< SVE floating-point multiply-accumulate writing addend
  AMED_AARCH64_ICLASS_sve_fp_3op_p_zds_b, //!< SVE floating-point multiply-accumulate writing multiplicand
  AMED_AARCH64_ICLASS_sve_fp_3op_u_zd, //!< SVE floating-point arithmetic (unpredicated)
  AMED_AARCH64_ICLASS_sve_fp_fast_red, //!< SVE floating-point recursive reduction
  AMED_AARCH64_ICLASS_sve_fp_fcadd, //!< SVE floating-point complex add (predicated)
  AMED_AARCH64_ICLASS_sve_fp_fcmla, //!< SVE floating-point complex multiply-add (predicated)
  AMED_AARCH64_ICLASS_sve_fp_fcmla_by_indexed_elem, //!< SVE floating-point complex multiply-add (indexed)
  AMED_AARCH64_ICLASS_sve_fp_fcvt2, //!< SVE floating-point convert precision odd elements
  AMED_AARCH64_ICLASS_sve_fp_fdot, //!< SVE BFloat16 floating-point dot product
  AMED_AARCH64_ICLASS_sve_fp_fdot_by_indexed_elem, //!< SVE BFloat16 floating-point dot product (indexed)
  AMED_AARCH64_ICLASS_sve_fp_fma_by_indexed_elem, //!< SVE floating-point multiply-add (indexed)
  AMED_AARCH64_ICLASS_sve_fp_fma_long, //!< SVE floating-point multiply-add long
  AMED_AARCH64_ICLASS_sve_fp_fma_long_by_indexed_elem, //!< SVE floating-point multiply-add long (indexed)
  AMED_AARCH64_ICLASS_sve_fp_fmmla, //!< SVE floating point matrix multiply accumulate
  AMED_AARCH64_ICLASS_sve_fp_fmul_by_indexed_elem, //!< SVE floating-point multiply (indexed)
  AMED_AARCH64_ICLASS_sve_fp_ftmad, //!< SVE floating-point trig multiply-add coefficient
  AMED_AARCH64_ICLASS_sve_fp_pairwise, //!< SVE2 floating-point pairwise operations
  AMED_AARCH64_ICLASS_sve_int_arith_imm0, //!< SVE integer add/subtract immediate (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_arith_imm1, //!< SVE integer min/max immediate (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_arith_imm2, //!< SVE integer multiply immediate (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_arith_vl, //!< SVE stack frame adjustment
  AMED_AARCH64_ICLASS_sve_int_bin_cons_arit_0, //!< SVE integer add/subtract vectors (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_bin_cons_log, //!< SVE bitwise logical operations (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_bin_cons_misc_0_a, //!< SVE address generation
  AMED_AARCH64_ICLASS_sve_int_bin_cons_misc_0_b, //!< SVE floating-point trig select coefficient
  AMED_AARCH64_ICLASS_sve_int_bin_cons_misc_0_c, //!< SVE floating-point exponential accelerator
  AMED_AARCH64_ICLASS_sve_int_bin_cons_misc_0_d, //!< SVE constructive prefix (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_bin_cons_shift_a, //!< SVE bitwise shift by wide elements (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_bin_cons_shift_b, //!< SVE bitwise shift by immediate (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_bin_pred_arit_0, //!< SVE integer add/subtract vectors (predicated)
  AMED_AARCH64_ICLASS_sve_int_bin_pred_arit_1, //!< SVE integer min/max/difference (predicated)
  AMED_AARCH64_ICLASS_sve_int_bin_pred_arit_2, //!< SVE integer multiply vectors (predicated)
  AMED_AARCH64_ICLASS_sve_int_bin_pred_div, //!< SVE integer divide vectors (predicated)
  AMED_AARCH64_ICLASS_sve_int_bin_pred_log, //!< SVE bitwise logical operations (predicated)
  AMED_AARCH64_ICLASS_sve_int_bin_pred_shift_0, //!< SVE bitwise shift by immediate (predicated)
  AMED_AARCH64_ICLASS_sve_int_bin_pred_shift_1, //!< SVE bitwise shift by vector (predicated)
  AMED_AARCH64_ICLASS_sve_int_bin_pred_shift_2, //!< SVE bitwise shift by wide elements (predicated)
  AMED_AARCH64_ICLASS_sve_int_break, //!< SVE partition break condition
  AMED_AARCH64_ICLASS_sve_int_brkn, //!< SVE propagate break to next partition
  AMED_AARCH64_ICLASS_sve_int_brkp, //!< SVE propagate break from previous partition
  AMED_AARCH64_ICLASS_sve_int_cmp_0, //!< SVE integer compare vectors
  AMED_AARCH64_ICLASS_sve_int_cmp_1, //!< SVE integer compare with wide elements
  AMED_AARCH64_ICLASS_sve_int_count, //!< SVE element count
  AMED_AARCH64_ICLASS_sve_int_count_r, //!< SVE inc/dec register by predicate count
  AMED_AARCH64_ICLASS_sve_int_count_r_sat, //!< SVE saturating inc/dec register by predicate count
  AMED_AARCH64_ICLASS_sve_int_count_v, //!< SVE inc/dec vector by predicate count
  AMED_AARCH64_ICLASS_sve_int_count_v_sat, //!< SVE saturating inc/dec vector by predicate count
  AMED_AARCH64_ICLASS_sve_int_countvlv0, //!< SVE saturating inc/dec vector by element count
  AMED_AARCH64_ICLASS_sve_int_countvlv1, //!< SVE inc/dec vector by element count
  AMED_AARCH64_ICLASS_sve_int_cterm, //!< SVE conditionally terminate scalars
  AMED_AARCH64_ICLASS_sve_int_dup_fpimm, //!< SVE broadcast floating-point immediate (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_dup_fpimm_pred, //!< SVE copy floating-point immediate (predicated)
  AMED_AARCH64_ICLASS_sve_int_dup_imm, //!< SVE broadcast integer immediate (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_dup_imm_pred, //!< SVE copy integer immediate (predicated)
  AMED_AARCH64_ICLASS_sve_int_dup_mask_imm, //!< SVE broadcast bitmask immediate
  AMED_AARCH64_ICLASS_sve_int_index_ii, //!< SVE index generation (immediate start, immediate increment)
  AMED_AARCH64_ICLASS_sve_int_index_ir, //!< SVE index generation (immediate start, register increment)
  AMED_AARCH64_ICLASS_sve_int_index_ri, //!< SVE index generation (register start, immediate increment)
  AMED_AARCH64_ICLASS_sve_int_index_rr, //!< SVE index generation (register start, register increment)
  AMED_AARCH64_ICLASS_sve_int_log_imm, //!< SVE bitwise logical with immediate (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_mladdsub_vvv_pred, //!< SVE integer multiply-add writing multiplicand (predicated)
  AMED_AARCH64_ICLASS_sve_int_mlas_vvv_pred, //!< SVE integer multiply-accumulate writing addend (predicated)
  AMED_AARCH64_ICLASS_sve_int_movprfx_pred, //!< SVE constructive prefix (predicated)
  AMED_AARCH64_ICLASS_sve_int_mul_b, //!< SVE2 integer multiply vectors (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_pcount_pred, //!< SVE predicate count
  AMED_AARCH64_ICLASS_sve_int_perm_bin_long_perm_zz, //!< SVE permute vector segments
  AMED_AARCH64_ICLASS_sve_int_perm_bin_perm_pp, //!< SVE permute predicate elements
  AMED_AARCH64_ICLASS_sve_int_perm_bin_perm_zz, //!< SVE permute vector elements
  AMED_AARCH64_ICLASS_sve_int_perm_clast_rz, //!< SVE conditionally extract element to general register
  AMED_AARCH64_ICLASS_sve_int_perm_clast_vz, //!< SVE conditionally extract element to SIMD&FP scalar
  AMED_AARCH64_ICLASS_sve_int_perm_clast_zz, //!< SVE conditionally broadcast element to vector
  AMED_AARCH64_ICLASS_sve_int_perm_compact, //!< SVE compress active elements
  AMED_AARCH64_ICLASS_sve_int_perm_cpy_r, //!< SVE copy general register to vector (predicated)
  AMED_AARCH64_ICLASS_sve_int_perm_cpy_v, //!< SVE copy SIMD&FP scalar register to vector (predicated)
  AMED_AARCH64_ICLASS_sve_int_perm_dup_i, //!< SVE broadcast indexed element
  AMED_AARCH64_ICLASS_sve_int_perm_dup_r, //!< SVE broadcast general register
  AMED_AARCH64_ICLASS_sve_int_perm_extract_i, //!< SVE extract vector (immediate offset, destructive)
  AMED_AARCH64_ICLASS_sve_int_perm_insrs, //!< SVE insert general register
  AMED_AARCH64_ICLASS_sve_int_perm_insrv, //!< SVE insert SIMD&FP scalar register
  AMED_AARCH64_ICLASS_sve_int_perm_last_r, //!< SVE extract element to general register
  AMED_AARCH64_ICLASS_sve_int_perm_last_v, //!< SVE extract element to SIMD&FP scalar register
  AMED_AARCH64_ICLASS_sve_int_perm_punpk, //!< SVE unpack predicate elements
  AMED_AARCH64_ICLASS_sve_int_perm_rev, //!< SVE reverse within elements
  AMED_AARCH64_ICLASS_sve_int_perm_reverse_p, //!< SVE reverse predicate elements
  AMED_AARCH64_ICLASS_sve_int_perm_reverse_z, //!< SVE reverse vector elements
  AMED_AARCH64_ICLASS_sve_int_perm_splice, //!< SVE vector splice (destructive)
  AMED_AARCH64_ICLASS_sve_int_perm_tbl, //!< SVE table lookup
  AMED_AARCH64_ICLASS_sve_int_perm_tbl_3src, //!< SVE table lookup (three sources)
  AMED_AARCH64_ICLASS_sve_int_perm_unpk, //!< SVE unpack vector elements
  AMED_AARCH64_ICLASS_sve_int_pfalse, //!< SVE predicate zero
  AMED_AARCH64_ICLASS_sve_int_pfirst, //!< SVE predicate first active
  AMED_AARCH64_ICLASS_sve_int_pnext, //!< SVE predicate next active
  AMED_AARCH64_ICLASS_sve_int_pred_log, //!< SVE predicate logical operations
  AMED_AARCH64_ICLASS_sve_int_pred_pattern_a, //!< SVE inc/dec register by element count
  AMED_AARCH64_ICLASS_sve_int_pred_pattern_b, //!< SVE saturating inc/dec register by element count
  AMED_AARCH64_ICLASS_sve_int_ptest, //!< SVE predicate test
  AMED_AARCH64_ICLASS_sve_int_ptrue, //!< SVE predicate initialize
  AMED_AARCH64_ICLASS_sve_int_rdffr, //!< SVE predicate read from FFR (predicated)
  AMED_AARCH64_ICLASS_sve_int_rdffr_2, //!< SVE predicate read from FFR (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_read_vl_a, //!< SVE stack frame size
  AMED_AARCH64_ICLASS_sve_int_reduce_0, //!< SVE integer add reduction (predicated)
  AMED_AARCH64_ICLASS_sve_int_reduce_1, //!< SVE integer min/max reduction (predicated)
  AMED_AARCH64_ICLASS_sve_int_reduce_2, //!< SVE bitwise logical reduction (predicated)
  AMED_AARCH64_ICLASS_sve_int_rotate_imm, //!< sve_int_rotate_imm
  AMED_AARCH64_ICLASS_sve_int_scmp_vi, //!< SVE integer compare with signed immediate
  AMED_AARCH64_ICLASS_sve_int_sel_vvv, //!< SVE select vector elements (predicated)
  AMED_AARCH64_ICLASS_sve_int_setffr, //!< SVE FFR initialise
  AMED_AARCH64_ICLASS_sve_int_sqdmulh, //!< SVE2 signed saturating doubling multiply high (unpredicated)
  AMED_AARCH64_ICLASS_sve_int_tern_log, //!< SVE2 bitwise ternary operations
  AMED_AARCH64_ICLASS_sve_int_ucmp_vi, //!< SVE integer compare with unsigned immediate
  AMED_AARCH64_ICLASS_sve_int_un_pred_arit_0, //!< SVE integer unary operations (predicated)
  AMED_AARCH64_ICLASS_sve_int_un_pred_arit_1, //!< SVE bitwise unary operations (predicated)
  AMED_AARCH64_ICLASS_sve_int_while_rr, //!< SVE integer compare scalar count and limit
  AMED_AARCH64_ICLASS_sve_int_whilenc, //!< SVE pointer conflict compare
  AMED_AARCH64_ICLASS_sve_int_wrffr, //!< SVE FFR write from predicate
  AMED_AARCH64_ICLASS_sve_intx_aba, //!< SVE2 integer absolute difference and accumulate
  AMED_AARCH64_ICLASS_sve_intx_aba_long, //!< SVE2 integer absolute difference and accumulate long
  AMED_AARCH64_ICLASS_sve_intx_accumulate_long_pairs, //!< SVE2 integer pairwise add and accumulate long
  AMED_AARCH64_ICLASS_sve_intx_adc_long, //!< SVE2 integer add/subtract long with carry
  AMED_AARCH64_ICLASS_sve_intx_arith_binary_pairs, //!< SVE2 integer pairwise arithmetic
  AMED_AARCH64_ICLASS_sve_intx_arith_narrow, //!< SVE2 integer add/subtract narrow high part
  AMED_AARCH64_ICLASS_sve_intx_bin_pred_shift_sat_round, //!< SVE2 saturating/rounding bitwise shift left (predicated)
  AMED_AARCH64_ICLASS_sve_intx_cadd, //!< SVE2 complex integer add
  AMED_AARCH64_ICLASS_sve_intx_cdot, //!< SVE2 complex integer dot product
  AMED_AARCH64_ICLASS_sve_intx_cdot_by_indexed_elem, //!< SVE2 complex integer dot product (indexed)
  AMED_AARCH64_ICLASS_sve_intx_clong, //!< SVE2 integer add/subtract interleaved long
  AMED_AARCH64_ICLASS_sve_intx_cmla, //!< SVE2 complex integer multiply-add
  AMED_AARCH64_ICLASS_sve_intx_cmla_by_indexed_elem, //!< SVE2 complex integer multiply-add (indexed)
  AMED_AARCH64_ICLASS_sve_intx_cons_arith_long, //!< SVE2 integer add/subtract long
  AMED_AARCH64_ICLASS_sve_intx_cons_arith_wide, //!< SVE2 integer add/subtract wide
  AMED_AARCH64_ICLASS_sve_intx_cons_mul_long, //!< SVE2 integer multiply long
  AMED_AARCH64_ICLASS_sve_intx_dot, //!< SVE integer dot product (unpredicated)
  AMED_AARCH64_ICLASS_sve_intx_dot_by_indexed_elem, //!< SVE integer dot product (indexed)
  AMED_AARCH64_ICLASS_sve_intx_eorx, //!< SVE2 bitwise exclusive-or interleaved
  AMED_AARCH64_ICLASS_sve_intx_extract_narrow, //!< SVE2 saturating extract narrow
  AMED_AARCH64_ICLASS_sve_intx_histcnt, //!< SVE2 histogram generation (vector)
  AMED_AARCH64_ICLASS_sve_intx_histseg, //!< SVE2 histogram generation  (segment)
  AMED_AARCH64_ICLASS_sve_intx_match, //!< SVE2 character match
  AMED_AARCH64_ICLASS_sve_intx_mixed_dot, //!< SVE mixed sign dot product
  AMED_AARCH64_ICLASS_sve_intx_mixed_dot_by_indexed_elem, //!< SVE mixed sign dot product (indexed)
  AMED_AARCH64_ICLASS_sve_intx_mla_by_indexed_elem, //!< SVE2 integer multiply-add (indexed)
  AMED_AARCH64_ICLASS_sve_intx_mla_long_by_indexed_elem, //!< SVE2 integer multiply-add long (indexed)
  AMED_AARCH64_ICLASS_sve_intx_mlal_long, //!< SVE2 integer multiply-add long
  AMED_AARCH64_ICLASS_sve_intx_mmla, //!< SVE integer matrix multiply accumulate
  AMED_AARCH64_ICLASS_sve_intx_mul_by_indexed_elem, //!< SVE2 integer multiply (indexed)
  AMED_AARCH64_ICLASS_sve_intx_mul_long_by_indexed_elem, //!< SVE2 integer multiply long (indexed)
  AMED_AARCH64_ICLASS_sve_intx_perm_bit, //!< SVE2 bitwise permute
  AMED_AARCH64_ICLASS_sve_intx_perm_extract_i, //!< SVE2 extract vector (immediate offset, constructive)
  AMED_AARCH64_ICLASS_sve_intx_perm_splice, //!< SVE2 vector splice (constructive)
  AMED_AARCH64_ICLASS_sve_intx_pred_arith_binary, //!< SVE2 integer halving add/subtract (predicated)
  AMED_AARCH64_ICLASS_sve_intx_pred_arith_binary_sat, //!< SVE2 saturating add/subtract
  AMED_AARCH64_ICLASS_sve_intx_pred_arith_unary, //!< SVE2 integer unary operations (predicated)
  AMED_AARCH64_ICLASS_sve_intx_qdmla_long_by_indexed_elem, //!< SVE2 saturating multiply-add (indexed)
  AMED_AARCH64_ICLASS_sve_intx_qdmlal_long, //!< SVE2 saturating  multiply-add long
  AMED_AARCH64_ICLASS_sve_intx_qdmlalbt, //!< SVE2 saturating multiply-add interleaved long
  AMED_AARCH64_ICLASS_sve_intx_qdmul_long_by_indexed_elem, //!< SVE2 saturating multiply (indexed)
  AMED_AARCH64_ICLASS_sve_intx_qdmulh_by_indexed_elem, //!< SVE2 saturating  multiply high (indexed)
  AMED_AARCH64_ICLASS_sve_intx_qrdcmla_by_indexed_elem, //!< SVE2 complex saturating multiply-add (indexed)
  AMED_AARCH64_ICLASS_sve_intx_qrdmlah, //!< SVE2 saturating multiply-add high
  AMED_AARCH64_ICLASS_sve_intx_qrdmlah_by_indexed_elem, //!< SVE2 saturating multiply-add high (indexed)
  AMED_AARCH64_ICLASS_sve_intx_shift_insert, //!< SVE2 bitwise shift and insert
  AMED_AARCH64_ICLASS_sve_intx_shift_long, //!< SVE2 bitwise shift left long
  AMED_AARCH64_ICLASS_sve_intx_shift_narrow, //!< SVE2 bitwise shift right narrow
  AMED_AARCH64_ICLASS_sve_intx_sra, //!< SVE2 bitwise shift right and accumulate
  AMED_AARCH64_ICLASS_sve_mem_32b_fill, //!< SVE load vector register
  AMED_AARCH64_ICLASS_sve_mem_32b_gld_sv_a, //!< SVE 32-bit gather load halfwords (scalar plus 32-bit scaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_32b_gld_sv_b, //!< SVE 32-bit gather load words (scalar plus 32-bit scaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_32b_gld_vi, //!< SVE 32-bit gather load (vector plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_32b_gld_vs, //!< SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_32b_gldnt_vs, //!< SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_32b_pfill, //!< SVE load predicate register
  AMED_AARCH64_ICLASS_sve_mem_32b_prfm_sv, //!< SVE 32-bit gather prefetch (scalar plus 32-bit scaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_32b_prfm_vi, //!< SVE 32-bit gather prefetch (vector plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_64b_gld_sv, //!< SVE 64-bit gather load (scalar plus 32-bit unpacked scaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_64b_gld_sv2, //!< SVE 64-bit gather load (scalar plus 64-bit scaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_64b_gld_vi, //!< SVE 64-bit gather load (vector plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_64b_gld_vs, //!< SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_64b_gld_vs2, //!< SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_64b_gldnt_vs, //!< SVE2 64-bit gather non-temporal load (scalar plus unpacked 32-bit unscaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_64b_prfm_sv, //!< SVE 64-bit gather prefetch (scalar plus unpacked 32-bit scaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_64b_prfm_sv2, //!< SVE 64-bit gather prefetch (scalar plus 64-bit scaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_64b_prfm_vi, //!< SVE 64-bit gather prefetch (vector plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_cld_si, //!< SVE contiguous load (scalar plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_cld_ss, //!< SVE contiguous load (scalar plus scalar)
  AMED_AARCH64_ICLASS_sve_mem_cldff_ss, //!< SVE contiguous first-fault load (scalar plus scalar)
  AMED_AARCH64_ICLASS_sve_mem_cldnf_si, //!< SVE contiguous non-fault load (scalar plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_cldnt_si, //!< SVE contiguous non-temporal load (scalar plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_cldnt_ss, //!< SVE contiguous non-temporal load (scalar plus scalar)
  AMED_AARCH64_ICLASS_sve_mem_cst_si, //!< SVE contiguous store (scalar plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_cst_ss, //!< SVE contiguous store (scalar plus scalar)
  AMED_AARCH64_ICLASS_sve_mem_cstnt_si, //!< SVE contiguous non-temporal store (scalar plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_cstnt_ss, //!< SVE contiguous non-temporal store (scalar plus scalar)
  AMED_AARCH64_ICLASS_sve_mem_eld_si, //!< SVE load multiple structures (scalar plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_eld_ss, //!< SVE load multiple structures (scalar plus scalar)
  AMED_AARCH64_ICLASS_sve_mem_est_si, //!< SVE store multiple structures (scalar plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_est_ss, //!< SVE store multiple structures (scalar plus scalar)
  AMED_AARCH64_ICLASS_sve_mem_ld_dup, //!< SVE load and broadcast element
  AMED_AARCH64_ICLASS_sve_mem_ldqr_si, //!< SVE load and broadcast quadword (scalar plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_ldqr_ss, //!< SVE load and broadcast quadword (scalar plus scalar)
  AMED_AARCH64_ICLASS_sve_mem_prfm_si, //!< SVE contiguous prefetch (scalar plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_prfm_ss, //!< SVE contiguous prefetch (scalar plus scalar)
  AMED_AARCH64_ICLASS_sve_mem_pspill, //!< SVE store predicate register
  AMED_AARCH64_ICLASS_sve_mem_spill, //!< SVE store vector register
  AMED_AARCH64_ICLASS_sve_mem_sst_sv2, //!< SVE 64-bit scatter store (scalar plus 64-bit scaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_sst_sv_a, //!< SVE 64-bit scatter store (scalar plus unpacked 32-bit scaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_sst_sv_b, //!< SVE 32-bit scatter store (scalar plus 32-bit scaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_sst_vi_a, //!< SVE 64-bit scatter store (vector plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_sst_vi_b, //!< SVE 32-bit scatter store (vector plus immediate)
  AMED_AARCH64_ICLASS_sve_mem_sst_vs2, //!< SVE 64-bit scatter store (scalar plus 64-bit unscaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_sst_vs_a, //!< SVE 64-bit scatter store (scalar plus unpacked 32-bit unscaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_sst_vs_b, //!< SVE 32-bit scatter store (scalar plus 32-bit unscaled offsets)
  AMED_AARCH64_ICLASS_sve_mem_sstnt_32b_vs, //!< SVE2 32-bit scatter non-temporal store (vector plus scalar)
  AMED_AARCH64_ICLASS_sve_mem_sstnt_64b_vs, //!< SVE2 64-bit scatter non-temporal store (vector plus scalar)
} amed_aarch64_iclass;

#define AMED_AARCH64_PSTATEFIELD_MAX_TEXT_LENGTH (7 + 1)

typedef enum _amed_aarch64_pstatefield
{
  AMED_AARCH64_PSTATEFIELD_NONE,
  AMED_AARCH64_PSTATEFIELD_DAIFClr,
  AMED_AARCH64_PSTATEFIELD_DAIFSet,
  AMED_AARCH64_PSTATEFIELD_DIT,
  AMED_AARCH64_PSTATEFIELD_PAN,
  AMED_AARCH64_PSTATEFIELD_SPSel,
  AMED_AARCH64_PSTATEFIELD_SSBS,
  AMED_AARCH64_PSTATEFIELD_TCO,
  AMED_AARCH64_PSTATEFIELD_UAO,
} amed_aarch64_pstatefield;

#define AMED_AARCH64_GROUP_MAX_TEXT_LENGTH (31 + 1)

typedef enum _amed_aarch64_group
{
  AMED_AARCH64_GROUP_NONE,
  AMED_AARCH64_GROUP_invalid, //!< invalid
  AMED_AARCH64_GROUP_control, //!< Branches, Exception Generating and System instructions
  AMED_AARCH64_GROUP_dpimm, //!< Data Processing -- Immediate
  AMED_AARCH64_GROUP_dpreg, //!< Data Processing -- Register
  AMED_AARCH64_GROUP_reserved, //!< Reserved
  AMED_AARCH64_GROUP_ldst, //!< Loads and Stores
  AMED_AARCH64_GROUP_simd_dp, //!< Data Processing -- Scalar Floating-Point and Advanced SIMD
  AMED_AARCH64_GROUP_sve, //!< SVE encodings
  AMED_AARCH64_GROUP_sve_alloca, //!< SVE Stack Allocation
  AMED_AARCH64_GROUP_sve_cmpgpr, //!< SVE Integer Compare - Scalars
  AMED_AARCH64_GROUP_sve_cmpvec, //!< SVE Integer Compare - Vectors
  AMED_AARCH64_GROUP_sve_countelt, //!< SVE Element Count
  AMED_AARCH64_GROUP_sve_fp_cmpzero, //!< SVE Floating Point Compare - with Zero
  AMED_AARCH64_GROUP_sve_fp_fma, //!< SVE Floating Point Multiply-Add
  AMED_AARCH64_GROUP_sve_fp_fma_long, //!< SVE Floating Point Widening Multiply-Add
  AMED_AARCH64_GROUP_sve_fp_fma_long_by_indexed_elem, //!< SVE Floating Point Widening Multiply-Add - Indexed
  AMED_AARCH64_GROUP_sve_fp_pred, //!< SVE Floating Point Arithmetic - Predicated
  AMED_AARCH64_GROUP_sve_fp_unary, //!< SVE Floating Point Unary Operations - Predicated
  AMED_AARCH64_GROUP_sve_fp_unary_unpred, //!< SVE Floating Point Unary Operations - Unpredicated
  AMED_AARCH64_GROUP_sve_index, //!< SVE Index Generation
  AMED_AARCH64_GROUP_sve_int_muladd_pred, //!< SVE Integer Multiply-Add - Predicated
  AMED_AARCH64_GROUP_sve_int_pred_bin, //!< SVE Integer Binary Arithmetic - Predicated
  AMED_AARCH64_GROUP_sve_int_pred_red, //!< SVE Integer Reduction
  AMED_AARCH64_GROUP_sve_int_pred_shift, //!< SVE Bitwise Shift - Predicated
  AMED_AARCH64_GROUP_sve_int_pred_un, //!< SVE Integer Unary Arithmetic - Predicated
  AMED_AARCH64_GROUP_sve_int_unpred_arit_b, //!< SVE2 Integer Multiply - Unpredicated
  AMED_AARCH64_GROUP_sve_int_unpred_logical, //!< SVE Bitwise Logical - Unpredicated
  AMED_AARCH64_GROUP_sve_int_unpred_misc, //!< SVE Integer Misc - Unpredicated
  AMED_AARCH64_GROUP_sve_int_unpred_shift, //!< SVE Bitwise Shift - Unpredicated
  AMED_AARCH64_GROUP_sve_intx_acc, //!< SVE2 Accumulate
  AMED_AARCH64_GROUP_sve_intx_by_indexed_elem, //!< SVE Multiply - Indexed
  AMED_AARCH64_GROUP_sve_intx_cons_widening, //!< SVE2 Widening Integer Arithmetic
  AMED_AARCH64_GROUP_sve_intx_constructive, //!< SVE Misc
  AMED_AARCH64_GROUP_sve_intx_crypto, //!< SVE2 Crypto Extensions
  AMED_AARCH64_GROUP_sve_intx_histseg, //!< SVE2 Histogram Computation - Segment
  AMED_AARCH64_GROUP_sve_intx_muladd_unpred, //!< SVE Integer Multiply-Add - Unpredicated
  AMED_AARCH64_GROUP_sve_intx_narrowing, //!< SVE2 Narrowing
  AMED_AARCH64_GROUP_sve_intx_predicated, //!< SVE2 Integer - Predicated
  AMED_AARCH64_GROUP_sve_maskimm, //!< SVE Bitwise Immediate
  AMED_AARCH64_GROUP_sve_mem32, //!< SVE Memory - 32-bit Gather and Unsized Contiguous
  AMED_AARCH64_GROUP_sve_mem64, //!< SVE Memory - 64-bit Gather
  AMED_AARCH64_GROUP_sve_memcld, //!< SVE Memory - Contiguous Load
  AMED_AARCH64_GROUP_sve_memst_cs, //!< SVE Memory - Contiguous Store and Unsized Contiguous
  AMED_AARCH64_GROUP_sve_memst_nt, //!< SVE Memory - Non-temporal and Multi-register Store
  AMED_AARCH64_GROUP_sve_memst_si, //!< SVE Memory - Contiguous Store with Immediate Offset
  AMED_AARCH64_GROUP_sve_memst_ss, //!< SVE Memory - Scatter with Optional Sign Extend
  AMED_AARCH64_GROUP_sve_memst_ss2, //!< SVE Memory - Scatter
  AMED_AARCH64_GROUP_sve_perm_extract, //!< SVE Permute Vector - Extract
  AMED_AARCH64_GROUP_sve_perm_pred, //!< SVE Permute Vector - Predicated
  AMED_AARCH64_GROUP_sve_perm_predicates, //!< SVE Permute Predicate
  AMED_AARCH64_GROUP_sve_perm_unpred, //!< SVE Permute Vector - Unpredicated
  AMED_AARCH64_GROUP_sve_pred_count_b, //!< SVE Inc/Dec by Predicate Count
  AMED_AARCH64_GROUP_sve_pred_gen_b, //!< SVE Propagate Break
  AMED_AARCH64_GROUP_sve_pred_gen_c, //!< SVE Partition Break
  AMED_AARCH64_GROUP_sve_pred_gen_d, //!< SVE Predicate Misc
  AMED_AARCH64_GROUP_sve_pred_wrffr, //!< SVE Write FFR
  AMED_AARCH64_GROUP_sve_wideimm_pred, //!< SVE Integer Wide Immediate - Predicated
  AMED_AARCH64_GROUP_sve_wideimm_unpred, //!< SVE Integer Wide Immediate - Unpredicated
} amed_aarch64_group;

#define AMED_AARCH64_SYMBOL_MAX_TEXT_LENGTH (15 + 1)

typedef enum _amed_aarch64_symbol
{
  AMED_AARCH64_SYMBOL_NONE,
  AMED_AARCH64_SYMBOL_amount,
  AMED_AARCH64_SYMBOL_at_op,
  AMED_AARCH64_SYMBOL_cond,
  AMED_AARCH64_SYMBOL_const,
  AMED_AARCH64_SYMBOL_dc_op,
  AMED_AARCH64_SYMBOL_extend,
  AMED_AARCH64_SYMBOL_fbits_right,
  AMED_AARCH64_SYMBOL_ic_op,
  AMED_AARCH64_SYMBOL_imm,
  AMED_AARCH64_SYMBOL_imm1,
  AMED_AARCH64_SYMBOL_imm2,
  AMED_AARCH64_SYMBOL_imm6,
  AMED_AARCH64_SYMBOL_immr,
  AMED_AARCH64_SYMBOL_imms,
  AMED_AARCH64_SYMBOL_label,
  AMED_AARCH64_SYMBOL_aimm,
  AMED_AARCH64_SYMBOL_vfpimm,
  AMED_AARCH64_SYMBOL_advimm,
  AMED_AARCH64_SYMBOL_imm8,
  AMED_AARCH64_SYMBOL_lsb,
  AMED_AARCH64_SYMBOL_mask,
  AMED_AARCH64_SYMBOL_mod,
  AMED_AARCH64_SYMBOL_nzcv,
  AMED_AARCH64_SYMBOL_op1,
  AMED_AARCH64_SYMBOL_op2,
  AMED_AARCH64_SYMBOL_WideImmInverted,
  AMED_AARCH64_SYMBOL_WideImmAlias,
  AMED_AARCH64_SYMBOL_option,
  AMED_AARCH64_SYMBOL_pattern,
  AMED_AARCH64_SYMBOL_pimm,
  AMED_AARCH64_SYMBOL_prfop,
  AMED_AARCH64_SYMBOL_pstatefield,
  AMED_AARCH64_SYMBOL_rotate,
  AMED_AARCH64_SYMBOL_shift,
  AMED_AARCH64_SYMBOL_shift_left,
  AMED_AARCH64_SYMBOL_shift_right,
  AMED_AARCH64_SYMBOL_shifter,
  AMED_AARCH64_SYMBOL_simm,
  AMED_AARCH64_SYMBOL_systemreg,
  AMED_AARCH64_SYMBOL_targets,
  AMED_AARCH64_SYMBOL_tlbi_op,
  AMED_AARCH64_SYMBOL_uimm4,
  AMED_AARCH64_SYMBOL_uimm6,
  AMED_AARCH64_SYMBOL_width,
  AMED_AARCH64_SYMBOL_GPR32,
  AMED_AARCH64_SYMBOL_GPR64,
  AMED_AARCH64_SYMBOL_SIMD8,
  AMED_AARCH64_SYMBOL_SIMD16,
  AMED_AARCH64_SYMBOL_SIMD32,
  AMED_AARCH64_SYMBOL_SIMD64,
  AMED_AARCH64_SYMBOL_SIMD128,
  AMED_AARCH64_SYMBOL_VECREG,
  AMED_AARCH64_SYMBOL_PRDREG,
  AMED_AARCH64_SYMBOL_SVEREG,
  AMED_AARCH64_SYMBOL_Bd,
  AMED_AARCH64_SYMBOL_Bdn,
  AMED_AARCH64_SYMBOL_Bm,
  AMED_AARCH64_SYMBOL_Bn,
  AMED_AARCH64_SYMBOL_Bt,
  AMED_AARCH64_SYMBOL_Cm,
  AMED_AARCH64_SYMBOL_Cn,
  AMED_AARCH64_SYMBOL_Da,
  AMED_AARCH64_SYMBOL_Dd,
  AMED_AARCH64_SYMBOL_Ddn,
  AMED_AARCH64_SYMBOL_Dm,
  AMED_AARCH64_SYMBOL_Dn,
  AMED_AARCH64_SYMBOL_Dt,
  AMED_AARCH64_SYMBOL_Dt1,
  AMED_AARCH64_SYMBOL_Dt2,
  AMED_AARCH64_SYMBOL_Ha,
  AMED_AARCH64_SYMBOL_Hd,
  AMED_AARCH64_SYMBOL_Hdn,
  AMED_AARCH64_SYMBOL_Hm,
  AMED_AARCH64_SYMBOL_Hn,
  AMED_AARCH64_SYMBOL_Ht,
  AMED_AARCH64_SYMBOL_Pd,
  AMED_AARCH64_SYMBOL_Pdm,
  AMED_AARCH64_SYMBOL_Pdn,
  AMED_AARCH64_SYMBOL_Pg,
  AMED_AARCH64_SYMBOL_Pm,
  AMED_AARCH64_SYMBOL_Pn,
  AMED_AARCH64_SYMBOL_Pt,
  AMED_AARCH64_SYMBOL_Qd,
  AMED_AARCH64_SYMBOL_Qn,
  AMED_AARCH64_SYMBOL_Qt,
  AMED_AARCH64_SYMBOL_Qt1,
  AMED_AARCH64_SYMBOL_Qt2,
  AMED_AARCH64_SYMBOL_Sa,
  AMED_AARCH64_SYMBOL_Sd,
  AMED_AARCH64_SYMBOL_Sdn,
  AMED_AARCH64_SYMBOL_Sm,
  AMED_AARCH64_SYMBOL_Sn,
  AMED_AARCH64_SYMBOL_St,
  AMED_AARCH64_SYMBOL_St1,
  AMED_AARCH64_SYMBOL_St2,
  AMED_AARCH64_SYMBOL_Va,
  AMED_AARCH64_SYMBOL_Vd,
  AMED_AARCH64_SYMBOL_Vm,
  AMED_AARCH64_SYMBOL_Vn,
  AMED_AARCH64_SYMBOL_Vt,
  AMED_AARCH64_SYMBOL_Wa,
  AMED_AARCH64_SYMBOL_Wd,
  AMED_AARCH64_SYMBOL_Wdn,
  AMED_AARCH64_SYMBOL_Wm,
  AMED_AARCH64_SYMBOL_Wn,
  AMED_AARCH64_SYMBOL_Ws,
  AMED_AARCH64_SYMBOL_WsPair,
  AMED_AARCH64_SYMBOL_Wt,
  AMED_AARCH64_SYMBOL_Wt1,
  AMED_AARCH64_SYMBOL_Wt2,
  AMED_AARCH64_SYMBOL_WtPair,
  AMED_AARCH64_SYMBOL_Xa,
  AMED_AARCH64_SYMBOL_Xd,
  AMED_AARCH64_SYMBOL_Xdn,
  AMED_AARCH64_SYMBOL_Xm,
  AMED_AARCH64_SYMBOL_Xn,
  AMED_AARCH64_SYMBOL_Xs,
  AMED_AARCH64_SYMBOL_XsPair,
  AMED_AARCH64_SYMBOL_Xt,
  AMED_AARCH64_SYMBOL_Xt1,
  AMED_AARCH64_SYMBOL_Xt2,
  AMED_AARCH64_SYMBOL_XtPair,
  AMED_AARCH64_SYMBOL_ZM,
  AMED_AARCH64_SYMBOL_Za,
  AMED_AARCH64_SYMBOL_Zd,
  AMED_AARCH64_SYMBOL_Zda,
  AMED_AARCH64_SYMBOL_Zdn,
  AMED_AARCH64_SYMBOL_Zk,
  AMED_AARCH64_SYMBOL_Zm,
  AMED_AARCH64_SYMBOL_Zn,
  AMED_AARCH64_SYMBOL_Zn1,
  AMED_AARCH64_SYMBOL_Zt,
  AMED_AARCH64_SYMBOL_Zt1,
} amed_aarch64_symbol;

#define AMED_AARCH64_NODE_TYPE_MAX_TEXT_LENGTH (11 + 1)

typedef enum _amed_aarch64_node_type
{
  AMED_AARCH64_NODE_TYPE_NONE,
  AMED_AARCH64_NODE_TYPE_AT_OP,
  AMED_AARCH64_NODE_TYPE_DC_OP,
  AMED_AARCH64_NODE_TYPE_IC_OP,
  AMED_AARCH64_NODE_TYPE_TLBI_OP,
  AMED_AARCH64_NODE_TYPE_SYNC_OP,
  AMED_AARCH64_NODE_TYPE_CTX_OP,
  AMED_AARCH64_NODE_TYPE_PRF_OP,
  AMED_AARCH64_NODE_TYPE_BTI_OP,
  AMED_AARCH64_NODE_TYPE_PSTATEFIELD,
  AMED_AARCH64_NODE_TYPE_BARRIER,
  AMED_AARCH64_NODE_TYPE_COND,
  AMED_AARCH64_NODE_TYPE_INVCOND,
  AMED_AARCH64_NODE_TYPE_BASE,
  AMED_AARCH64_NODE_TYPE_VBASE,
  AMED_AARCH64_NODE_TYPE_EBASE,
  AMED_AARCH64_NODE_TYPE_REG,
  AMED_AARCH64_NODE_TYPE_REGSH,
  AMED_AARCH64_NODE_TYPE_VREG,
  AMED_AARCH64_NODE_TYPE_EREG,
  AMED_AARCH64_NODE_TYPE_PREG,
  AMED_AARCH64_NODE_TYPE_REGOFF,
  AMED_AARCH64_NODE_TYPE_REGOFFSH,
  AMED_AARCH64_NODE_TYPE_VREGOFF,
  AMED_AARCH64_NODE_TYPE_VREGOFFSH,
  AMED_AARCH64_NODE_TYPE_VDS,
  AMED_AARCH64_NODE_TYPE_VDT,
  AMED_AARCH64_NODE_TYPE_VLIST,
  AMED_AARCH64_NODE_TYPE_ELIST,
  AMED_AARCH64_NODE_TYPE_COUNT,
  AMED_AARCH64_NODE_TYPE_IDX,
  AMED_AARCH64_NODE_TYPE_SHIFTER,
  AMED_AARCH64_NODE_TYPE_SHIFT,
  AMED_AARCH64_NODE_TYPE_EXTEND,
  AMED_AARCH64_NODE_TYPE_AMOUNT,
  AMED_AARCH64_NODE_TYPE_PATTERN,
  AMED_AARCH64_NODE_TYPE_PATTERNSH,
  AMED_AARCH64_NODE_TYPE_FPIMM,
  AMED_AARCH64_NODE_TYPE_IMM,
  AMED_AARCH64_NODE_TYPE_IMMSH,
  AMED_AARCH64_NODE_TYPE_IMMOFF,
  AMED_AARCH64_NODE_TYPE_IMMOFFSH,
  AMED_AARCH64_NODE_TYPE_LABEL,
  AMED_AARCH64_NODE_TYPE_ADDR,
  AMED_AARCH64_NODE_TYPE_MEM,
  AMED_AARCH64_NODE_TYPE_SZ,
  AMED_AARCH64_NODE_TYPE_CSPACE,
  AMED_AARCH64_NODE_TYPE_SYSREG,
} amed_aarch64_node_type;

